Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel pan@semihalf.com --- .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++++++++++++++ arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi new file mode 100644 index 0000000000..365e05100a --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10-u-boot.dtsi" + +/ { + chosen { + firmware-loader = <&fs_loader0>; + }; + + fs_loader0: fs-loader { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + phandlepart = <&mmc 1>; + }; +}; + +&atsha204a { + u-boot,dm-pre-reloc; +}; + +&fpga_mgr { + u-boot,dm-pre-reloc; + altr,bitstream = "fpga.itb"; +}; + +&i2c1 { + u-boot,dm-pre-reloc; +}; + +&main_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&peri_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_free_clk { + u-boot,dm-pre-reloc; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi new file mode 100644 index 0000000000..fee1fc39bb --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10.dtsi" + +/ { + aliases { + ethernet0 = &gmac0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&phy3>; + + max-frame-size = <3800>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy3: ethernet-phy@3 { + reg = <3>; + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&i2c1 { + atsha204a: atsha204a@64 { + compatible = "atmel,atsha204a"; + reg = <0x64>; + }; + + isl12022: isl12022@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +&mmc { + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&osc1 { + clock-frequency = <33330000>; +};

Add handoff headers for the Google Chameleonv3 variants: 480-2 and 270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel pan@semihalf.com --- ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++++++++++++++++++ ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++++++++++++++++++ 2 files changed, 610 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h new file mode 100644 index 0000000000..9d8f4a0dd3 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 60000000 +#define EMAC0_CLK_HZ 250000000 +#define EMAC1_CLK_HZ 250000000 +#define EMAC2_CLK_HZ 250000000 +#define EOSC1_CLK_HZ 33330000 +#define F2H_FREE_CLK_HZ 200000000 +#define H2F_USER0_CLK_HZ 200000000 +#define H2F_USER1_CLK_HZ 100000000 +#define L3_MAIN_FREE_CLK_HZ 200000000 +#define SDMMC_CLK_HZ 200000000 +#define TPIU_CLK_HZ 100000000 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_CNT 7 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 15 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1584 +#define PERPLLGRP_CNTR2CLK_CNT 5 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 14 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 374 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1485 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 7 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 0 +#define CONFIG_IO_12_PD_DRV_STRG 0 +#define CONFIG_IO_12_PD_SLW_RT 0 +#define CONFIG_IO_12_PU_DRV_STRG 0 +#define CONFIG_IO_12_PU_SLW_RT 0 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 0 +#define CONFIG_IO_13_PD_DRV_STRG 0 +#define CONFIG_IO_13_PD_SLW_RT 0 +#define CONFIG_IO_13_PU_DRV_STRG 0 +#define CONFIG_IO_13_PU_SLW_RT 0 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 0 +#define CONFIG_IO_14_PD_DRV_STRG 0 +#define CONFIG_IO_14_PD_SLW_RT 0 +#define CONFIG_IO_14_PU_DRV_STRG 0 +#define CONFIG_IO_14_PU_SLW_RT 0 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 0 +#define CONFIG_IO_15_PD_DRV_STRG 0 +#define CONFIG_IO_15_PD_SLW_RT 0 +#define CONFIG_IO_15_PU_DRV_STRG 0 +#define CONFIG_IO_15_PU_SLW_RT 0 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define CONFIG_IO_16_PU_DRV_STRG 8 +#define CONFIG_IO_16_PU_SLW_RT 1 +#define CONFIG_IO_16_RTRIM 1 +#define CONFIG_IO_16_WK_PU_EN 0 +#define CONFIG_IO_17_INPUT_BUF_EN 1 +#define CONFIG_IO_17_PD_DRV_STRG 10 +#define CONFIG_IO_17_PD_SLW_RT 1 +#define CONFIG_IO_17_PU_DRV_STRG 8 +#define CONFIG_IO_17_PU_SLW_RT 1 +#define CONFIG_IO_17_RTRIM 1 +#define CONFIG_IO_17_WK_PU_EN 0 +#define CONFIG_IO_1_INPUT_BUF_EN 1 +#define CONFIG_IO_1_PD_DRV_STRG 10 +#define CONFIG_IO_1_PD_SLW_RT 0 +#define CONFIG_IO_1_PU_DRV_STRG 8 +#define CONFIG_IO_1_PU_SLW_RT 0 +#define CONFIG_IO_1_RTRIM 1 +#define CONFIG_IO_1_WK_PU_EN 1 +#define CONFIG_IO_2_INPUT_BUF_EN 1 +#define CONFIG_IO_2_PD_DRV_STRG 10 +#define CONFIG_IO_2_PD_SLW_RT 0 +#define CONFIG_IO_2_PU_DRV_STRG 8 +#define CONFIG_IO_2_PU_SLW_RT 0 +#define CONFIG_IO_2_RTRIM 1 +#define CONFIG_IO_2_WK_PU_EN 1 +#define CONFIG_IO_3_INPUT_BUF_EN 1 +#define CONFIG_IO_3_PD_DRV_STRG 10 +#define CONFIG_IO_3_PD_SLW_RT 0 +#define CONFIG_IO_3_PU_DRV_STRG 8 +#define CONFIG_IO_3_PU_SLW_RT 0 +#define CONFIG_IO_3_RTRIM 1 +#define CONFIG_IO_3_WK_PU_EN 1 +#define CONFIG_IO_4_INPUT_BUF_EN 1 +#define CONFIG_IO_4_PD_DRV_STRG 10 +#define CONFIG_IO_4_PD_SLW_RT 1 +#define CONFIG_IO_4_PU_DRV_STRG 8 +#define CONFIG_IO_4_PU_SLW_RT 1 +#define CONFIG_IO_4_RTRIM 1 +#define CONFIG_IO_4_WK_PU_EN 0 +#define CONFIG_IO_5_INPUT_BUF_EN 1 +#define CONFIG_IO_5_PD_DRV_STRG 10 +#define CONFIG_IO_5_PD_SLW_RT 1 +#define CONFIG_IO_5_PU_DRV_STRG 8 +#define CONFIG_IO_5_PU_SLW_RT 1 +#define CONFIG_IO_5_RTRIM 1 +#define CONFIG_IO_5_WK_PU_EN 0 +#define CONFIG_IO_6_INPUT_BUF_EN 0 +#define CONFIG_IO_6_PD_DRV_STRG 10 +#define CONFIG_IO_6_PD_SLW_RT 1 +#define CONFIG_IO_6_PU_DRV_STRG 8 +#define CONFIG_IO_6_PU_SLW_RT 1 +#define CONFIG_IO_6_RTRIM 1 +#define CONFIG_IO_6_WK_PU_EN 0 +#define CONFIG_IO_7_INPUT_BUF_EN 1 +#define CONFIG_IO_7_PD_DRV_STRG 10 +#define CONFIG_IO_7_PD_SLW_RT 1 +#define CONFIG_IO_7_PU_DRV_STRG 8 +#define CONFIG_IO_7_PU_SLW_RT 1 +#define CONFIG_IO_7_RTRIM 1 +#define CONFIG_IO_7_WK_PU_EN 0 +#define CONFIG_IO_8_INPUT_BUF_EN 1 +#define CONFIG_IO_8_PD_DRV_STRG 10 +#define CONFIG_IO_8_PD_SLW_RT 1 +#define CONFIG_IO_8_PU_DRV_STRG 8 +#define CONFIG_IO_8_PU_SLW_RT 1 +#define CONFIG_IO_8_RTRIM 1 +#define CONFIG_IO_8_WK_PU_EN 0 +#define CONFIG_IO_9_INPUT_BUF_EN 1 +#define CONFIG_IO_9_PD_DRV_STRG 10 +#define CONFIG_IO_9_PD_SLW_RT 1 +#define CONFIG_IO_9_PU_DRV_STRG 8 +#define CONFIG_IO_9_PU_SLW_RT 1 +#define CONFIG_IO_9_RTRIM 1 +#define CONFIG_IO_9_WK_PU_EN 0 +#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1 +#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1 +#define PINMUX_DEDICATED_IO_10_SEL 15 +#define PINMUX_DEDICATED_IO_11_SEL 15 +#define PINMUX_DEDICATED_IO_12_SEL 1 +#define PINMUX_DEDICATED_IO_13_SEL 1 +#define PINMUX_DEDICATED_IO_14_SEL 10 +#define PINMUX_DEDICATED_IO_15_SEL 10 +#define PINMUX_DEDICATED_IO_16_SEL 13 +#define PINMUX_DEDICATED_IO_17_SEL 13 +#define PINMUX_DEDICATED_IO_4_SEL 8 +#define PINMUX_DEDICATED_IO_5_SEL 8 +#define PINMUX_DEDICATED_IO_6_SEL 8 +#define PINMUX_DEDICATED_IO_7_SEL 8 +#define PINMUX_DEDICATED_IO_8_SEL 8 +#define PINMUX_DEDICATED_IO_9_SEL 8 +#define PINMUX_I2C0_USEFPGA_SEL 1 +#define PINMUX_I2C1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC0_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC2_USEFPGA_SEL 0 +#define PINMUX_NAND_USEFPGA_SEL 0 +#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0 +#define PINMUX_QSPI_USEFPGA_SEL 0 +#define PINMUX_RGMII0_USEFPGA_SEL 0 +#define PINMUX_RGMII1_USEFPGA_SEL 0 +#define PINMUX_RGMII2_USEFPGA_SEL 0 +#define PINMUX_SDMMC_USEFPGA_SEL 0 +#define PINMUX_SHARED_IO_Q1_10_SEL 8 +#define PINMUX_SHARED_IO_Q1_11_SEL 8 +#define PINMUX_SHARED_IO_Q1_12_SEL 8 +#define PINMUX_SHARED_IO_Q1_1_SEL 8 +#define PINMUX_SHARED_IO_Q1_2_SEL 8 +#define PINMUX_SHARED_IO_Q1_3_SEL 8 +#define PINMUX_SHARED_IO_Q1_4_SEL 8 +#define PINMUX_SHARED_IO_Q1_5_SEL 8 +#define PINMUX_SHARED_IO_Q1_6_SEL 8 +#define PINMUX_SHARED_IO_Q1_7_SEL 8 +#define PINMUX_SHARED_IO_Q1_8_SEL 8 +#define PINMUX_SHARED_IO_Q1_9_SEL 8 +#define PINMUX_SHARED_IO_Q2_10_SEL 4 +#define PINMUX_SHARED_IO_Q2_11_SEL 4 +#define PINMUX_SHARED_IO_Q2_12_SEL 4 +#define PINMUX_SHARED_IO_Q2_1_SEL 4 +#define PINMUX_SHARED_IO_Q2_2_SEL 4 +#define PINMUX_SHARED_IO_Q2_3_SEL 4 +#define PINMUX_SHARED_IO_Q2_4_SEL 4 +#define PINMUX_SHARED_IO_Q2_5_SEL 4 +#define PINMUX_SHARED_IO_Q2_6_SEL 4 +#define PINMUX_SHARED_IO_Q2_7_SEL 4 +#define PINMUX_SHARED_IO_Q2_8_SEL 4 +#define PINMUX_SHARED_IO_Q2_9_SEL 4 +#define PINMUX_SHARED_IO_Q3_10_SEL 15 +#define PINMUX_SHARED_IO_Q3_11_SEL 1 +#define PINMUX_SHARED_IO_Q3_12_SEL 1 +#define PINMUX_SHARED_IO_Q3_1_SEL 15 +#define PINMUX_SHARED_IO_Q3_2_SEL 15 +#define PINMUX_SHARED_IO_Q3_3_SEL 15 +#define PINMUX_SHARED_IO_Q3_4_SEL 15 +#define PINMUX_SHARED_IO_Q3_5_SEL 15 +#define PINMUX_SHARED_IO_Q3_6_SEL 15 +#define PINMUX_SHARED_IO_Q3_7_SEL 0 +#define PINMUX_SHARED_IO_Q3_8_SEL 0 +#define PINMUX_SHARED_IO_Q3_9_SEL 15 +#define PINMUX_SHARED_IO_Q4_10_SEL 10 +#define PINMUX_SHARED_IO_Q4_11_SEL 10 +#define PINMUX_SHARED_IO_Q4_12_SEL 10 +#define PINMUX_SHARED_IO_Q4_1_SEL 10 +#define PINMUX_SHARED_IO_Q4_2_SEL 10 +#define PINMUX_SHARED_IO_Q4_3_SEL 10 +#define PINMUX_SHARED_IO_Q4_4_SEL 10 +#define PINMUX_SHARED_IO_Q4_5_SEL 10 +#define PINMUX_SHARED_IO_Q4_6_SEL 10 +#define PINMUX_SHARED_IO_Q4_7_SEL 10 +#define PINMUX_SHARED_IO_Q4_8_SEL 10 +#define PINMUX_SHARED_IO_Q4_9_SEL 10 +#define PINMUX_SPIM0_USEFPGA_SEL 0 +#define PINMUX_SPIM1_USEFPGA_SEL 0 +#define PINMUX_SPIS0_USEFPGA_SEL 0 +#define PINMUX_SPIS1_USEFPGA_SEL 0 +#define PINMUX_UART0_USEFPGA_SEL 1 +#define PINMUX_UART1_USEFPGA_SEL 0 +#define PINMUX_USB0_USEFPGA_SEL 0 +#define PINMUX_USB1_USEFPGA_SEL 0 + +/* Bridge Configuration */ +#define F2H_AXI_SLAVE 1 +#define F2SDRAM0_AXI_SLAVE 1 +#define F2SDRAM1_AXI_SLAVE 1 +#define F2SDRAM2_AXI_SLAVE 1 +#define H2F_AXI_MASTER 1 +#define LWH2F_AXI_MASTER 1 + +/* Voltage Select for Config IO */ +#define CONFIG_IO_BANK_VSEL \ + (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \ + (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3)) + +/* Macro for Config IO bit mapping */ +#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \ + ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \ + ((NAME ## _WK_PU_EN & 0x1) << 16) | \ + ((NAME ## _PU_SLW_RT & 0x1) << 13) | \ + ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \ + ((NAME ## _PD_SLW_RT & 0x1) << 5) | \ + (NAME ## _PD_DRV_STRG & 0x1f)) + +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */ diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h new file mode 100644 index 0000000000..caaff604eb --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Intel Arria 10 SoCFPGA configuration + */ + +#ifndef __SOCFPGA_ARRIA10_CONFIG_H__ +#define __SOCFPGA_ARRIA10_CONFIG_H__ + +/* Clocks */ +#define CB_INTOSC_LS_CLK_HZ 60000000 +#define EMAC0_CLK_HZ 250000000 +#define EMAC1_CLK_HZ 250000000 +#define EMAC2_CLK_HZ 250000000 +#define EOSC1_CLK_HZ 33330000 +#define F2H_FREE_CLK_HZ 200000000 +#define H2F_USER0_CLK_HZ 200000000 +#define H2F_USER1_CLK_HZ 100000000 +#define L3_MAIN_FREE_CLK_HZ 200000000 +#define SDMMC_CLK_HZ 200000000 +#define TPIU_CLK_HZ 100000000 +#define MAINPLLGRP_CNTR15CLK_CNT 900 +#define MAINPLLGRP_CNTR2CLK_CNT 900 +#define MAINPLLGRP_CNTR3CLK_CNT 900 +#define MAINPLLGRP_CNTR4CLK_CNT 900 +#define MAINPLLGRP_CNTR5CLK_CNT 900 +#define MAINPLLGRP_CNTR6CLK_CNT 9 +#define MAINPLLGRP_CNTR7CLK_CNT 9 +#define MAINPLLGRP_CNTR7CLK_SRC 0 +#define MAINPLLGRP_CNTR8CLK_CNT 19 +#define MAINPLLGRP_CNTR9CLK_CNT 900 +#define MAINPLLGRP_CNTR9CLK_SRC 0 +#define MAINPLLGRP_MPUCLK_CNT 0 +#define MAINPLLGRP_MPUCLK_SRC 0 +#define MAINPLLGRP_NOCCLK_CNT 0 +#define MAINPLLGRP_NOCCLK_SRC 0 +#define MAINPLLGRP_NOCDIV_CSATCLK 0 +#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1 +#define MAINPLLGRP_NOCDIV_CSTRACECLK 0 +#define MAINPLLGRP_NOCDIV_L4MAINCLK 0 +#define MAINPLLGRP_NOCDIV_L4MPCLK 1 +#define MAINPLLGRP_NOCDIV_L4SPCLK 2 +#define MAINPLLGRP_VCO0_PSRC 0 +#define MAINPLLGRP_VCO1_DENOM 32 +#define MAINPLLGRP_VCO1_NUMER 1980 +#define PERPLLGRP_CNTR2CLK_CNT 7 +#define PERPLLGRP_CNTR2CLK_SRC 1 +#define PERPLLGRP_CNTR3CLK_CNT 900 +#define PERPLLGRP_CNTR3CLK_SRC 1 +#define PERPLLGRP_CNTR4CLK_CNT 19 +#define PERPLLGRP_CNTR4CLK_SRC 1 +#define PERPLLGRP_CNTR5CLK_CNT 499 +#define PERPLLGRP_CNTR5CLK_SRC 1 +#define PERPLLGRP_CNTR6CLK_CNT 900 +#define PERPLLGRP_CNTR6CLK_SRC 0 +#define PERPLLGRP_CNTR7CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_CNT 900 +#define PERPLLGRP_CNTR8CLK_SRC 0 +#define PERPLLGRP_CNTR9CLK_CNT 900 +#define PERPLLGRP_EMACCTL_EMAC0SEL 0 +#define PERPLLGRP_EMACCTL_EMAC1SEL 0 +#define PERPLLGRP_EMACCTL_EMAC2SEL 0 +#define PERPLLGRP_GPIODIV_GPIODBCLK 32000 +#define PERPLLGRP_VCO0_PSRC 0 +#define PERPLLGRP_VCO1_DENOM 32 +#define PERPLLGRP_VCO1_NUMER 1980 +#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16 +#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8 +#define CLKMGR_TESTIOCTRL_PERICLKSEL 8 +#define ALTERAGRP_MPUCLK_MAINCNT 1 +#define ALTERAGRP_MPUCLK_PERICNT 900 +#define ALTERAGRP_NOCCLK_MAINCNT 9 +#define ALTERAGRP_NOCCLK_PERICNT 900 +#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \ + (ALTERAGRP_MPUCLK_MAINCNT)) +#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \ + (ALTERAGRP_NOCCLK_MAINCNT)) + +/* Pin Mux Configuration */ +#define CONFIG_IO_10_INPUT_BUF_EN 1 +#define CONFIG_IO_10_PD_DRV_STRG 10 +#define CONFIG_IO_10_PD_SLW_RT 1 +#define CONFIG_IO_10_PU_DRV_STRG 8 +#define CONFIG_IO_10_PU_SLW_RT 1 +#define CONFIG_IO_10_RTRIM 1 +#define CONFIG_IO_10_WK_PU_EN 0 +#define CONFIG_IO_11_INPUT_BUF_EN 1 +#define CONFIG_IO_11_PD_DRV_STRG 10 +#define CONFIG_IO_11_PD_SLW_RT 1 +#define CONFIG_IO_11_PU_DRV_STRG 8 +#define CONFIG_IO_11_PU_SLW_RT 1 +#define CONFIG_IO_11_RTRIM 1 +#define CONFIG_IO_11_WK_PU_EN 0 +#define CONFIG_IO_12_INPUT_BUF_EN 0 +#define CONFIG_IO_12_PD_DRV_STRG 0 +#define CONFIG_IO_12_PD_SLW_RT 0 +#define CONFIG_IO_12_PU_DRV_STRG 0 +#define CONFIG_IO_12_PU_SLW_RT 0 +#define CONFIG_IO_12_RTRIM 1 +#define CONFIG_IO_12_WK_PU_EN 1 +#define CONFIG_IO_13_INPUT_BUF_EN 0 +#define CONFIG_IO_13_PD_DRV_STRG 0 +#define CONFIG_IO_13_PD_SLW_RT 0 +#define CONFIG_IO_13_PU_DRV_STRG 0 +#define CONFIG_IO_13_PU_SLW_RT 0 +#define CONFIG_IO_13_RTRIM 1 +#define CONFIG_IO_13_WK_PU_EN 1 +#define CONFIG_IO_14_INPUT_BUF_EN 0 +#define CONFIG_IO_14_PD_DRV_STRG 0 +#define CONFIG_IO_14_PD_SLW_RT 0 +#define CONFIG_IO_14_PU_DRV_STRG 0 +#define CONFIG_IO_14_PU_SLW_RT 0 +#define CONFIG_IO_14_RTRIM 1 +#define CONFIG_IO_14_WK_PU_EN 1 +#define CONFIG_IO_15_INPUT_BUF_EN 0 +#define CONFIG_IO_15_PD_DRV_STRG 0 +#define CONFIG_IO_15_PD_SLW_RT 0 +#define CONFIG_IO_15_PU_DRV_STRG 0 +#define CONFIG_IO_15_PU_SLW_RT 0 +#define CONFIG_IO_15_RTRIM 1 +#define CONFIG_IO_15_WK_PU_EN 1 +#define CONFIG_IO_16_INPUT_BUF_EN 0 +#define CONFIG_IO_16_PD_DRV_STRG 10 +#define CONFIG_IO_16_PD_SLW_RT 1 +#define CONFIG_IO_16_PU_DRV_STRG 8 +#define CONFIG_IO_16_PU_SLW_RT 1 +#define CONFIG_IO_16_RTRIM 1 +#define CONFIG_IO_16_WK_PU_EN 0 +#define CONFIG_IO_17_INPUT_BUF_EN 1 +#define CONFIG_IO_17_PD_DRV_STRG 10 +#define CONFIG_IO_17_PD_SLW_RT 1 +#define CONFIG_IO_17_PU_DRV_STRG 8 +#define CONFIG_IO_17_PU_SLW_RT 1 +#define CONFIG_IO_17_RTRIM 1 +#define CONFIG_IO_17_WK_PU_EN 0 +#define CONFIG_IO_1_INPUT_BUF_EN 1 +#define CONFIG_IO_1_PD_DRV_STRG 10 +#define CONFIG_IO_1_PD_SLW_RT 0 +#define CONFIG_IO_1_PU_DRV_STRG 8 +#define CONFIG_IO_1_PU_SLW_RT 0 +#define CONFIG_IO_1_RTRIM 1 +#define CONFIG_IO_1_WK_PU_EN 1 +#define CONFIG_IO_2_INPUT_BUF_EN 1 +#define CONFIG_IO_2_PD_DRV_STRG 10 +#define CONFIG_IO_2_PD_SLW_RT 0 +#define CONFIG_IO_2_PU_DRV_STRG 8 +#define CONFIG_IO_2_PU_SLW_RT 0 +#define CONFIG_IO_2_RTRIM 1 +#define CONFIG_IO_2_WK_PU_EN 1 +#define CONFIG_IO_3_INPUT_BUF_EN 1 +#define CONFIG_IO_3_PD_DRV_STRG 10 +#define CONFIG_IO_3_PD_SLW_RT 0 +#define CONFIG_IO_3_PU_DRV_STRG 8 +#define CONFIG_IO_3_PU_SLW_RT 0 +#define CONFIG_IO_3_RTRIM 1 +#define CONFIG_IO_3_WK_PU_EN 1 +#define CONFIG_IO_4_INPUT_BUF_EN 1 +#define CONFIG_IO_4_PD_DRV_STRG 10 +#define CONFIG_IO_4_PD_SLW_RT 1 +#define CONFIG_IO_4_PU_DRV_STRG 8 +#define CONFIG_IO_4_PU_SLW_RT 1 +#define CONFIG_IO_4_RTRIM 1 +#define CONFIG_IO_4_WK_PU_EN 0 +#define CONFIG_IO_5_INPUT_BUF_EN 1 +#define CONFIG_IO_5_PD_DRV_STRG 10 +#define CONFIG_IO_5_PD_SLW_RT 1 +#define CONFIG_IO_5_PU_DRV_STRG 8 +#define CONFIG_IO_5_PU_SLW_RT 1 +#define CONFIG_IO_5_RTRIM 1 +#define CONFIG_IO_5_WK_PU_EN 0 +#define CONFIG_IO_6_INPUT_BUF_EN 0 +#define CONFIG_IO_6_PD_DRV_STRG 10 +#define CONFIG_IO_6_PD_SLW_RT 1 +#define CONFIG_IO_6_PU_DRV_STRG 8 +#define CONFIG_IO_6_PU_SLW_RT 1 +#define CONFIG_IO_6_RTRIM 1 +#define CONFIG_IO_6_WK_PU_EN 0 +#define CONFIG_IO_7_INPUT_BUF_EN 1 +#define CONFIG_IO_7_PD_DRV_STRG 10 +#define CONFIG_IO_7_PD_SLW_RT 1 +#define CONFIG_IO_7_PU_DRV_STRG 8 +#define CONFIG_IO_7_PU_SLW_RT 1 +#define CONFIG_IO_7_RTRIM 1 +#define CONFIG_IO_7_WK_PU_EN 0 +#define CONFIG_IO_8_INPUT_BUF_EN 1 +#define CONFIG_IO_8_PD_DRV_STRG 10 +#define CONFIG_IO_8_PD_SLW_RT 1 +#define CONFIG_IO_8_PU_DRV_STRG 8 +#define CONFIG_IO_8_PU_SLW_RT 1 +#define CONFIG_IO_8_RTRIM 1 +#define CONFIG_IO_8_WK_PU_EN 0 +#define CONFIG_IO_9_INPUT_BUF_EN 1 +#define CONFIG_IO_9_PD_DRV_STRG 10 +#define CONFIG_IO_9_PD_SLW_RT 1 +#define CONFIG_IO_9_PU_DRV_STRG 8 +#define CONFIG_IO_9_PU_SLW_RT 1 +#define CONFIG_IO_9_RTRIM 1 +#define CONFIG_IO_9_WK_PU_EN 0 +#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1 +#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1 +#define PINMUX_DEDICATED_IO_10_SEL 15 +#define PINMUX_DEDICATED_IO_11_SEL 15 +#define PINMUX_DEDICATED_IO_12_SEL 1 +#define PINMUX_DEDICATED_IO_13_SEL 1 +#define PINMUX_DEDICATED_IO_14_SEL 10 +#define PINMUX_DEDICATED_IO_15_SEL 10 +#define PINMUX_DEDICATED_IO_16_SEL 13 +#define PINMUX_DEDICATED_IO_17_SEL 13 +#define PINMUX_DEDICATED_IO_4_SEL 8 +#define PINMUX_DEDICATED_IO_5_SEL 8 +#define PINMUX_DEDICATED_IO_6_SEL 8 +#define PINMUX_DEDICATED_IO_7_SEL 8 +#define PINMUX_DEDICATED_IO_8_SEL 8 +#define PINMUX_DEDICATED_IO_9_SEL 8 +#define PINMUX_I2C0_USEFPGA_SEL 1 +#define PINMUX_I2C1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC0_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC1_USEFPGA_SEL 0 +#define PINMUX_I2CEMAC2_USEFPGA_SEL 0 +#define PINMUX_NAND_USEFPGA_SEL 0 +#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0 +#define PINMUX_QSPI_USEFPGA_SEL 0 +#define PINMUX_RGMII0_USEFPGA_SEL 0 +#define PINMUX_RGMII1_USEFPGA_SEL 0 +#define PINMUX_RGMII2_USEFPGA_SEL 0 +#define PINMUX_SDMMC_USEFPGA_SEL 0 +#define PINMUX_SHARED_IO_Q1_10_SEL 8 +#define PINMUX_SHARED_IO_Q1_11_SEL 8 +#define PINMUX_SHARED_IO_Q1_12_SEL 8 +#define PINMUX_SHARED_IO_Q1_1_SEL 8 +#define PINMUX_SHARED_IO_Q1_2_SEL 8 +#define PINMUX_SHARED_IO_Q1_3_SEL 8 +#define PINMUX_SHARED_IO_Q1_4_SEL 8 +#define PINMUX_SHARED_IO_Q1_5_SEL 8 +#define PINMUX_SHARED_IO_Q1_6_SEL 8 +#define PINMUX_SHARED_IO_Q1_7_SEL 8 +#define PINMUX_SHARED_IO_Q1_8_SEL 8 +#define PINMUX_SHARED_IO_Q1_9_SEL 8 +#define PINMUX_SHARED_IO_Q2_10_SEL 4 +#define PINMUX_SHARED_IO_Q2_11_SEL 4 +#define PINMUX_SHARED_IO_Q2_12_SEL 4 +#define PINMUX_SHARED_IO_Q2_1_SEL 4 +#define PINMUX_SHARED_IO_Q2_2_SEL 4 +#define PINMUX_SHARED_IO_Q2_3_SEL 4 +#define PINMUX_SHARED_IO_Q2_4_SEL 4 +#define PINMUX_SHARED_IO_Q2_5_SEL 4 +#define PINMUX_SHARED_IO_Q2_6_SEL 4 +#define PINMUX_SHARED_IO_Q2_7_SEL 4 +#define PINMUX_SHARED_IO_Q2_8_SEL 4 +#define PINMUX_SHARED_IO_Q2_9_SEL 4 +#define PINMUX_SHARED_IO_Q3_10_SEL 15 +#define PINMUX_SHARED_IO_Q3_11_SEL 1 +#define PINMUX_SHARED_IO_Q3_12_SEL 1 +#define PINMUX_SHARED_IO_Q3_1_SEL 15 +#define PINMUX_SHARED_IO_Q3_2_SEL 15 +#define PINMUX_SHARED_IO_Q3_3_SEL 15 +#define PINMUX_SHARED_IO_Q3_4_SEL 15 +#define PINMUX_SHARED_IO_Q3_5_SEL 15 +#define PINMUX_SHARED_IO_Q3_6_SEL 15 +#define PINMUX_SHARED_IO_Q3_7_SEL 0 +#define PINMUX_SHARED_IO_Q3_8_SEL 0 +#define PINMUX_SHARED_IO_Q3_9_SEL 15 +#define PINMUX_SHARED_IO_Q4_10_SEL 10 +#define PINMUX_SHARED_IO_Q4_11_SEL 10 +#define PINMUX_SHARED_IO_Q4_12_SEL 10 +#define PINMUX_SHARED_IO_Q4_1_SEL 10 +#define PINMUX_SHARED_IO_Q4_2_SEL 10 +#define PINMUX_SHARED_IO_Q4_3_SEL 10 +#define PINMUX_SHARED_IO_Q4_4_SEL 10 +#define PINMUX_SHARED_IO_Q4_5_SEL 10 +#define PINMUX_SHARED_IO_Q4_6_SEL 10 +#define PINMUX_SHARED_IO_Q4_7_SEL 10 +#define PINMUX_SHARED_IO_Q4_8_SEL 10 +#define PINMUX_SHARED_IO_Q4_9_SEL 10 +#define PINMUX_SPIM0_USEFPGA_SEL 0 +#define PINMUX_SPIM1_USEFPGA_SEL 0 +#define PINMUX_SPIS0_USEFPGA_SEL 0 +#define PINMUX_SPIS1_USEFPGA_SEL 0 +#define PINMUX_UART0_USEFPGA_SEL 1 +#define PINMUX_UART1_USEFPGA_SEL 0 +#define PINMUX_USB0_USEFPGA_SEL 0 +#define PINMUX_USB1_USEFPGA_SEL 0 + +/* Bridge Configuration */ +#define F2H_AXI_SLAVE 1 +#define F2SDRAM0_AXI_SLAVE 1 +#define F2SDRAM1_AXI_SLAVE 1 +#define F2SDRAM2_AXI_SLAVE 1 +#define H2F_AXI_MASTER 1 +#define LWH2F_AXI_MASTER 1 + +/* Voltage Select for Config IO */ +#define CONFIG_IO_BANK_VSEL \ + (((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \ + (CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3)) + +/* Macro for Config IO bit mapping */ +#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \ + ((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \ + ((NAME ## _WK_PU_EN & 0x1) << 16) | \ + ((NAME ## _PU_SLW_RT & 0x1) << 13) | \ + ((NAME ## _PU_DRV_STRG & 0xf) << 8) | \ + ((NAME ## _PD_SLW_RT & 0x1) << 5) | \ + (NAME ## _PD_DRV_STRG & 0x1f)) + +#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */

Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel pan@semihalf.com Signed-off-by: Alexandru M Stan amstan@chromium.org --- arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 +++++++++++++++++++ ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 ++ .../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 ++ ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 ++ .../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 ++ 6 files changed, 118 insertions(+) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f6..910b6c3acd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_chameleonv3_270_3.dtb \ + socfpga_arria10_chameleonv3_480_2.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_is1.dtb \ diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/dts/socfpga_arria10_chameleonv3.dts new file mode 100644 index 0000000000..988cc44543 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Google Chameleon V3"; + compatible = "google,chameleon-v3", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + ssm2603: ssm2603@1a { + compatible = "adi,ssm2603"; + reg = <0x1a>; + }; +}; + +&i2c1 { + status = "okay"; + + u80: u80@21 { + compatible = "nxp,pca9535"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "SOM_AUD_MUTE", + "DP1_OUT_CEC_EN", + "DP2_OUT_CEC_EN", + "DP1_SOM_PS8469_CAD", + "DPD_SOM_PS8469_CAD", + "DP_OUT_PWR_EN", + "STM32_RST_L", + "STM32_BOOT0", + + "FPGA_PROT", + "STM32_FPGA_COMM0", + "TP119", + "TP120", + "TP121", + "TP122", + "TP123", + "TP124"; + }; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi new file mode 100644 index 0000000000..e789d49657 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3_270_3_handoff.h" +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi" diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts new file mode 100644 index 0000000000..5f40af6eb9 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3.dts" diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi new file mode 100644 index 0000000000..7bbcc471c5 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3_480_2_handoff.h" +#include "socfpga_arria10-handoff.dtsi" +#include "socfpga_arria10_handoff_u-boot.dtsi" +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi" diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts new file mode 100644 index 0000000000..5f40af6eb9 --- /dev/null +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include "socfpga_arria10_chameleonv3.dts"

Add board directory for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel pan@semihalf.com --- board/google/chameleonv3/Makefile | 5 +++ board/google/chameleonv3/board.c | 27 ++++++++++++++ board/google/chameleonv3/fpga.its | 28 ++++++++++++++ board/google/chameleonv3/fpga_early_io.its | 35 ++++++++++++++++++ board/google/chameleonv3/mercury_aa1.c | 43 ++++++++++++++++++++++ board/google/chameleonv3/mercury_aa1.h | 12 ++++++ 6 files changed, 150 insertions(+) create mode 100644 board/google/chameleonv3/Makefile create mode 100644 board/google/chameleonv3/board.c create mode 100644 board/google/chameleonv3/fpga.its create mode 100644 board/google/chameleonv3/fpga_early_io.its create mode 100644 board/google/chameleonv3/mercury_aa1.c create mode 100644 board/google/chameleonv3/mercury_aa1.h

diff --git a/board/google/chameleonv3/Makefile b/board/google/chameleonv3/Makefile new file mode 100644 index 0000000000..bb413fde83 --- /dev/null +++ b/board/google/chameleonv3/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright 2022 Google LLC + +obj-y := board.o mercury_aa1.o diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c new file mode 100644 index 0000000000..4d3049689d --- /dev/null +++ b/board/google/chameleonv3/board.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include <net.h> +#include <errno.h> +#include "mercury_aa1.h" + +int misc_init_r(void) +{ + u8 mac[ARP_HLEN]; + int res; + + if (env_get("ethaddr")) + return 0; + + res = mercury_aa1_read_mac(mac); + if (res) { + printf("couldn't read mac address: %s\n", errno_str(res)); + return 0; + } + + if (is_valid_ethaddr(mac)) + eth_env_set_enetaddr("ethaddr", mac); + + return 0; +} diff --git a/board/google/chameleonv3/fpga.its b/board/google/chameleonv3/fpga.its new file mode 100644 index 0000000000..85a830002f --- /dev/null +++ b/board/google/chameleonv3/fpga.its @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA full bitstream"; + data = /incbin/("../../../fpga.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA config"; + fpga = "fpga-periph-1"; + }; + }; +}; diff --git a/board/google/chameleonv3/fpga_early_io.its b/board/google/chameleonv3/fpga_early_io.its new file mode 100644 index 0000000000..ebc7bcbaae --- /dev/null +++ b/board/google/chameleonv3/fpga_early_io.its @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +/dts-v1/; + +/ { + description = "FIT image with FPGA bistream"; + #address-cells = <1>; + + images { + fpga-periph-1 { + description = "FPGA peripheral bitstream"; + data = /incbin/("../../../periph.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + fpga-core-1 { + description = "FPGA core bitstream"; + data = /incbin/("../../../core.rbf"); + type = "fpga"; + arch = "arm"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + config-1 { + description = "Boot with FPGA config"; + fpga = "fpga-periph-1", "fpga-core-1"; + }; + }; +}; diff --git a/board/google/chameleonv3/mercury_aa1.c b/board/google/chameleonv3/mercury_aa1.c new file mode 100644 index 0000000000..ed447ec37c --- /dev/null +++ b/board/google/chameleonv3/mercury_aa1.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2022 Google LLC + */ +#include <net.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <atsha204a-i2c.h> +#include "mercury_aa1.h" + +#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4 +#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5 + +int mercury_aa1_read_mac(u8 *mac) +{ + struct udevice *dev; + u8 buf[8]; + int ret; + + ret = uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev); + if (ret) + return ret; + + ret = atsha204a_wakeup(dev); + if (ret) + return ret; + + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + MERCURY_AA1_ATSHA204A_OTP_MAC0, buf); + if (ret) + goto sleep; + + ret = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, + MERCURY_AA1_ATSHA204A_OTP_MAC1, buf + 4); + if (ret) + goto sleep; + + memcpy(mac, buf, ARP_HLEN); + +sleep: + atsha204a_sleep(dev); + return ret; +} diff --git a/board/google/chameleonv3/mercury_aa1.h b/board/google/chameleonv3/mercury_aa1.h new file mode 100644 index 0000000000..636b735a3b --- /dev/null +++ b/board/google/chameleonv3/mercury_aa1.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2022 Google LLC + */ + +/** + * mercury_aa1_read_mac() - Read mac address from on-board OTP memory + * + * @mac: Returned mac address + * Return: 0 if successful, -ve on error + */ +int mercury_aa1_read_mac(u8 *mac);

Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel pan@semihalf.com --- arch/arm/mach-socfpga/Kconfig | 7 +++++ configs/socfpga_chameleonv3_defconfig | 29 ++++++++++++++++++ include/configs/socfpga_chameleonv3.h | 44 +++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 configs/socfpga_chameleonv3_defconfig create mode 100644 include/configs/socfpga_chameleonv3.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 78a7549a41..fe851f575e 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" select TARGET_SOCFPGA_ARRIA5

+config TARGET_SOCFPGA_CHAMELEONV3 + bool "Google Chameleon v3 (Arria 10)" + select TARGET_SOCFPGA_ARRIA10 + config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -194,6 +198,7 @@ config SYS_BOARD default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK + default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO @@ -219,6 +224,7 @@ config SYS_VENDOR default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES + default "google" if TARGET_SOCFPGA_CHAMELEONV3 default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO @@ -234,6 +240,7 @@ config SYS_CONFIG_NAME default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK + default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig new file mode 100644 index 0000000000..7870d31b09 --- /dev/null +++ b/configs/socfpga_chameleonv3_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" +CONFIG_DISTRO_DEFAULTS=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_FPGA=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y +CONFIG_MMC_DW=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_MISC_INIT_R=y +CONFIG_ATSHA204A=y diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h new file mode 100644 index 0000000000..891b762946 --- /dev/null +++ b/include/configs/socfpga_chameleonv3.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2022 Google LLC + */ +#ifndef __SOCFGPA_CHAMELEONV3_H__ +#define __SOCFGPA_CHAMELEONV3_H__ + +#include <asm/arch/base_addr_a10.h> + +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* + * U-Boot general configurations + */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \ + "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \ + "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \ + "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0" + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + +/* SPL memory allocation configuration, this is for FAT implementation */ +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __SOCFGPA_CHAMELEONV3_H__ */

From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device exits low-power mode and, after a delay of tWHI, is ready to receive I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel pan@semihalf.com --- drivers/misc/atsha204a-i2c.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index aa6acf0f9a..81ecb5b617 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -21,7 +21,8 @@ #include <linux/bitrev.h> #include <u-boot/crc.h>

-#define ATSHA204A_TWLO 60 +#define ATSHA204A_TWLO_US 60 +#define ATSHA204A_TWHI_US 2500 #define ATSHA204A_TRANSACTION_TIMEOUT 100000 #define ATSHA204A_TRANSACTION_RETRY 5 #define ATSHA204A_EXECTIME 5000 @@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev) continue; }

- udelay(ATSHA204A_TWLO); + udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);

res = atsha204a_recv_resp(dev, &resp); if (res) {

This driver is a child of the rstmgr driver, both of which share the same devicetree node. As a result, passing the child's udevice pointer to dev_read_addr_ptr results in a failure of reading the #address-cells property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel pan@semihalf.com --- drivers/sysreset/sysreset_socfpga.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c index e38296ac3f..9b62dd5eab 100644 --- a/drivers/sysreset/sysreset_socfpga.c +++ b/drivers/sysreset/sysreset_socfpga.c @@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev) { struct socfpga_sysreset_data *data = dev_get_priv(dev);

- data->rstmgr_base = dev_read_addr_ptr(dev); + data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev)); return 0; }

Using udelay while the clocks aren't fully configured causes the timer system to save the wrong clock rate. Use sdelay and wait_on_value instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel pan@semihalf.com --- arch/arm/mach-socfpga/clock_manager.c | 7 ++++--- arch/arm/mach-socfpga/clock_manager_arria10.c | 12 ++++++------ arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 ++++ 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 9e645a4253..c9bd4859f7 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask) /* function to poll in the fsm busy bit */ int cm_wait_for_fsm(void) { - return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() + - CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000, - false); + void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT); + + /* 20s timeout */ + return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 100000000); }

int set_cpu_clk_info(void) diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c index 58d5d3fd8a..daa06b9d03 100644 --- a/arch/arm/mach-socfpga/clock_manager_arria10.c +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c @@ -551,13 +551,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, CLKMGR_MAINPLL_VCO1_DENOM_LSB) | cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); } writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | main_cfg->vco1_numer, socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); }

@@ -585,13 +585,13 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, clk_hz), socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); } writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | per_cfg->vco1_numer, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); - mdelay(1); + sdelay(1000000); /* 1ms */ cm_wait_for_lock(LOCKED_MASK); }

@@ -727,7 +727,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);

/* Wait for at least 5 us */ - udelay(5); + sdelay(5000);

/* Now deassert BGPWRDN and PWRDN */ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, @@ -738,7 +738,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);

/* Wait for at least 7 us */ - udelay(7); + sdelay(7000);

/* enable the VCO and disable the external regulator to PLL */ writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) & diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index a8cb07a1c4..78013f0527 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -20,6 +20,10 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #endif #endif

+void sdelay(unsigned long loops); +u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr, + u32 bound); + #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <asm/arch/clock_manager_gen5.h> #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

For some reason, on the Mercury+ AA1 module, calling fpgamgr_wait_early_user_mode immediately after writing the peripheral bitstream leaves the fpga in a broken state (ddr calibration hangs). Adding a delay before the first sync word is written seems to fix this. Inspecting the fpgamgr registers before and after the delay, imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit (instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel pan@semihalf.com --- drivers/fpga/socfpga_arria10.c | 8 ++++++++ 1 file changed, 8 insertions(+)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 07bfe3060e..d8089122af 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -80,6 +80,13 @@ static int wait_for_user_mode(void) 1, FPGA_TIMEOUT_MSEC, false); }

+static int wait_for_fifo_empty(void) +{ + return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, + ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK, + 1, FPGA_TIMEOUT_MSEC, false); +} + int is_fpgamgr_early_user_mode(void) { return (readl(&fpga_manager_base->imgcfg_stat) & @@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,

WATCHDOG_RESET(); } + wait_for_fifo_empty();

if (fpga_loadfs.rbfinfo.section == periph_section) { if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {

Before relocating to SDRAM, the ECC is initialized by clearing the whole SDRAM. In order to speed this up, dcache_enable is used (see sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate access control"), this no longer works, because running code in OCRAM with the XN bit set causes a page fault. Override dram_bank_mmu_setup to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel pan@semihalf.com --- arch/arm/mach-socfpga/misc_arria10.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 0ed2adfd84..7ce888d197 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -246,3 +246,29 @@ int qspi_flash_software_reset(void) return 0; } #endif + +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + u32 start, size; + int i; + + /* If we're still in OCRAM, don't set the XN bit on it */ + if (!(gd->flags & GD_FLG_RELOC)) { + set_section_dcache( + CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + DCACHE_WRITETHROUGH); + } + + /* + * The default implementation of this function allows the DRAM dcache + * to be enabled only after relocation. However, to speed up ECC + * initialization, we want to be able to enable DRAM dcache before + * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram + * is set first). + */ + start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + for (i = start; i < start + size; i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +}