[PATCH v3 0/2] Xilinx PCI driver fixes
This series fixes couple issues with the Xilinx PCIe host controller driver.
Changes in v3: - Add error checking and improve commit title of patch 1 - Rebase patch 2 on modified patch 1
Mayuresh Chitale (2): pci: xilinx: Fix "reg" not found error pci: xilinx: Enable MMIO region
drivers/pci/pcie_xilinx.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-)
Fix the driver to use the dev_read_addr_size API to fetch the reg property from the DT.
Signed-off-by: Mayuresh Chitale mchitale@ventanamicro.com --- drivers/pci/pcie_xilinx.c | 29 ++++++++++++----------------- 1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index 53fd121e90..fdc9b08c10 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -8,11 +8,10 @@ #include <common.h> #include <dm.h> #include <pci.h> -#include <asm/global_data.h> #include <linux/bitops.h> #include <linux/printk.h> - -#include <asm/io.h> +#include <linux/io.h> +#include <linux/err.h>
/** * struct xilinx_pcie - Xilinx PCIe controller state @@ -140,20 +139,16 @@ static int pcie_xilinx_write_config(struct udevice *bus, pci_dev_t bdf, static int pcie_xilinx_of_to_plat(struct udevice *dev) { struct xilinx_pcie *pcie = dev_get_priv(dev); - struct fdt_resource reg_res; - DECLARE_GLOBAL_DATA_PTR; - int err; - - err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg", - 0, ®_res); - if (err < 0) { - pr_err(""reg" resource not found\n"); - return err; - } - - pcie->cfg_base = map_physmem(reg_res.start, - fdt_resource_size(®_res), - MAP_NOCACHE); + fdt_addr_t addr; + fdt_size_t size; + + addr = dev_read_addr_size(dev, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + pcie->cfg_base = devm_ioremap(dev, addr, size); + if (IS_ERR(pcie->cfg_base)) + return PTR_ERR(pcie->cfg_base);
return 0; }
The host bridge MMIO region is disabled by default due to which MMIO accesses cause an exception. Fix it by setting the bridge enable bit. This change is ported from the linux pcie-xilinx driver.
Signed-off-by: Mayuresh Chitale mchitale@ventanamicro.com Reviewed-by: Michal Simek michal.simek@amd.com --- drivers/pci/pcie_xilinx.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index fdc9b08c10..3db460b5f9 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -24,6 +24,8 @@ struct xilinx_pcie { /* Register definitions */ #define XILINX_PCIE_REG_PSCR 0x144 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) +#define XILINX_PCIE_REG_RPSC 0x148 +#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
/** * pcie_xilinx_link_up() - Check whether the PCIe link is up @@ -141,6 +143,7 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev) struct xilinx_pcie *pcie = dev_get_priv(dev); fdt_addr_t addr; fdt_size_t size; + u32 rpsc;
addr = dev_read_addr_size(dev, &size); if (addr == FDT_ADDR_T_NONE) @@ -150,6 +153,11 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev) if (IS_ERR(pcie->cfg_base)) return PTR_ERR(pcie->cfg_base);
+ /* Enable the Bridge enable bit */ + rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC); + rpsc |= XILINX_PCIE_REG_RPSC_BEN; + __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC); + return 0; }
On 11/16/23 17:51, Mayuresh Chitale wrote:
This series fixes couple issues with the Xilinx PCIe host controller driver.
Changes in v3:
- Add error checking and improve commit title of patch 1
- Rebase patch 2 on modified patch 1
Mayuresh Chitale (2): pci: xilinx: Fix "reg" not found error pci: xilinx: Enable MMIO region
drivers/pci/pcie_xilinx.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-)
Applied. M
participants (2)
-
Mayuresh Chitale -
Michal Simek