[PATCH 0/4] spi-synquacer fixes and improvement
When we support SPI-NAND flash with spi-synquacer driver, we encounter several issues. This series fixes the spi-synquacer driver to make SPI-NAND flash device work. This series also includes some improvement and simplifies the implementation.
Masahisa Kojima (4): spi: synquacer: busy variable must be initialized before use spi: synquacer: wait until slave is deselected spi: synquacer: DMSTART bit must not be set while transferring spi: synquacer: simplify tx completion checking
drivers/spi/spi-synquacer.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-)
"busy" variable is ORed without being initialized, must be zeroed before use.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com --- drivers/spi/spi-synquacer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index ce558c4bc0..62f85f0335 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -275,7 +275,7 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, { struct udevice *bus = dev->parent; struct synquacer_spi_priv *priv = dev_get_priv(bus); - u32 val, words, busy; + u32 val, words, busy = 0;
val = readl(priv->base + FIFOCFG); val |= (1 << RX_FLUSH);
On Tue, 17 May 2022 at 03:41, Masahisa Kojima masahisa.kojima@linaro.org wrote:
"busy" variable is ORed without being initialized, must be zeroed before use.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com
Acked-by: Jassi Brar jaswinder.singh@linaro.org
On Tue, May 17, 2022 at 05:41:36PM +0900, Masahisa Kojima wrote:
"busy" variable is ORed without being initialized, must be zeroed before use.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com Acked-by: Jassi Brar jaswinder.singh@linaro.org
Applied to u-boot/next, thanks!
synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com --- drivers/spi/spi-synquacer.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 62f85f0335..f1422cf893 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -46,7 +46,9 @@ #define RXE 0x24 #define RXC 0x28 #define TFLETE 4 +#define TSSRS 6 #define RFMTE 5 +#define RSSRS 6
#define FAULTF 0x2c #define FAULTC 0x30 @@ -170,6 +172,11 @@ static void synquacer_cs_set(struct synquacer_spi_priv *priv, bool active) priv->rx_words = 16; read_fifo(priv); } + + /* wait until slave is deselected */ + while (!(readl(priv->base + TXF) & BIT(TSSRS)) || + !(readl(priv->base + RXF) & BIT(RSSRS))) + ; } }
On Tue, 17 May 2022 at 03:41, Masahisa Kojima masahisa.kojima@linaro.org wrote:
synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com
Acked-by: Jassi Brar jaswinder.singh@linaro.org
On Tue, May 17, 2022 at 05:41:37PM +0900, Masahisa Kojima wrote:
synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com Acked-by: Jassi Brar jaswinder.singh@linaro.org
Applied to u-boot/next, thanks!
DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com --- drivers/spi/spi-synquacer.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index f1422cf893..5e1b3aedc7 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, writel(~0, priv->base + RXC);
/* Trigger */ - val = readl(priv->base + DMSTART); - val |= BIT(TRIGGER); - writel(val, priv->base + DMSTART); + if (flags & SPI_XFER_BEGIN) { + val = readl(priv->base + DMSTART); + val |= BIT(TRIGGER); + writel(val, priv->base + DMSTART); + }
while (busy & (BIT(RXBIT) | BIT(TXBIT))) { if (priv->rx_words)
On Tue, 17 May 2022 at 03:41, Masahisa Kojima masahisa.kojima@linaro.org wrote:
DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com
Acked-by: Jassi Brar jaswinder.singh@linaro.org
On Tue, May 17, 2022 at 05:41:38PM +0900, Masahisa Kojima wrote:
DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com Acked-by: Jassi Brar jaswinder.singh@linaro.org
Applied to u-boot/next, thanks!
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com --- drivers/spi/spi-synquacer.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index 5e1b3aedc7..0cae3dfc77 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -45,6 +45,7 @@ #define RXF 0x20 #define RXE 0x24 #define RXC 0x28 +#define TFES 1 #define TFLETE 4 #define TSSRS 6 #define RFMTE 5 @@ -345,13 +346,10 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, if (priv->tx_words) { write_fifo(priv); } else { - u32 len; - - do { /* wait for shifter to empty out */ + /* wait for shifter to empty out */ + while (!(readl(priv->base + TXF) & BIT(TFES))) cpu_relax(); - len = readl(priv->base + DMSTATUS); - len = (len >> TX_DATA_SHIFT) & TX_DATA_MASK; - } while (tx_buf && len); + busy &= ~BIT(TXBIT); } }
On Tue, 17 May 2022 at 03:41, Masahisa Kojima masahisa.kojima@linaro.org wrote:
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com
Acked-by: Jassi Brar jaswinder.singh@linaro.org
On Tue, May 17, 2022 at 05:41:39PM +0900, Masahisa Kojima wrote:
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes.
Signed-off-by: Masahisa Kojima masahisa.kojima@linaro.org Signed-off-by: Satoru Okamoto okamoto.satoru@socionext.com Acked-by: Jassi Brar jaswinder.singh@linaro.org
Applied to u-boot/next, thanks!
participants (3)
-
Jassi Brar -
Masahisa Kojima -
Tom Rini