Add clock driver support for Rockchip rv1108 soc

Signed-off-by: Andy Yan andy.yan@rock-chips.com ---

arch/arm/include/asm/arch-rockchip/cru_rv1108.h | 111 ++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rv1108.c | 223 ++++++++++++++++++++ include/dt-bindings/clock/rv1108-cru.h | 269 ++++++++++++++++++++++++ 5 files changed, 605 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1108.h create mode 100644 drivers/clk/rockchip/clk_rv1108.c create mode 100644 include/dt-bindings/clock/rv1108-cru.h

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h new file mode 100644 index 0000000..2a1ae69 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan andy.yan@rock-chips.com + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RV1108_H +#define _ASM_ARCH_CRU_RV1108_H + +#include <common.h> + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +struct rv1108_clk_priv { + struct rv1108_cru *cru; + ulong rate; +}; + +struct rv1108_cru { + struct rv1108_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int con5; + unsigned int reserved[2]; + } pll[3]; + unsigned int clksel_con[46]; + unsigned int reserved1[2]; + unsigned int clkgate_con[20]; + unsigned int reserved2[4]; + unsigned int softrst_con[13]; + unsigned int reserved3[3]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int glb_cnt_th; + unsigned int misc_con; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rv1108_cru, emmc_con[1], 0x01ec); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLL CON0 */ + FBDIV_MASK = 0xfff, + FBDIV_SHIFT = 0, + + /* PLL CON1 */ + POSTDIV2_SHIFT = 12, + POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, + POSTDIV1_SHIFT = 8, + POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, + REFDIV_MASK = 0x3f, + REFDIV_SHIFT = 0, + + /* PLL CON2 */ + LOCK_STA_SHIFT = 31, + LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, + FRACDIV_MASK = 0xffffff, + FRACDIV_SHIFT = 0, + + /* PLL CON3 */ + WORK_MODE_SHIFT = 8, + WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, + WORK_MODE_SLOW = 0, + WORK_MODE_NORMAL = 1, + DSMPD_SHIFT = 3, + DSMPD_MASK = 1 << DSMPD_SHIFT, + + /* CLKSEL0_CON */ + CORE_PLL_SEL_SHIFT = 8, + CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, + CORE_PLL_SEL_APLL = 0, + CORE_PLL_SEL_GPLL = 1, + CORE_PLL_SEL_DPLL = 2, + CORE_CLK_DIV_SHIFT = 0, + CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + + /* CLKSEL24_CON */ + MAC_PLL_SEL_SHIFT = 12, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + MAC_PLL_SEL_APLL = 0, + MAC_PLL_SEL_GPLL = 1, + RMII_EXTCLK_SEL_SHIFT = 8, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, + MAC_CLK_DIV_MASK = 0x1f, + MAC_CLK_DIV_SHIFT = 0, + + /* CLKSEL27_CON */ + SFC_PLL_SEL_SHIFT = 7, + SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, + SFC_PLL_SEL_DPLL = 0, + SFC_PLL_SEL_GPLL = 1, + SFC_CLK_DIV_SHIFT = 0, + SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index 8018d47..9f4bc2e 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -42,6 +42,7 @@ enum periph_id { PERIPH_ID_SDMMC2, PERIPH_ID_HDMI, PERIPH_ID_GMAC, + PERIPH_ID_SFC,

PERIPH_ID_COUNT,

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 8dc60f8..e404c0c 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o +obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c new file mode 100644 index 0000000..0946dab --- /dev/null +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -0,0 +1,223 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan andy.yan@rock-chips.com + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rv1108.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rv1108-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + VCO_MAX_HZ = 2400U * 1000000, + VCO_MIN_HZ = 600 * 1000000, + OUTPUT_MAX_HZ = 2400U * 1000000, + OUTPUT_MIN_HZ = 24 * 1000000, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\ + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\ + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\ + #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* use interge mode*/ +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); + +static inline int rv1108_pll_id(enum rk_clk_id clk_id) +{ + int id = 0; + + switch (clk_id) { + case CLK_ARM: + case CLK_DDR: + id = clk_id - 1; + break; + case CLK_GENERAL: + id = 2; + break; + default: + printf("invalid pll id:%d\n", clk_id); + id = -1; + break; + } + + return id; +} + +static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t refdiv, fbdiv, postdiv1, postdiv2; + uint32_t con0, con1, con3; + int pll_id = rv1108_pll_id(clk_id); + struct rv1108_pll *pll = &cru->pll[pll_id]; + uint32_t freq; + + con3 = readl(&pll->con3); + + if (con3 & WORK_MODE_MASK) { + con0 = readl(&pll->con0); + con1 = readl(&pll->con1); + fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK; + postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; + postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; + refdiv = (con1 & REFDIV_MASK) >> REFDIV_SHIFT; + freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; + } else { + freq = OSC_HZ; + } + + return freq; +} + +static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) +{ + uint32_t con = readl(&cru->clksel_con[24]); + ulong pll_rate; + uint8_t div; + + if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + else + pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); + + /*default set 50MHZ for gmac*/ + if (!rate) + rate = 50000000; + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x1f) + rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, + div << MAC_CLK_DIV_SHIFT); + else + debug("Unsupported div for gmac:%d\n", div); + + return DIV_TO_RATE(pll_rate, div); +} + +static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) +{ + u32 con = readl(&cru->clksel_con[27]); + u32 pll_rate; + u32 div; + + if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL) + pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); + else + pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x3f) + rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, + div << SFC_CLK_DIV_SHIFT); + else + debug("Unsupported sfc clk rate:%d\n", rate); + + return DIV_TO_RATE(pll_rate, div); +} + +static ulong rv1108_clk_get_rate(struct clk *clk) +{ + struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0 ... 63: + return rkclk_pll_get_rate(priv->cru, clk->id); + default: + return -ENOENT; + } +} + +static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1108_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate; + + switch (clk->id) { + case SCLK_MAC: + new_rate = rv1108_mac_set_clk(priv->cru, rate); + break; + case SCLK_SFC: + new_rate = rv1108_sfc_set_clk(priv->cru, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static const struct clk_ops rv1108_clk_ops = { + .get_rate = rv1108_clk_get_rate, + .set_rate = rv1108_clk_set_rate, +}; + +static void rkclk_init(struct rv1108_cru *cru) +{ + unsigned int apll = rkclk_pll_get_rate(cru, CLK_ARM); + unsigned int dpll = rkclk_pll_get_rate(cru, CLK_DDR); + unsigned int gpll = rkclk_pll_get_rate(cru, CLK_GENERAL); + + rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK, + 0 << MAC_CLK_DIV_SHIFT); + + printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll); +} + +static int rv1108_clk_probe(struct udevice *dev) +{ + struct rv1108_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rv1108_cru *)dev_get_addr(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rv1108_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rv1108_sysreset", "reset", &dev); + if (ret) + error("No Rv1108 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rv1108_clk_ids[] = { + { .compatible = "rockchip,rv1108-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rv1108) = { + .name = "clk_rv1108", + .id = UCLASS_CLK, + .of_match = rv1108_clk_ids, + .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv), + .ops = &rv1108_clk_ops, + .bind = rv1108_clk_bind, + .probe = rv1108_clk_probe, +}; diff --git a/include/dt-bindings/clock/rv1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h new file mode 100644 index 0000000..d2ad3bb --- /dev/null +++ b/include/dt-bindings/clock/rv1108-cru.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co. Ltd. + * Author: Shawn Lin shawn.lin@rock-chips.com + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H + +/* pll id */ +#define PLL_APLL 0 +#define PLL_DPLL 1 +#define PLL_GPLL 2 +#define ARMCLK 3 + +/* sclk gates (special clocks) */ +#define SCLK_MAC 64 +#define SCLK_SPI0 65 +#define SCLK_NANDC 67 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_UART0 72 +#define SCLK_UART1 73 +#define SCLK_UART2 74 +#define SCLK_I2S0 75 +#define SCLK_I2S1 76 +#define SCLK_I2S2 77 +#define SCLK_TIMER0 78 +#define SCLK_TIMER1 79 +#define SCLK_SFC 80 +#define SCLK_SDMMC_DRV 81 +#define SCLK_SDIO_DRV 82 +#define SCLK_EMMC_DRV 83 +#define SCLK_SDMMC_SAMPLE 84 +#define SCLK_SDIO_SAMPLE 85 +#define SCLK_EMMC_SAMPLE 86 +#define SCLK_MAC_RX 87 +#define SCLK_MAC_TX 88 +#define SCLK_MACREF 89 +#define SCLK_MACREF_OUT 90 + + +/* aclk gates */ +#define ACLK_DMAC 192 +#define ACLK_PRE 193 +#define ACLK_CORE 194 +#define ACLK_ENMCORE 195 +#define ACLK_GMAC 196 + + +/* pclk gates */ +#define PCLK_GPIO1 256 +#define PCLK_GPIO2 257 +#define PCLK_GPIO3 258 +#define PCLK_GRF 259 +#define PCLK_I2C1 260 +#define PCLK_I2C2 261 +#define PCLK_I2C3 262 +#define PCLK_SPI 263 +#define PCLK_SFC 264 +#define PCLK_UART0 265 +#define PCLK_UART1 266 +#define PCLK_UART2 267 +#define PCLK_TSADC 268 +#define PCLK_PWM 269 +#define PCLK_TIMER 270 +#define PCLK_PERI 271 +#define PCLK_GMAC 272 + +/* hclk gates */ +#define HCLK_I2S0_8CH 320 +#define HCLK_I2S1_8CH 321 +#define HCLK_I2S2_2CH 322 +#define HCLK_NANDC 323 +#define HCLK_SDMMC 324 +#define HCLK_SDIO 325 +#define HCLK_EMMC 326 +#define HCLK_PERI 327 +#define HCLK_SFC 328 + +#define CLK_NR_CLKS (HCLK_SFC + 1) + +/* reset id */ +#define SRST_CORE_PO_AD 0 +#define SRST_CORE_AD 1 +#define SRST_L2_AD 2 +#define SRST_CPU_NIU_AD 3 +#define SRST_CORE_PO 4 +#define SRST_CORE 5 +#define SRST_L2 6 +#define SRST_CORE_DBG 8 +#define PRST_DBG 9 +#define RST_DAP 10 +#define PRST_DBG_NIU 11 +#define ARST_STRC_SYS_AD 15 + +#define SRST_DDRPHY_CLKDIV 16 +#define SRST_DDRPHY 17 +#define PRST_DDRPHY 18 +#define PRST_HDMIPHY 19 +#define PRST_VDACPHY 20 +#define PRST_VADCPHY 21 +#define PRST_MIPI_CSI_PHY 22 +#define PRST_MIPI_DSI_PHY 23 +#define PRST_ACODEC 24 +#define ARST_BUS_NIU 25 +#define PRST_TOP_NIU 26 +#define ARST_INTMEM 27 +#define HRST_ROM 28 +#define ARST_DMAC 29 +#define SRST_MSCH_NIU 30 +#define PRST_MSCH_NIU 31 + +#define PRST_DDRUPCTL 32 +#define NRST_DDRUPCTL 33 +#define PRST_DDRMON 34 +#define HRST_I2S0_8CH 35 +#define MRST_I2S0_8CH 36 +#define HRST_I2S1_2CH 37 +#define MRST_IS21_2CH 38 +#define HRST_I2S2_2CH 39 +#define MRST_I2S2_2CH 40 +#define HRST_CRYPTO 41 +#define SRST_CRYPTO 42 +#define PRST_SPI 43 +#define SRST_SPI 44 +#define PRST_UART0 45 +#define PRST_UART1 46 +#define PRST_UART2 47 + +#define SRST_UART0 48 +#define SRST_UART1 49 +#define SRST_UART2 50 +#define PRST_I2C1 51 +#define PRST_I2C2 52 +#define PRST_I2C3 53 +#define SRST_I2C1 54 +#define SRST_I2C2 55 +#define SRST_I2C3 56 +#define PRST_PWM1 58 +#define SRST_PWM1 60 +#define PRST_WDT 61 +#define PRST_GPIO1 62 +#define PRST_GPIO2 63 + +#define PRST_GPIO3 64 +#define PRST_GRF 65 +#define PRST_EFUSE 66 +#define PRST_EFUSE512 67 +#define PRST_TIMER0 68 +#define SRST_TIMER0 69 +#define SRST_TIMER1 70 +#define PRST_TSADC 71 +#define SRST_TSADC 72 +#define PRST_SARADC 73 +#define SRST_SARADC 74 +#define HRST_SYSBUS 75 +#define PRST_USBGRF 76 + +#define ARST_PERIPH_NIU 80 +#define HRST_PERIPH_NIU 81 +#define PRST_PERIPH_NIU 82 +#define HRST_PERIPH 83 +#define HRST_SDMMC 84 +#define HRST_SDIO 85 +#define HRST_EMMC 86 +#define HRST_NANDC 87 +#define NRST_NANDC 88 +#define HRST_SFC 89 +#define SRST_SFC 90 +#define ARST_GMAC 91 +#define HRST_OTG 92 +#define SRST_OTG 93 +#define SRST_OTG_ADP 94 +#define HRST_HOST0 95 + +#define HRST_HOST0_AUX 96 +#define HRST_HOST0_ARB 97 +#define SRST_HOST0_EHCIPHY 98 +#define SRST_HOST0_UTMI 99 +#define SRST_USBPOR 100 +#define SRST_UTMI0 101 +#define SRST_UTMI1 102 + +#define ARST_VIO0_NIU 102 +#define ARST_VIO1_NIU 103 +#define HRST_VIO_NIU 104 +#define PRST_VIO_NIU 105 +#define ARST_VOP 106 +#define HRST_VOP 107 +#define DRST_VOP 108 +#define ARST_IEP 109 +#define HRST_IEP 110 +#define ARST_RGA 111 +#define HRST_RGA 112 +#define SRST_RGA 113 +#define PRST_CVBS 114 +#define PRST_HDMI 115 +#define SRST_HDMI 116 +#define PRST_MIPI_DSI 117 + +#define ARST_ISP_NIU 118 +#define HRST_ISP_NIU 119 +#define HRST_ISP 120 +#define SRST_ISP 121 +#define ARST_VIP0 122 +#define HRST_VIP0 123 +#define PRST_VIP0 124 +#define ARST_VIP1 125 +#define HRST_VIP1 126 +#define PRST_VIP1 127 +#define ARST_VIP2 128 +#define HRST_VIP2 129 +#define PRST_VIP2 120 +#define ARST_VIP3 121 +#define HRST_VIP3 122 +#define PRST_VIP4 123 + +#define PRST_CIF1TO4 124 +#define SRST_CVBS_CLK 125 +#define HRST_CVBS 126 + +#define ARST_VPU_NIU 140 +#define HRST_VPU_NIU 141 +#define ARST_VPU 142 +#define HRST_VPU 143 +#define ARST_RKVDEC_NIU 144 +#define HRST_RKVDEC_NIU 145 +#define ARST_RKVDEC 146 +#define HRST_RKVDEC 147 +#define SRST_RKVDEC_CABAC 148 +#define SRST_RKVDEC_CORE 149 +#define ARST_RKVENC_NIU 150 +#define HRST_RKVENC_NIU 151 +#define ARST_RKVENC 152 +#define HRST_RKVENC 153 +#define SRST_RKVENC_CORE 154 + +#define SRST_DSP_CORE 156 +#define SRST_DSP_SYS 157 +#define SRST_DSP_GLOBAL 158 +#define SRST_DSP_OECM 159 +#define PRST_DSP_IOP_NIU 160 +#define ARST_DSP_EPP_NIU 161 +#define ARST_DSP_EDP_NIU 162 +#define PRST_DSP_DBG_NIU 163 +#define PRST_DSP_CFG_NIU 164 +#define PRST_DSP_GRF 165 +#define PRST_DSP_MAILBOX 166 +#define PRST_DSP_INTC 167 +#define PRST_DSP_PFM_MON 169 +#define SRST_DSP_PFM_MON 170 +#define ARST_DSP_EDAP_NIU 171 + +#define SRST_PMU 172 +#define SRST_PMU_I2C0 173 +#define PRST_PMU_I2C0 174 +#define PRST_PMU_GPIO0 175 +#define PRST_PMU_INTMEM 176 +#define PRST_PMU_PWM0 177 +#define SRST_PMU_PWM0 178 +#define PRST_PMU_GRF 179 +#define SRST_PMU_NIU 180 +#define SRST_PMU_PVTM 181 +#define ARST_DSP_EDP_PERF 184 +#define ARST_DSP_EPP_PERF 185 + +#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */

Add basic support for rv1108 evb, whith this patch we can boot into u-boot console.

Signed-off-by: Andy Yan andy.yan@rock-chips.com ---

arch/arm/dts/Makefile | 3 +- arch/arm/dts/rv1108-evb.dts | 54 ++++ arch/arm/dts/rv1108.dtsi | 479 +++++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rv1108/Kconfig | 19 ++ board/rockchip/evb_rv1108/Kconfig | 15 ++ board/rockchip/evb_rv1108/MAINTAINERS | 6 + board/rockchip/evb_rv1108/Makefile | 7 + board/rockchip/evb_rv1108/README | 47 ++++ board/rockchip/evb_rv1108/evb_rv1108.c | 52 ++++ configs/evb-rv1108_defconfig | 40 +++ include/configs/evb_rv1108.h | 26 ++ 11 files changed, 747 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rv1108-evb.dts create mode 100644 arch/arm/dts/rv1108.dtsi create mode 100644 board/rockchip/evb_rv1108/Kconfig create mode 100644 board/rockchip/evb_rv1108/MAINTAINERS create mode 100644 board/rockchip/evb_rv1108/Makefile create mode 100644 board/rockchip/evb_rv1108/README create mode 100644 board/rockchip/evb_rv1108/evb_rv1108.c create mode 100644 configs/evb-rv1108_defconfig create mode 100644 include/configs/evb_rv1108.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4621c6f..a777384 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -46,7 +46,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3368-px5-evb.dtb \ rk3399-evb.dtb \ rk3399-firefly.dtb \ - rk3399-puma.dtb + rk3399-puma.dtb \ + rv1108-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts new file mode 100644 index 0000000..0128dd8 --- /dev/null +++ b/arch/arm/dts/rv1108-evb.dts @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "rv1108.dtsi" + +/ { + model = "Rockchip RV1108 Evaluation board"; + compatible = "rockchip,rv1108-evb", "rockchip,rv1108"; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x08000000>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + status = "okay"; + clock_in_out = <0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; +}; + +&sfc { + status = "okay"; + flash@0 { + compatible = "gd25q256","spi-flash"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + spi-max-frequency = <96000000>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi new file mode 100644 index 0000000..77ca24e --- /dev/null +++ b/arch/arm/dts/rv1108.dtsi @@ -0,0 +1,479 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/rv1108-cru.h> +#include <dt-bindings/pinctrl/rockchip.h> +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1108"; + + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + spi0 = &sfc; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@102a0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x102a0000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + }; + + bus_intmem@10080000 { + compatible = "mmio-sram"; + reg = <0x10080000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x10080000 0x2000>; + }; + + uart2: serial@10210000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10210000 0x100>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart1: serial@10220000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10220000 0x100>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart0: serial@10230000 { + compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; + reg = <0x10230000 0x100>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + grf: syscon@10300000 { + compatible = "rockchip,rv1108-grf", "syscon"; + reg = <0x10300000 0x1000>; + }; + + pmugrf: syscon@20060000 { + compatible = "rockchip,rv1108-pmugrf", "syscon"; + reg = <0x20060000 0x1000>; + }; + + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + emmc: dwmmc@30110000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30110000 0x4000>; + status = "disabled"; + }; + + sdio: dwmmc@30120000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30120000 0x4000>; + status = "disabled"; + }; + + sdmmc: dwmmc@30130000 { + compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; + clock-freq-min-max = <400000 100000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30130000 0x4000>; + status = "disabled"; + }; + + sfc: sfc@301c0000 { + compatible = "rockchip,sfc"; + reg = <0x301c0000 0x200>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&sfc_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + + gmac: ethernet@30200000 { + compatible = "rockchip,rv1108-gmac"; + reg = <0x30200000 0x10000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, + <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + phy-mode = "rmii"; + max-speed = <100>; + status = "disabled"; + }; + + gic: interrupt-controller@32010000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x32011000 0x1000>, + <0x32012000 0x1000>, + <0x32014000 0x2000>, + <0x32016000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1108-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@20030000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20030000 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@10310000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10310000 0x100>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@10320000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10320000 0x100>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@10330000 { + compatible = "rockchip,gpio-bank"; + reg = <0x10330000 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xin24m>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { + drive-strength = <12>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { + drive-strength = <4>; + }; + + pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + gmac { + rmii_pins: rmii-pins { + rockchip,pins = <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PC4 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB3 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB4 RK_FUNC_3 &pcfg_pull_none_drv_12ma>, + <1 RK_PB5 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PB6 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PB7 RK_FUNC_3 &pcfg_pull_none>, + <1 RK_PC2 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>; + }; + + i2c2m1_gpio: i2c2m1-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c2m05v { + i2c2m05v_xfer: i2c2m05v-xfer { + rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>; + }; + + i2c2m05v_gpio: i2c2m05v-gpio { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, + <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + sfc { + sfc_pins: sfc-pins { + rockchip,pins = <2 RK_PA3 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PA2 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PA1 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PA0 RK_FUNC_3 &pcfg_pull_none>, + <2 RK_PB7 RK_FUNC_2 &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>, + <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>, + <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart01rts: uart1-rts { + rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>, + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart2m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>, + <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2_5v { + uart2_5v_cts: uart2_5v-cts { + rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart2_5v_rts: uart2_5v-rts { + rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index 40237bb..e6cba66 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -1,9 +1,28 @@ if ROCKCHIP_RV1108

+config TARGET_EVB_RV1108 + bool "EVB_RV1108" + help + RV1108 EVB is a evaluation board for Rockchp RV1108. + + Key features of the board include: + * one macro USB OTG port + * one USB HOST port + * one RS232 to USB port route to UART2 as debug port + * MIPI screen with resolution 720 x 1280 + * 128M DDR3 + * 64M SPI Nor Flash + * macro SD card interface + * HDMI output + * 10/100 Mbps Ethernet + * camera interface compatible with imx323 / ov2710 / ov4689 + config SYS_SOC default "rockchip"

config SYS_MALLOC_F_LEN default 0x400

+source board/rockchip/evb_rv1108/Kconfig + endif diff --git a/board/rockchip/evb_rv1108/Kconfig b/board/rockchip/evb_rv1108/Kconfig new file mode 100644 index 0000000..4a76e0b --- /dev/null +++ b/board/rockchip/evb_rv1108/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RV1108 + +config SYS_BOARD + default "evb_rv1108" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rv1108" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rv1108/MAINTAINERS b/board/rockchip/evb_rv1108/MAINTAINERS new file mode 100644 index 0000000..94def32 --- /dev/null +++ b/board/rockchip/evb_rv1108/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RV1108 +M: Andy Yan andy.yan@rock-chips.com +S: Maintained +F: board/rockchip/evb_rv1108 +F: include/configs/evb_rv1108.h +F: configs/evb-rv1108_defconfig diff --git a/board/rockchip/evb_rv1108/Makefile b/board/rockchip/evb_rv1108/Makefile new file mode 100644 index 0000000..dd99054 --- /dev/null +++ b/board/rockchip/evb_rv1108/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rv1108.o diff --git a/board/rockchip/evb_rv1108/README b/board/rockchip/evb_rv1108/README new file mode 100644 index 0000000..5889596 --- /dev/null +++ b/board/rockchip/evb_rv1108/README @@ -0,0 +1,47 @@ +Here is the step-by-step to boot U-Boot on rv1108 evb. + +Get ddr init binary +============================================================================== + > git clone https://github.com/rockchip-linux/rkbin.git + > dd if=./rkbin/rv1x/rv1108ddr.bin of=ddr.bin bs=4 skip=1 + +Compile U-Boot +=========================== + > make CROSS_COMPILE=arm-linux-gnueabi- evb-rv1108_defconfig all + > ./tools/mkimage -n rv1108 -T rksd -d ddr.bin spl.bin + > cat spl.bin u-boot.bin > u-boot.img + +Flash the image by rkdeveloptool +================================ +rkdeveloptool can get from https://github.com/rockchip-linux/rkdeveloptool.git + +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + > rkdeveloptool db ./rkbin/rv1x/RV1108_usb_boot.bin + > rkdeveloptool wl 0x40 u-boot.img + > rkdeveloptool RD + +You should be able to get U-Boot log message from boot console: + +DDR Version V1.02 20170220 +In +400MHz +DDR3 +Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB +mach:2 +OUT + + +U-Boot 2017.05-00693-g3a5b171 (Jun 01 2017 - 17:37:53 +0800) + +Model: Rockchip RV1108 Evaluation board +DRAM: 128 MiB +APLL: 600000000 DPLL:792000000 GPLL:384000000 +MMC: +Using default environment + +In: serial@10210000 +Out: serial@10210000 +Err: serial@10210000 +Net: No ethernet found. +Hit any key to stop autoboot: 0 +=> diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c new file mode 100644 index 0000000..fe37eac --- /dev/null +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -0,0 +1,52 @@ +/* + * (C)Copyright 2016 Rockchip Electronics Co., Ltd + * Authors: Andy Yan andy.yan@rock-chips.com + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <fdtdec.h> +#include <asm/arch/grf_rv1108.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int mach_cpu_init(void) +{ + int node; + struct rv1108_grf *grf; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf"); + grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); + + /*evb board use UART2 m0 for debug*/ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D2_MASK | GPIO2D1_MASK, + GPIO2D2_UART2_SOUT_M0 << GPIO2D2_SHIFT | + GPIO2D1_UART2_SIN_M0 << GPIO2D1_SHIFT); + rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); + + return 0; +} + + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x8000000; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = 0x60000000; + gd->bd->bi_dram[0].size = 0x8000000; + + return 0; +} diff --git a/configs/evb-rv1108_defconfig b/configs/evb-rv1108_defconfig new file mode 100644 index 0000000..3fa1ae8 --- /dev/null +++ b/configs/evb-rv1108_defconfig @@ -0,0 +1,40 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_ROCKCHIP_RV1108=y +CONFIG_TARGET_EVB_RV1108=y +CONFIG_DEFAULT_DEVICE_TREE="rv1108-evb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RV1108=y +CONFIG_RAM=y +CONFIG_BAUDRATE=1500000 +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x10210000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h new file mode 100644 index 0000000..ff3531b --- /dev/null +++ b/include/configs/evb_rv1108.h @@ -0,0 +1,26 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/rv1108_common.h> + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ipaddr=172.16.12.50\0" \ + "serverip=172.16.12.69\0" \ + "" +#define CONFIG_BOOTCOMMAND \ + "sf probe;" \ + "sf read 0x62000000 0x140800 0x500000;" \ + "dcache off;" \ + "go 0x62000000" + +#endif