[U-Boot] [PATCH 0/2] sunxi: FEL boot mode improvements
Hello,
One of the current FEL problems is a very limited available SRAM space, so that trying to add new code to u-boot or even changing the GCC version introduces a risk of exceeding it. Another problem is that booting a Linux system on Allwinner A10/A13 devices in FEL mode ends up with L2 cache disabled, and this is not very nice for the performance. These two patches make FEL boot mode more usable.
Siarhei Siamashka (2): sunxi: Use Thumb2 and move stack to gain more SRAM space in FEL mode sunxi: Set the AUXCR L2EN bit for sun4i/sun5i in FEL boot mode
arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/board.c | 12 +++++++++ arch/arm/cpu/armv7/sunxi/start_fel.S | 42 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 4 +-- include/configs/sunxi-common.h | 2 -- 5 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
The Allwinner SoCs support a special FEL boot mode, which can be activated by users via a button press (or other means). In the FEL mode, the BROM implements a custom FEL protocol over USB, which allows to upload code to the device and run it. This protocol had been reverse engineered and documented by Henrik Nordström:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
Because the BROM code is using some parts of the SRAM for itself, only a few areas are available for use in u-boot. Currently the SPL is loaded into the "0x2000-0x5cff Free for program use" area and the stack pointer is at the end of this area. This is barely enough to fit just the current SPL and leaves almost no headroom for the future code.
This patch enables the use of a more compact Thumb2 mode for compiling the FEL SPL binary. And also relocates the stack to another "0x8000-0xbfff Free for program use" area. Additionally, the BSS segment is cleared.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/start_fel.S | 42 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 4 +-- include/configs/sunxi-common.h | 2 -- 4 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a64bfa1..b3eff98 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -21,5 +21,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o +extra-y += start_fel.o endif endif diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S b/arch/arm/cpu/armv7/sunxi/start_fel.S new file mode 100644 index 0000000..2789fd9 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start_fel.S @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2014 Siarhei Siamashka siarhei.siamashka@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.syntax unified +.text +.arm +.arch armv7a +.p2align 2 + +.globl _start_fel +.globl s_init +.globl __bss_start +.globl __bss_end + +_start_fel: + /* Relocate stack to the 0x8000-0xBFFF area */ + mov r0, #0xC000 + str sp, [r0, #-4]! + str lr, [r0, #-4]! + adr lr, _exit_fel /* Return back to '_exit_fel' */ + mov sp, r0 + + /* Erase the BSS segment */ + ldr r0, =__bss_start + ldr r1, =__bss_end + mov r2, #0 +0: cmp r0, r1 + strbne r2, [r0], #1 + bne 0b + + /* Pass control to the 's_init()' function */ + b s_init + +_exit_fel: + /* Relocate stack back and return */ + mov r0, #0xC000 + ldr sp, [r0, #-4]! + ldr lr, [r0, #-4]! + bx lr diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds index 364e35c..418c2fc 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -6,7 +6,7 @@ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -ENTRY(s_init) +ENTRY(_start_fel) SECTIONS { . = 0x00002000; @@ -14,7 +14,7 @@ SECTIONS . = ALIGN(4); .text : { - *(.text.s_init) + arch/arm/cpu/armv7/sunxi/start_fel.o (.text) *(.text*) }
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d72d62..4b980e9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -18,10 +18,8 @@ */ #define CONFIG_SUNXI /* sunxi family */ #ifdef CONFIG_SPL_BUILD -#ifndef CONFIG_SPL_FEL #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#endif
#include <asm/arch/cpu.h> /* get chip and board defs */
Hi,
On 07/18/2014 07:09 PM, Siarhei Siamashka wrote:
The Allwinner SoCs support a special FEL boot mode, which can be activated by users via a button press (or other means). In the FEL mode, the BROM implements a custom FEL protocol over USB, which allows to upload code to the device and run it. This protocol had been reverse engineered and documented by Henrik Nordström:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.htmlBecause the BROM code is using some parts of the SRAM for itself, only a few areas are available for use in u-boot. Currently the SPL is loaded into the "0x2000-0x5cff Free for program use" area and the stack pointer is at the end of this area. This is barely enough to fit just the current SPL and leaves almost no headroom for the future code.
This patch enables the use of a more compact Thumb2 mode for compiling the FEL SPL binary. And also relocates the stack to another "0x8000-0xbfff Free for program use" area. Additionally, the BSS segment is cleared.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
Looks good:
Acked-by: Hans de Goede hdegoede@redhat.com
Regards,
Hans
arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/start_fel.S | 42 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 4 +-- include/configs/sunxi-common.h | 2 -- 4 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a64bfa1..b3eff98 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -21,5 +21,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o +extra-y += start_fel.o endif endif diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S b/arch/arm/cpu/armv7/sunxi/start_fel.S new file mode 100644 index 0000000..2789fd9 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start_fel.S @@ -0,0 +1,42 @@ +/*
- Copyright (c) 2014 Siarhei Siamashka siarhei.siamashka@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+.syntax unified +.text +.arm +.arch armv7a +.p2align 2
+.globl _start_fel +.globl s_init +.globl __bss_start +.globl __bss_end
+_start_fel:
- /* Relocate stack to the 0x8000-0xBFFF area */
- mov r0, #0xC000
- str sp, [r0, #-4]!
- str lr, [r0, #-4]!
- adr lr, _exit_fel /* Return back to '_exit_fel' */
- mov sp, r0
- /* Erase the BSS segment */
- ldr r0, =__bss_start
- ldr r1, =__bss_end
- mov r2, #0
+0: cmp r0, r1
- strbne r2, [r0], #1
- bne 0b
- /* Pass control to the 's_init()' function */
- b s_init
+_exit_fel:
- /* Relocate stack back and return */
- mov r0, #0xC000
- ldr sp, [r0, #-4]!
- ldr lr, [r0, #-4]!
- bx lr
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds index 364e35c..418c2fc 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -6,7 +6,7 @@ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -ENTRY(s_init) +ENTRY(_start_fel) SECTIONS { . = 0x00002000; @@ -14,7 +14,7 @@ SECTIONS . = ALIGN(4); .text : {
*(.text.s_init)
arch/arm/cpu/armv7/sunxi/start_fel.o (.text)diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d72d62..4b980e9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -18,10 +18,8 @@ */ #define CONFIG_SUNXI /* sunxi family */ #ifdef CONFIG_SPL_BUILD -#ifndef CONFIG_SPL_FEL #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#endif
#include <asm/arch/cpu.h> /* get chip and board defs */
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
I think a better reference is https://github.com/hno/Allwinner-Info/blob/master/FEL-usb/USB-protocol.txt
+.syntax unified +.text +.arm +.arch armv7a +.p2align 2
+.globl _start_fel
Is there any reason not to use ENTRY() for this?
+.globl s_init +.globl __bss_start +.globl __bss_end
I don't think you need .globl to access external symbols, all .globl does is control the visibility of things defined in this file. IOW you can drop all 3 of these AFAICT.
[...]
- /* Pass control to the 's_init()' function */
- b s_init
Since this code is in arm mode and s_init will, I think, be in Thumb mode after this patch shouldn't this be a bx?
Ian.
On Mon, 21 Jul 2014 19:31:45 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
I think a better reference is https://github.com/hno/Allwinner-Info/blob/master/FEL-usb/USB-protocol.txt
Yes, very likely. Except that I'm a little bit concerned about the long term availability of this link (which is a personal repository on github).
I have quoted the relevant parts of the memory map information in the commit message. But now I wonder if we should replicate the Allwinner FEL mode memory map information somewhere in the u-boot documentation?
+.syntax unified +.text +.arm +.arch armv7a +.p2align 2
+.globl _start_fel
Is there any reason not to use ENTRY() for this?
Yes, we can use it. Thanks for the hint.
+.globl s_init +.globl __bss_start +.globl __bss_end
I don't think you need .globl to access external symbols, all .globl does is control the visibility of things defined in this file. IOW you can drop all 3 of these AFAICT.
You are right, "info as" indeed says that "`as' treats all undefined symbols as external"
[...]
- /* Pass control to the 's_init()' function */
- b s_init
Since this code is in arm mode and s_init will, I think, be in Thumb mode after this patch shouldn't this be a bx?
Since this branch instruction refers to an external symbol, the linker has all the necessary information and takes care of handling Thumb interworking whenever it is necessary.
And GCC is normally using 'b' and 'bl' instructions in such cases. For example, let's have a look at the following C source code:
extern int bar(void); int foo(int (*baz)(void)) { return bar() + baz(); }
If we compile it as "-march=armv7-a -O2 -marm", then we get the following code in the object file:
00000000 <foo>: 0: e92d4038 push {r3, r4, r5, lr} 4: e1a05000 mov r5, r0 8: ebfffffe bl 0 <bar> c: e1a04000 mov r4, r0 10: e12fff35 blx r5 14: e0840000 add r0, r4, r0 18: e8bd8038 pop {r3, r4, r5, pc}
However if we link the very same object file into an executable (with the 'bar' function compiled in Thumb2 mode), the linker does the 'bl' -> 'blx' conversion automatically:
00008440 <bar>: 8440: 2001 movs r0, #1 8442: 4770 bx lr
00008444 <foo>: 8444: e92d4038 push {r3, r4, r5, lr} 8448: e1a05000 mov r5, r0 844c: fafffffb blx 8440 <bar> 8450: e1a04000 mov r4, r0 8454: e12fff35 blx r5 8458: e0840000 add r0, r4, r0 845c: e8bd8038 pop {r3, r4, r5, pc}
Hi,
On Fri, Jul 25, 2014 at 11:01 AM, Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
On Mon, 21 Jul 2014 19:31:45 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
I think a better reference is https://github.com/hno/Allwinner-Info/blob/master/FEL-usb/USB-protocol.txt
Yes, very likely. Except that I'm a little bit concerned about the long term availability of this link (which is a personal repository on github).
Stupid question: why isn't this on the wiki?
Thanks,
Hi,
On Fri, Jul 25, 2014 at 11:03 AM, Julian Calaby julian.calaby@gmail.com wrote:
Hi,
On Fri, Jul 25, 2014 at 11:01 AM, Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
On Mon, 21 Jul 2014 19:31:45 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
I think a better reference is https://github.com/hno/Allwinner-Info/blob/master/FEL-usb/USB-protocol.txt
Yes, very likely. Except that I'm a little bit concerned about the long term availability of this link (which is a personal repository on github).
Stupid question: why isn't this on the wiki?
Stupider question: why not add it myself?
It's now on the linux-sunxi wiki at:
http://linux-sunxi.org/FEL/Protocol
Thanks,
On Fri, 2014-07-25 at 04:01 +0300, Siarhei Siamashka wrote:
On Mon, 21 Jul 2014 19:31:45 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Fri, 2014-07-18 at 20:09 +0300, Siarhei Siamashka wrote:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.html
I think a better reference is https://github.com/hno/Allwinner-Info/blob/master/FEL-usb/USB-protocol.txt
Yes, very likely. Except that I'm a little bit concerned about the long term availability of this link (which is a personal repository on github).
I have quoted the relevant parts of the memory map information in the commit message. But now I wonder if we should replicate the Allwinner FEL mode memory map information somewhere in the u-boot documentation?
Or move it to the sunxi wiki?
[...]
- /* Pass control to the 's_init()' function */
- b s_init
Since this code is in arm mode and s_init will, I think, be in Thumb mode after this patch shouldn't this be a bx?
Since this branch instruction refers to an external symbol, the linker has all the necessary information and takes care of handling Thumb interworking whenever it is necessary.
OK.
On Fri, 18 Jul 2014 20:09:44 +0300 Siarhei Siamashka siarhei.siamashka@gmail.com wrote:
The Allwinner SoCs support a special FEL boot mode, which can be activated by users via a button press (or other means). In the FEL mode, the BROM implements a custom FEL protocol over USB, which allows to upload code to the device and run it. This protocol had been reverse engineered and documented by Henrik Nordström:
http://lists.phcomp.co.uk/pipermail/arm-netbook/2012-June/004341.htmlBecause the BROM code is using some parts of the SRAM for itself, only a few areas are available for use in u-boot. Currently the SPL is loaded into the "0x2000-0x5cff Free for program use" area and the stack pointer is at the end of this area. This is barely enough to fit just the current SPL and leaves almost no headroom for the future code.
This patch enables the use of a more compact Thumb2 mode for compiling the FEL SPL binary. And also relocates the stack to another "0x8000-0xbfff Free for program use" area.
Self review.
Maybe instead of adding the stack relocation hacks, a better idea would be to just change the usb-boot script to load the SPL to 0x8000 address instead of 0x2000? The relevant usb-boot code is here:
https://github.com/linux-sunxi/sunxi-tools/blob/e2a3f16e36f6/usb-boot#L73
In this case the stack would remain in the 0x2000-0x5cff area, and the code/data would use 0x8000-0xbfff. However backwards compatibility with the existing sunxi-tools becomes an issue. Does anyone have any opinion?
Additionally, the BSS segment is cleared.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/start_fel.S | 42 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 4 +-- include/configs/sunxi-common.h | 2 -- 4 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/start_fel.S
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a64bfa1..b3eff98 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -21,5 +21,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SUN7I) += dram.o ifdef CONFIG_SPL_FEL obj-y += start.o +extra-y += start_fel.o endif endif diff --git a/arch/arm/cpu/armv7/sunxi/start_fel.S b/arch/arm/cpu/armv7/sunxi/start_fel.S new file mode 100644 index 0000000..2789fd9 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start_fel.S @@ -0,0 +1,42 @@ +/*
- Copyright (c) 2014 Siarhei Siamashka siarhei.siamashka@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+.syntax unified +.text +.arm +.arch armv7a +.p2align 2
+.globl _start_fel +.globl s_init +.globl __bss_start +.globl __bss_end
+_start_fel:
- /* Relocate stack to the 0x8000-0xBFFF area */
- mov r0, #0xC000
- str sp, [r0, #-4]!
- str lr, [r0, #-4]!
- adr lr, _exit_fel /* Return back to '_exit_fel' */
- mov sp, r0
- /* Erase the BSS segment */
- ldr r0, =__bss_start
- ldr r1, =__bss_end
- mov r2, #0
+0: cmp r0, r1
- strbne r2, [r0], #1
- bne 0b
- /* Pass control to the 's_init()' function */
- b s_init
+_exit_fel:
- /* Relocate stack back and return */
- mov r0, #0xC000
- ldr sp, [r0, #-4]!
- ldr lr, [r0, #-4]!
- bx lr
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds index 364e35c..418c2fc 100644 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds @@ -6,7 +6,7 @@ */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) -ENTRY(s_init) +ENTRY(_start_fel) SECTIONS { . = 0x00002000; @@ -14,7 +14,7 @@ SECTIONS . = ALIGN(4); .text : {
*(.text.s_init)
arch/arm/cpu/armv7/sunxi/start_fel.o (.text)diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5d72d62..4b980e9 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -18,10 +18,8 @@ */ #define CONFIG_SUNXI /* sunxi family */ #ifdef CONFIG_SPL_BUILD -#ifndef CONFIG_SPL_FEL #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#endif
#include <asm/arch/cpu.h> /* get chip and board defs */
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com --- arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..86cf4c9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -69,6 +69,18 @@ void s_init(void) "mcr p15, 0, r0, c1, c0, 1\n"); #endif
+#if defined(CONFIG_SPL_FEL) && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)) + /* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is + * set by the BROM code in the "normal" mode, but not in the "FEL" mode. + * Here we fix this inconsistency in the Auxiliary Ctl reg by also + * setting the missing L2EN bit. + */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #2\n" + "mcr p15, 0, r0, c1, c0, 1\n" : : : "r0"); +#endif + clock_init(); timer_init(); gpio_init();
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue.
Regards, Jeroen
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue.
The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode.
In any case I think these sorts of low level platform specific details are the sort of thing which the bootloader probably ought to be setting up.
Ian
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue.
The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode.
mmm, I guess there is something wrong with the boot sequence if the kernel itself can't access raw hw.
In any case I think these sorts of low level platform specific details are the sort of thing which the bootloader probably ought to be setting up.
No, u-boot tries not to touch anything it doesn't use and, if anything disables it after use. Hence, this seems like a kernel bug and nothing to do with u-boot. They should be independent, iow a kernel should not rely on u-boot setting thing up, that is a bug.
Regards, Jeroen
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote:
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue.
The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode.
mmm, I guess there is something wrong with the boot sequence if the kernel itself can't access raw hw.
Do you know what ARM Secure and Non-Secure worlds are?
The kernel expects to be launched in NS mode and simply cannot access this register. This is a feature not a bug.
Ian.
On Mon, 21 Jul 2014 21:59:51 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote:
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue.
The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode.
mmm, I guess there is something wrong with the boot sequence if the kernel itself can't access raw hw.
Do you know what ARM Secure and Non-Secure worlds are?
The kernel expects to be launched in NS mode and simply cannot access this register. This is a feature not a bug.
Just curious. Is there a modern consensus about how this all is supposed to be done nowadays?
The last time I read anything about this subject was the following longish and already old discussion thread (which has probably already lost relevance): http://lists.linaro.org/pipermail/boot-architecture/2011-August/000060.html
Since the Allwinner BROM does not forcefully drop us to the non-secure mode, we have the absolute freedom of choice and may implement any policy.
On Fri, 2014-07-25 at 03:21 +0300, Siarhei Siamashka wrote:
On Mon, 21 Jul 2014 21:59:51 +0100 Ian Campbell ijc@hellion.org.uk wrote:
On Mon, 2014-07-21 at 22:39 +0200, Jeroen Hofstee wrote:
Hello Ian,
On 21-07-14 22:07, Ian Campbell wrote:
On Fri, 2014-07-18 at 20:47 +0200, Jeroen Hofstee wrote:
Hello Siarhei,
On 18-07-14 19:09, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
I don't know a single about the sunxi, but shouldn't linux be patched instead. The commit message seems to indicate it is not an u-boot issue.
The ACTLR may not be writeable from NS mode so it has to be setup in the bootloader before dropping to NS mode.
mmm, I guess there is something wrong with the boot sequence if the kernel itself can't access raw hw.
Do you know what ARM Secure and Non-Secure worlds are?
The kernel expects to be launched in NS mode and simply cannot access this register. This is a feature not a bug.
Just curious. Is there a modern consensus about how this all is supposed to be done nowadays?
The kernel's Booting.txt strongly encourages you to enter in HYP mode if it is available, which implies NS mode.
This a basic requirement to use virtualisation (Xen or KVM etc).
I believe that the general consensus is to run in NS mode on newer platforms by default.
FWIW on v8 arm64 Linux documentation requires NS mode.
The last time I read anything about this subject was the following longish and already old discussion thread (which has probably already lost relevance): http://lists.linaro.org/pipermail/boot-architecture/2011-August/000060.html
Since the Allwinner BROM does not forcefully drop us to the non-secure mode, we have the absolute freedom of choice and may implement any policy.
We do, and we should implement PSCI and NS boot for kernels.
Ian.
Hi,
On 07/18/2014 07:09 PM, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..86cf4c9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -69,6 +69,18 @@ void s_init(void) "mcr p15, 0, r0, c1, c0, 1\n"); #endif
+#if defined(CONFIG_SPL_FEL) && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I))
- /* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is
* set by the BROM code in the "normal" mode, but not in the "FEL" mode.* Here we fix this inconsistency in the Auxiliary Ctl reg by also* setting the missing L2EN bit.*/- asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n""orr r0, r0, #2\n""mcr p15, 0, r0, c1, c0, 1\n" : : : "r0");+#endif
Wouldn't it be better to do this in the start_fel.S file you've introduced in the first patch of this series ?
Regards,
Hans
On Sat, 2014-07-19 at 13:20 +0200, Hans de Goede wrote:
Hi,
On 07/18/2014 07:09 PM, Siarhei Siamashka wrote:
This is needed to have feature parity with the normal boot mode, where the L2EN bit in the CP15 Auxiliary Control Register is set by the BROM code right from the start.
If this is not done, the Linux system ends up booted with the L2 cache disabled.
Signed-off-by: Siarhei Siamashka siarhei.siamashka@gmail.com
arch/arm/cpu/armv7/sunxi/board.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 49c9448..86cf4c9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -69,6 +69,18 @@ void s_init(void) "mcr p15, 0, r0, c1, c0, 1\n"); #endif
+#if defined(CONFIG_SPL_FEL) && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I))
- /* For ARM Cortex-A8 based hardware (sun4i and sun5i), the L2EN bit is
* set by the BROM code in the "normal" mode, but not in the "FEL" mode.* Here we fix this inconsistency in the Auxiliary Ctl reg by also* setting the missing L2EN bit.*/- asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n""orr r0, r0, #2\n""mcr p15, 0, r0, c1, c0, 1\n" : : : "r0");+#endif
Wouldn't it be better to do this in the start_fel.S file you've introduced in the first patch of this series ?
That wouldn't remove the need for the ifdef if that's what you are thinking since it still needs to be sun4i/sun5i specific.
I think doing it here is in keeping with setting ACTLR.SMP on the sun6i/sun7i platforms which is just above the context here.
Acked-by: Ian Campbell ijc@hellion.org.uk
Although I also wouldn't object to doing it in in start_fel.S if that is preferred.
I expect this needs to be done on secondary processors. Need to keep that in mind if/when someone works on PSCI for sun[45]i.
Ian.
On Mon, 2014-07-21 at 19:39 +0100, Ian Campbell wrote:
I expect this needs to be done on secondary processors. Need to keep that in mind if/when someone works on PSCI for sun[45]i.
Except as Tom points out on IRC, sun[45]i are both single core... Oops!
Ian.
participants (5)
-
Hans de Goede -
Ian Campbell -
Jeroen Hofstee -
Julian Calaby -
Siarhei Siamashka