[U-Boot] [PATCH] stx: create common vendor hierarchy for Silicon Turnkey boards
From: Alex Dubov oakad@yahoo.com
Move board definition files for STx XTC, GP3 and SSA boards into common subdirectory and factor out common code.
"-mno-spe" flag common to all MPC85xx configurations does not work so change it to "-mspe=no" which does (GCC bug 37759).
Signed-off-by: Alex Dubov oakad@yahoo.com --- Makefile | 6 +- board/{stxgp3 => stx/common}/Makefile | 20 +++-- board/{stxssa => stx/common}/ddr.c | 46 ++++++++--- board/{stxssa => stx/common}/law.c | 30 ++++--- board/{stxssa => stx/common}/tlb.c | 72 ++++++++++------- board/{ => stx}/stxgp3/Makefile | 3 - board/{ => stx}/stxgp3/config.mk | 0 board/{ => stx}/stxgp3/flash.c | 0 board/{ => stx}/stxgp3/stxgp3.c | 0 board/{ => stx}/stxgp3/u-boot.lds | 0 board/{ => stx}/stxssa/Makefile | 3 - board/{ => stx}/stxssa/config.mk | 0 board/{ => stx}/stxssa/stxssa.c | 0 board/{ => stx}/stxssa/u-boot.lds | 0 board/{ => stx}/stxxtc/Makefile | 0 board/{ => stx}/stxxtc/config.mk | 0 board/{ => stx}/stxxtc/stxxtc.c | 0 board/{ => stx}/stxxtc/u-boot.lds | 0 board/{ => stx}/stxxtc/u-boot.lds.debug | 0 board/stxgp3/ddr.c | 76 ------------------ board/stxgp3/law.c | 58 -------------- board/stxgp3/tlb.c | 130 ------------------------------- cpu/mpc85xx/config.mk | 2 +- include/configs/stxgp3.h | 21 +++-- include/configs/stxssa.h | 28 ++++--- 25 files changed, 135 insertions(+), 360 deletions(-) copy board/{stxgp3 => stx/common}/Makefile (82%) rename board/{stxssa => stx/common}/ddr.c (57%) rename board/{stxssa => stx/common}/law.c (74%) rename board/{stxssa => stx/common}/tlb.c (59%) rename board/{ => stx}/stxgp3/Makefile (95%) rename board/{ => stx}/stxgp3/config.mk (100%) rename board/{ => stx}/stxgp3/flash.c (100%) rename board/{ => stx}/stxgp3/stxgp3.c (100%) rename board/{ => stx}/stxgp3/u-boot.lds (100%) rename board/{ => stx}/stxssa/Makefile (95%) rename board/{ => stx}/stxssa/config.mk (100%) rename board/{ => stx}/stxssa/stxssa.c (100%) rename board/{ => stx}/stxssa/u-boot.lds (100%) rename board/{ => stx}/stxxtc/Makefile (100%) rename board/{ => stx}/stxxtc/config.mk (100%) rename board/{ => stx}/stxxtc/stxxtc.c (100%) rename board/{ => stx}/stxxtc/u-boot.lds (100%) rename board/{ => stx}/stxxtc/u-boot.lds.debug (100%) delete mode 100644 board/stxgp3/ddr.c delete mode 100644 board/stxgp3/law.c delete mode 100644 board/stxgp3/tlb.c
diff --git a/Makefile b/Makefile index 8096f91..a445eba 100644 --- a/Makefile +++ b/Makefile @@ -1129,7 +1129,7 @@ SPD823TS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx
stxxtc_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc + @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc stx
svm_sc8xx_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx @@ -2526,7 +2526,7 @@ socrates_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
stxgp3_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 + @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx
stxssa_config \ stxssa_4M_config: unconfig @@ -2535,7 +2535,7 @@ stxssa_4M_config: unconfig echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \ $(XECHO) "... with 4 MiB flash memory" ; \ fi - @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa + @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa stx
TQM8540_config \ TQM8541_config \ diff --git a/board/stxgp3/Makefile b/board/stx/common/Makefile similarity index 82% copy from board/stxgp3/Makefile copy to board/stx/common/Makefile index 5a68f11..08cc2f9 100644 --- a/board/stxgp3/Makefile +++ b/board/stx/common/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,25 @@
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).a +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif
-COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-y += flash.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o +LIB = $(obj)lib$(VENDOR).a + +COBJS-${CONFIG_MPC85xx} += ddr.o +COBJS-${CONFIG_MPC85xx} += law.o +COBJS-${CONFIG_MPC85xx} += tlb.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS))
-$(LIB): $(obj).depend $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS)
clean: - rm -f $(OBJS) $(SOBJS) + rm -f $(SOBJS) $(OBJS)
distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/stxssa/ddr.c b/board/stx/common/ddr.c similarity index 57% rename from board/stxssa/ddr.c rename to board/stx/common/ddr.c index 93d1100..5e7b184 100644 --- a/board/stxssa/ddr.c +++ b/board/stx/common/ddr.c @@ -1,5 +1,6 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2009 Alex Dubov oakad@yahoo.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,31 +14,33 @@ #include <asm/fsl_ddr_dimm_params.h>
static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { +#if defined(CONFIG_FSL_DDR2) + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +#elif defined(CONFIG_FSL_DDR1) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +#else +#error DDR type is not defined +#endif }
- -unsigned int -fsl_ddr_get_mem_data_rate(void) +unsigned int fsl_ddr_get_mem_data_rate(void) { return get_ddr_freq(0); }
- -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { unsigned int i; - unsigned int i2c_address = 0; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + }
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); } }
@@ -46,11 +49,28 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) { /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 6; + + /* * Factors to consider for CPO: * - frequency * - ddr1 vs. ddr2 */ +#if defined(CONFIG_FSL_DDR2) + popts->cpo_override = 7; +#else popts->cpo_override = 0; +#endif
/* * Factors to consider for write data delay: diff --git a/board/stxssa/law.c b/board/stx/common/law.c similarity index 74% rename from board/stxssa/law.c rename to board/stx/common/law.c index 55dde66..a82c99f 100644 --- a/board/stxssa/law.c +++ b/board/stx/common/law.c @@ -1,9 +1,9 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. - * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright 2009 Alex Dubov oakad@yahoo.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,30 +31,34 @@ * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 512M + * 0xa000_0000 0xbfff_ffff PCI2 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xfaff_ffff Local bus 128M - * 0xfb00_0000 0xfb00_ffff Config Latch 64K - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * 0xf000_0000 0xffff_ffff LBC options + FLASH 256M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping */
struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#ifdef CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), +#ifdef CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_RIO_MEM_PHYS + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), +#endif + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC) };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxssa/tlb.c b/board/stx/common/tlb.c similarity index 59% rename from board/stxssa/tlb.c rename to board/stx/common/tlb.c index 0386432..6298eaa 100644 --- a/board/stxssa/tlb.c +++ b/board/stx/common/tlb.c @@ -1,9 +1,9 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. - * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Copyright 2009 Alex Dubov oakad@yahoo.com + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,76 +31,90 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
/* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 6M4 FLASH + * TLB 0: 256M Non-cacheable, guarded + * 0xf0000000 256M LBC (FLASH included) * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, + CONFIG_SYS_LBC_OPTION_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), + 0, 0, BOOKE_PAGESZ_256M, 1),
/* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * TLB 1: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), + 0, 1, BOOKE_PAGESZ_64M, 1),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1),
/* * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, + CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), +#endif
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS /* * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1),
/* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO + * TLB 5: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS /* * TLB 6: 256M Non-cacheable, guarded - * 0xf0000000 Local bus expansion option. - * 0xfb000000 Configuration Latch register (one word) - * 0xfc000000 Up to 64M flash */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 7: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), +#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stxgp3/Makefile b/board/stx/stxgp3/Makefile similarity index 95% rename from board/stxgp3/Makefile rename to board/stx/stxgp3/Makefile index 5a68f11..dce320c 100644 --- a/board/stxgp3/Makefile +++ b/board/stx/stxgp3/Makefile @@ -26,10 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o COBJS-y += flash.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/stxgp3/config.mk b/board/stx/stxgp3/config.mk similarity index 100% rename from board/stxgp3/config.mk rename to board/stx/stxgp3/config.mk diff --git a/board/stxgp3/flash.c b/board/stx/stxgp3/flash.c similarity index 100% rename from board/stxgp3/flash.c rename to board/stx/stxgp3/flash.c diff --git a/board/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c similarity index 100% rename from board/stxgp3/stxgp3.c rename to board/stx/stxgp3/stxgp3.c diff --git a/board/stxgp3/u-boot.lds b/board/stx/stxgp3/u-boot.lds similarity index 100% rename from board/stxgp3/u-boot.lds rename to board/stx/stxgp3/u-boot.lds diff --git a/board/stxssa/Makefile b/board/stx/stxssa/Makefile similarity index 95% rename from board/stxssa/Makefile rename to board/stx/stxssa/Makefile index 9ab41ec..c0e9798 100644 --- a/board/stxssa/Makefile +++ b/board/stx/stxssa/Makefile @@ -26,9 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/stxssa/config.mk b/board/stx/stxssa/config.mk similarity index 100% rename from board/stxssa/config.mk rename to board/stx/stxssa/config.mk diff --git a/board/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c similarity index 100% rename from board/stxssa/stxssa.c rename to board/stx/stxssa/stxssa.c diff --git a/board/stxssa/u-boot.lds b/board/stx/stxssa/u-boot.lds similarity index 100% rename from board/stxssa/u-boot.lds rename to board/stx/stxssa/u-boot.lds diff --git a/board/stxxtc/Makefile b/board/stx/stxxtc/Makefile similarity index 100% rename from board/stxxtc/Makefile rename to board/stx/stxxtc/Makefile diff --git a/board/stxxtc/config.mk b/board/stx/stxxtc/config.mk similarity index 100% rename from board/stxxtc/config.mk rename to board/stx/stxxtc/config.mk diff --git a/board/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c similarity index 100% rename from board/stxxtc/stxxtc.c rename to board/stx/stxxtc/stxxtc.c diff --git a/board/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds similarity index 100% rename from board/stxxtc/u-boot.lds rename to board/stx/stxxtc/u-boot.lds diff --git a/board/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug similarity index 100% rename from board/stxxtc/u-boot.lds.debug rename to board/stx/stxxtc/u-boot.lds.debug diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c deleted file mode 100644 index 93d1100..0000000 --- a/board/stxgp3/ddr.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <i2c.h> - -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> - -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twoT_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c deleted file mode 100644 index ba89f0e..0000000 --- a/board/stxgp3/law.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xfc00_0000 0xfc00_ffff Config Latch 64K - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c deleted file mode 100644 index aa11a5d..0000000 --- a/board/stxgp3/tlb.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 9e574a2..a7d948d 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -25,4 +25,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ -Wa,-me500 -msoft-float -mno-string -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) +PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=no) diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 0424e29..12df277 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -78,6 +78,7 @@ */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ @@ -195,18 +196,20 @@
/* RapdIO Map configuration, mapped 1:1. */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ +#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 +#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_VIRT CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
/* Standard 8560 PCI addressing, mapped 1:1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */
diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 2783f9e..1d2a52d 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -220,19 +220,21 @@ * Standard 8555 PCI mapping. * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
#if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_MPC85XX_PCI2 1
From: Alex Dubov oakad@yahoo.com
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM slot, ethernet on front panel and backplane, RapidIO on backplane, USB controller on local bus (not currently enabled) and no PCI of any kind.
Signed-off-by: Alex Dubov oakad@yahoo.com --- Makefile | 3 + board/stx/stxamc8548/Makefile | 51 ++++++ board/stx/stxamc8548/config.mk | 32 ++++ board/stx/stxamc8548/stxamc8548.c | 168 +++++++++++++++++++ board/stx/stxamc8548/u-boot.lds | 143 ++++++++++++++++ include/configs/stxamc8548.h | 332 +++++++++++++++++++++++++++++++++++++ 6 files changed, 729 insertions(+), 0 deletions(-) create mode 100644 board/stx/stxamc8548/Makefile create mode 100644 board/stx/stxamc8548/config.mk create mode 100644 board/stx/stxamc8548/stxamc8548.c create mode 100644 board/stx/stxamc8548/u-boot.lds create mode 100644 include/configs/stxamc8548.h
diff --git a/Makefile b/Makefile index a445eba..909c2ca 100644 --- a/Makefile +++ b/Makefile @@ -2525,6 +2525,9 @@ sbc8560_66_config: unconfig socrates_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates
+stxamc8548_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxamc8548 stx + stxgp3_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx
diff --git a/board/stx/stxamc8548/Makefile b/board/stx/stxamc8548/Makefile new file mode 100644 index 0000000..39387d9 --- /dev/null +++ b/board/stx/stxamc8548/Makefile @@ -0,0 +1,51 @@ +# +# Copyright 2004 Freescale Semiconductor. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/stx/stxamc8548/config.mk b/board/stx/stxamc8548/config.mk new file mode 100644 index 0000000..923828b --- /dev/null +++ b/board/stx/stxamc8548/config.mk @@ -0,0 +1,32 @@ +# +# Copyright 2009 Alex Dubov oakad@yahoo.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# STx amc8548 board +# +ifndef TEXT_BASE +TEXT_BASE = 0xfffc0000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_E500=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 diff --git a/board/stx/stxamc8548/stxamc8548.c b/board/stx/stxamc8548/stxamc8548.c new file mode 100644 index 0000000..02ef97b --- /dev/null +++ b/board/stx/stxamc8548/stxamc8548.c @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2009 Alex Dubov oakad@yahoo.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/io.h> +#include <spd_sdram.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +void local_bus_init(void); +void sdram_init(void); + +char* +get_board_name(void) +{ + return "STx AMC8548"; +} + +unsigned long +get_clock_freq() +{ + return 33000000; +} + +unsigned int +get_board_version(void) +{ + return 0x10; +} + +int checkboard (void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + printf ("Board: %s Version 0x%02x\n", + get_board_name(), get_board_version ()); + + /* + * Initialize local bus. + */ + local_bus_init (); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */ + + out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ + out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ + return 0; +} + +phys_size_t +initdram(int board_type) +{ + long dram_size = 0; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + /* + * Work around to stabilize DDR DLL MSYNC_IN. + * Errata DDR9 seems to have been fixed. + * This is now the workaround for Errata DDR11: + * Override DLL = 1, Course Adj = 1, Tap Select = 0 + */ + + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + out_be32(&gur->ddrdllcr, 0x81000000); + sync(); + isync(); + udelay(200); +#endif + + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} + +/* + * Initialize Local Bus + */ +void +local_bus_init(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); + + uint clkdiv; + uint lbc_hz; + sys_info_t sysinfo; + + get_sys_info(&sysinfo); + clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + out_be32(&gur->lbiuiplldcr1, 0x00078080); + if (clkdiv == 16) { + out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); + } else if (clkdiv == 8) { + out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); + } else if (clkdiv == 4) { + out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); + } + + out_be32(&lbc->lcrr, in_be32(&lbc->lcrr) | 0x00030000); + + sync(); + isync(); + + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ +} + + +void +pci_init_board(void) +{ + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* PCI is disabled */ + out_be32(&gur->devdisr, in_be32(&gur->devdisr) + | MPC85xx_DEVDISR_PCI1 + | MPC85xx_DEVDISR_PCI2 + | MPC85xx_DEVDISR_PCIE); +} + + +#if defined(CONFIG_OF_BOARD_SETUP) + +void +ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} + +#endif diff --git a/board/stx/stxamc8548/u-boot.lds b/board/stx/stxamc8548/u-boot.lds new file mode 100644 index 0000000..57c4e51 --- /dev/null +++ b/board/stx/stxamc8548/u-boot.lds @@ -0,0 +1,143 @@ +/* + * Copyright 2004, 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +PHDRS +{ + text PT_LOAD; + bss PT_LOAD; +} + +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + *(.text) + *(.fixup) + *(.got1) + } :text + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.eh_frame) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } :text + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + .bootpg ADDR(.text) + 0x3f000 : + { + cpu/mpc85xx/start.o (.bootpg) + } :text = 0xffff + + .resetvec ADDR(.text) + 0x3fffc : + { + *(.resetvec) + } :text = 0xffff + + . = ADDR(.text) + 0x40000; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } :bss + + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/stxamc8548.h b/include/configs/stxamc8548.h new file mode 100644 index 0000000..c01a4bb --- /dev/null +++ b/include/configs/stxamc8548.h @@ -0,0 +1,332 @@ +/* + * Copyright 2009 Alex Dubov oakad@yahoo.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * STx amc8548 board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 /* MPC8548 specific */ +#define CONFIG_STXAMC8548 1 /* STXAMC8548 board specific */ + +#define CONFIG_RIO + +#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_INTERRUPTS 1 /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#ifndef __ASSEMBLY__ +extern unsigned long get_clock_freq(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE 1 /* toggle L2 cache */ +#define CONFIG_BTB 1 /* toggle branch predition */ + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ +#define CONFIG_DDR_SPD +#define CONFIG_DDR_DLL /* possible DLL fix needed */ + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1 /* DDR controller or DMA? */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + +/* I2C addresses of SPD EEPROMs */ +#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ + +/* Make sure required options are set */ +#ifndef CONFIG_SPD_EEPROM +#error ("CONFIG_SPD_EEPROM is required") +#endif + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Local Bus Definitions + */ + +/* + * FLASH on the Local Bus + * One banks, 16M, using the CFI driver. + */ + +#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ + +#define CONFIG_SYS_BR0_PRELIM 0xff001801 +#define CONFIG_SYS_BR1_PRELIM 0xf0001001 + +#define CONFIG_SYS_OR0_PRELIM 0xff006e65 +#define CONFIG_SYS_OR1_PRELIM 0xff006e65 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO + + +/* + * Local Bus + */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 +#define CONFIG_SYS_LBC_CACHE_BASE CONFIG_SYS_LBC_OPTION_BASE +#define CONFIG_SYS_LBC_CACHE_SIZE 64 +#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 +#define CONFIG_SYS_LBC_NONCACHE_SIZE 64 + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ + +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 2 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +#ifdef CONFIG_RIO +/* + * RapidIO MMU + */ +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 +#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC3" +#undef CONFIG_MPC85XX_FEC + +#define TSEC1_PHY_ADDR 0x10 +#define TSEC2_PHY_ADDR 0x11 +#define TSEC3_PHY_ADDR 0x12 +#define TSEC4_PHY_ADDR 0x1f + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +#define CONFIG_ETHPRIME "eTSEC0" +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x38000) +#define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_FPGA +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "STxAMC8548=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#endif /* __CONFIG_H */
From: Alex Dubov oakad@yahoo.com
Put environment into .ppcenv section aligned on a smaller "boot" eraseblock boundary near flash end.
Signed-off-by: Alex Dubov oakad@yahoo.com --- board/stx/stxamc8548/u-boot.lds | 11 ++++++++++- include/configs/stxamc8548.h | 3 ++- 2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/board/stx/stxamc8548/u-boot.lds b/board/stx/stxamc8548/u-boot.lds index 57c4e51..6b46c60 100644 --- a/board/stx/stxamc8548/u-boot.lds +++ b/board/stx/stxamc8548/u-boot.lds @@ -109,16 +109,25 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .;
+ .ppcenv ADDR(.text) + 0x38000 : + { + *(.ppcenv) + } + . = ALIGN(256); + __init_begin = .; .text.init : { *(.text.init) } .data.init : { *(.data.init) } + + . = ALIGN(256); __init_end = .;
+ .bootpg ADDR(.text) + 0x3f000 : { - cpu/mpc85xx/start.o (.bootpg) + cpu/mpc85xx/start.o (.bootpg) } :text = 0xffff
.resetvec ADDR(.text) + 0x3fffc : diff --git a/include/configs/stxamc8548.h b/include/configs/stxamc8548.h index c01a4bb..cecd858 100644 --- a/include/configs/stxamc8548.h +++ b/include/configs/stxamc8548.h @@ -246,9 +246,10 @@ extern unsigned long get_clock_freq(void); * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_USE_PPCENV 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x38000) #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dear oakad@yahoo.com,
In message 1249383697-28141-3-git-send-email-oakad@yahoo.com you wrote:
Put environment into .ppcenv section aligned on a smaller "boot" eraseblock boundary near flash end.
Hm... if you change to code to using a smaller boot sector...
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x38000) #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SIZE 0x4000
...should then not be CONFIG_ENV_SECT_SIZE changed to some smaller size, too?
Best regards,
Wolfgang Denk
Put environment into .ppcenv section aligned on a
smaller "boot" eraseblock
boundary near flash end.
Hm... if you change to code to using a smaller boot sector...
#define CONFIG_ENV_ADDR
(CONFIG_SYS_MONITOR_BASE + 0x38000)
#define
CONFIG_ENV_SECT_SIZE 0x4000 /* 16K(one sector) for env */
-#define CONFIG_ENV_SIZE
0x2000
+#define CONFIG_ENV_SIZE
0x4000
...should then not be CONFIG_ENV_SECT_SIZE changed to some smaller size, too?
The "large" eraseblock size for this flash config is 128k (2x64k). Small one is 16k (2x8k).
Dear Alex Dubov,
In message 591477.74934.qm@web37601.mail.mud.yahoo.com you wrote:
Hm... if you change to code to using a smaller boot sector...
#define CONFIG_ENV_ADDR
(CONFIG_SYS_MONITOR_BASE + 0x38000)
#define
CONFIG_ENV_SECT_SIZE 0x4000 /* 16K(one sector) for env */
-#define CONFIG_ENV_SIZE
0x2000
+#define CONFIG_ENV_SIZE
0x4000
...should then not be CONFIG_ENV_SECT_SIZE changed to some smaller size, too?
The "large" eraseblock size for this flash config is 128k (2x64k). Small one is 16k (2x8k).
So the old setting (CONFIG_ENV_SECT_SIZE=0x4000=16K) was plain wrong?
Please merge this fix into your inital patch submission, then.
Best regards,
Wolfgang Denk
Dear oakad@yahoo.com,
In message 1249383697-28141-2-git-send-email-oakad@yahoo.com you wrote:
From: Alex Dubov oakad@yahoo.com
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM slot, ethernet on front panel and backplane, RapidIO on backplane, USB controller on local bus (not currently enabled) and no PCI of any kind.
Signed-off-by: Alex Dubov oakad@yahoo.com
Makefile | 3 + board/stx/stxamc8548/Makefile | 51 ++++++ board/stx/stxamc8548/config.mk | 32 ++++ board/stx/stxamc8548/stxamc8548.c | 168 +++++++++++++++++++ board/stx/stxamc8548/u-boot.lds | 143 ++++++++++++++++ include/configs/stxamc8548.h | 332 +++++++++++++++++++++++++++++++++++++ 6 files changed, 729 insertions(+), 0 deletions(-) create mode 100644 board/stx/stxamc8548/Makefile create mode 100644 board/stx/stxamc8548/config.mk create mode 100644 board/stx/stxamc8548/stxamc8548.c create mode 100644 board/stx/stxamc8548/u-boot.lds create mode 100644 include/configs/stxamc8548.h
What's the difference between this patch and the previously submitted one:
Subject: [U-Boot] [PATCH 2/2] stx: add support for AMC8548 board From: Alex Dubov oakad@yahoo.com Date: Tue, 4 Aug 2009 02:26:49 -0700 (PDT)
?
Best regards,
Wolfgang Denk
On Tue, 2009-08-04 at 14:27 +0200, Wolfgang Denk wrote:
Dear oakad@yahoo.com,
In message 1249383697-28141-2-git-send-email-oakad@yahoo.com you wrote:
From: Alex Dubov oakad@yahoo.com
STx AMC8548 board is an old, AMC form factor, MPC8548 based board intended for RapidIO applications. It features 16MiB NAND flash, one DDR2 soDIMM slot, ethernet on front panel and backplane, RapidIO on backplane, USB controller on local bus (not currently enabled) and no PCI of any kind.
Signed-off-by: Alex Dubov oakad@yahoo.com
Makefile | 3 + board/stx/stxamc8548/Makefile | 51 ++++++ board/stx/stxamc8548/config.mk | 32 ++++ board/stx/stxamc8548/stxamc8548.c | 168 +++++++++++++++++++ board/stx/stxamc8548/u-boot.lds | 143 ++++++++++++++++ include/configs/stxamc8548.h | 332 +++++++++++++++++++++++++++++++++++++ 6 files changed, 729 insertions(+), 0 deletions(-) create mode 100644 board/stx/stxamc8548/Makefile create mode 100644 board/stx/stxamc8548/config.mk create mode 100644 board/stx/stxamc8548/stxamc8548.c create mode 100644 board/stx/stxamc8548/u-boot.lds create mode 100644 include/configs/stxamc8548.h
What's the difference between this patch and the previously submitted one:
Subject: [U-Boot] [PATCH 2/2] stx: add support for AMC8548 board From: Alex Dubov oakad@yahoo.com Date: Tue, 4 Aug 2009 02:26:49 -0700 (PDT)
?
It looks like the MAINTAINERS and MAKEALL entries are still missing for this board too FWIW. Hopefully the other feedback has been taken into consideration in this patch?
It'd be nice when you resubmitted patches to include "v2" in the title, eg "[PATCH v2]" and also listed what you've changed in the comments below your signed-off-by. It makes it easier for others to keep track of what the most recent patch is and what has changed between resubmissions.
Best, Peter
Dear oakad@yahoo.com,
In message 1249383697-28141-1-git-send-email-oakad@yahoo.com you wrote:
From: Alex Dubov oakad@yahoo.com
Move board definition files for STx XTC, GP3 and SSA boards into common subdirectory and factor out common code.
"-mno-spe" flag common to all MPC85xx configurations does not work so change it to "-mspe=no" which does (GCC bug 37759).
Signed-off-by: Alex Dubov oakad@yahoo.com
...
--- a/board/stxgp3/Makefile +++ b/board/stx/common/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
How comes?
--- a/board/stxssa/ddr.c +++ b/board/stx/common/ddr.c @@ -1,5 +1,6 @@ /*
- Copyright 2008 Freescale Semiconductor, Inc.
- Copyright 2009 Alex Dubov oakad@yahoo.com
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
Please do not add a Copyright for such minor changes. Attribution for your work by the Signed-off-by: messages in the git repository should be sufficient here.
...
* Factors to consider for clock adjust:* - number of chips on bus* - position of slot* - DDR1 vs. DDR2?* - ???** This needs to be determined on a board-by-board basis.* 0110 3/4 cycle late* 0111 7/8 cycle late*/- popts->clk_adjust = 6;
If this "needs to be determined on a board-by-board basis" i would expect some CONFIG_SYS_* variable here, which is defined in the respective board config files?
+#if defined(CONFIG_FSL_DDR2)
- popts->cpo_override = 7;
+#else popts->cpo_override = 0; +#endif
Ditto - this should go to the respective board config files.
diff --git a/board/stxssa/law.c b/board/stx/common/law.c similarity index 74% rename from board/stxssa/law.c rename to board/stx/common/law.c index 55dde66..a82c99f 100644 --- a/board/stxssa/law.c +++ b/board/stx/common/law.c @@ -1,9 +1,9 @@ /*
- Copyright 2008 Freescale Semiconductor, Inc.
- (C) Copyright 2000
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- Copyright 2009 Alex Dubov oakad@yahoo.com
- See file CREDITS for list of people who contributed to this
- project.
NAK. Never ever delete any Copyrights. And don't add yoru own just for minor changes.
@@ -31,30 +31,34 @@
- LAW(Local Access Window) configuration:
- 0x0000_0000 0x7fff_ffff DDR 2G
- 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
- 0x8000_0000 0x9fff_ffff PCI1 512M
- 0xa000_0000 0xbfff_ffff PCI2 512M
- 0xc000_0000 0xdfff_ffff RapidIO 512M
- 0xe000_0000 0xe000_ffff CCSR 1M
- 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
- 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
- 0xf000_0000 0xfaff_ffff Local bus 128M
- 0xfb00_0000 0xfb00_ffff Config Latch 64K
- 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M
- 0xf000_0000 0xffff_ffff LBC options + FLASH 256M
Are you sure this is correct?
struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#endif
- SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- /* Map the whole localbus, including flash and reset latch. */
- SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif +#ifdef CONFIG_SYS_RIO_MEM_PHYS
- SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
- SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC)
};
This looks fishy, too.
--- a/board/stxssa/tlb.c +++ b/board/stx/common/tlb.c @@ -1,9 +1,9 @@ /*
- Copyright 2008 Freescale Semiconductor, Inc.
- (C) Copyright 2000
- Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- Copyright 2009 Alex Dubov oakad@yahoo.com
- See file CREDITS for list of people who contributed to this
- project.
NAK. See above.
@@ -31,76 +31,90 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
- SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),
Better split code beautifying into separate patch.
/*
* TLB 0: 64M Non-cacheable, guarded* 0xfc000000 6M4 FLASH
* TLB 0: 256M Non-cacheable, guarded* 0xf0000000 256M LBC (FLASH included)*/
- Out of reset this entry is only 4K.
You mean you change the mapping for soem (or all) boards?
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
CONFIG_SYS_LBC_OPTION_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_64M, 1),
0, 0, BOOKE_PAGESZ_256M, 1),/*
* TLB 1: 256M Non-cacheable, guarded* 0x80000000 256M PCI1 MEM First half
* TLB 1: 64M Non-cacheable, guarded* 0xe000_0000 1M CCSRBAR* 0xe200_0000 1M PCI1 IO* 0xe210_0000 1M PCI2 IO* 0xe300_0000 1M PCIe IO
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_256M, 1),
0, 1, BOOKE_PAGESZ_64M, 1),
Hm... did you actually test these changes on all 4 boards?
diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 9e574a2..a7d948d 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -25,4 +25,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ -Wa,-me500 -msoft-float -mno-string -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) +PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=no)
This is an unrelated change which must be submitted as a separate patch.
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 0424e29..12df277 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -78,6 +78,7 @@ */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ @@ -195,18 +196,20 @@
/* RapdIO Map configuration, mapped 1:1. */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ +#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 +#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_VIRT CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
Please submit code cleanup as separate patch(es).
Best regards,
Wolfgang Denk
Move board definition files for STx XTC, GP3 and SSA
boards into
common subdirectory and factor out common code.
"-mno-spe" flag common to all MPC85xx configurations
does not work
so change it to "-mspe=no" which does (GCC bug
37759).
Signed-off-by: Alex Dubov oakad@yahoo.com
...
--- a/board/stxgp3/Makefile +++ b/board/stx/common/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
How comes?
Git is confused somehow. I don't see this change in my tree.
@@ -31,30 +31,34 @@ * LAW(Local Access Window)
configuration:
* * 0x0000_0000
0x7fff_ffff DDR 2G
- 0x8000_0000
0x9fff_ffff PCI1 MEM 512M
- 0xa000_0000
0xbfff_ffff PCI2 MEM 512M
- 0x8000_0000
0x9fff_ffff PCI1 512M
- 0xa000_0000
0xbfff_ffff PCI2 512M
- 0xc000_0000
0xdfff_ffff RapidIO 512M
* 0xe000_0000
0xe000_ffff CCSR 1M
* 0xe200_0000
0xe2ff_ffff PCI1 IO 16M
* 0xe300_0000
0xe3ff_ffff PCI2 IO 16M
- 0xf000_0000
0xfaff_ffff Local bus 128M
- 0xfb00_0000
0xfb00_ffff Config Latch 64K
- 0xfc00_0000
0xffff_ffff FLASH (boot bank) 64M
- 0xf000_0000
0xffff_ffff LBC options + FLASH 256M
Are you sure this is correct?
Yes, this will cover all three boards affected by the change. They all have their address maps set in similar fashion.
struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE,
LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS,
LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+ SET_LAW(CONFIG_SYS_PCI1_IO_PHYS,
LAW_SIZE_16M, LAW_TRGT_IF_PCI),
#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS,
LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS
SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI1_IO_PHYS,
LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
- /* Map the whole localbus,
including flash and reset latch. */
-
SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+#endif +#ifdef CONFIG_SYS_RIO_MEM_PHYS + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS,
LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif +
SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC)
};
This looks fishy, too.
Just look at the respective boards' law.c files before the patch. They all have this entry, either called CONFIG_SYS_LBC_OPTION_BASE or CONFIG_SYS_LBC_SDRAM_BASE.
@@ -31,76 +31,90 @@ struct fsl_e_tlb_entry tlb_table[]
= {
SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
- SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ SET_TLB_ENTRY(0,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
Better split code beautifying into separate patch.
I wrote this file from scratch. Git is confused here. There's no separate patch. Same for the other issues here and below.
Hm... did you actually test these changes on all 4 boards?
There are no real changes. All three boards have nearly identical configs. stxxtc is only copied around and is not affected by this (no tlbs or law there).
Dear Alex Dubov,
In message 21798.45018.qm@web37604.mail.mud.yahoo.com you wrote:
--- a/board/stxgp3/Makefile +++ b/board/stx/common/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
How comes?
Git is confused somehow. I don't see this change in my tree.
Well, the result looks wrong to me in any case.
...
Are you sure this is correct?
Yes, this will cover all three boards affected by the change. They all have their address maps set in similar fashion.
Um... but that means you are actually changing the configuration for some (or all?) of them?
How much of this were you able to test?
This looks fishy, too.
Just look at the respective boards' law.c files before the patch. They all have this entry, either called CONFIG_SYS_LBC_OPTION_BASE or CONFIG_SYS_LBC_SDRAM_BASE.
I was referring to the whole block of code, not only the last entry.
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
Better split code beautifying into separate patch.
I wrote this file from scratch. Git is confused here.
Hm... git notices high similarity of this file with existing code:
rename board/{stxssa => stx/common}/tlb.c (59%)
There's no separate patch. Same for the other issues here and below.
Maybe should do it as git sees it, then. Don't write new code or change existing one unless necessary.
Hm... did you actually test these changes on all 4 boards?
There are no real changes. All three boards have nearly identical configs.
Hmm.. PCI initialization and memory map looks a bit different now. Or am I missing something?
Best regards,
Wolfgang Denk
Just a general observation: if you are not sure that tlb/law files can be safely factored out and most of the ddr.c files are actually board specific overrides (common part being less than 10 lines) why had you requested me to create a common board hierarchy for these STX boards in the first place?
For all I can see, they don't have any common, vendor specific hardware.
I still want my board supported, so I propose you decide how do you want them arranged (vendor/board/ or just board/) and I'll limit my contribution to my board's files exclusively.
After all, I don't work for Silicon Turnkey and it starts taking too much time.
Dear Alex Dubov,
In message 3287.56311.qm@web37604.mail.mud.yahoo.com you wrote:
Just a general observation: if you are not sure that tlb/law files can be safely factored out and most of the ddr.c files are actually board specific overrides (common part being less than 10 lines) why had you requested me to create a common board hierarchy for these STX boards in the first place?
I am sure that the tlb/law files can be safely factored out, but that does not mean that you can simply use one of the files and force it upon the othe rboards. The differences between the boards must obviously been taken care of, for example by using preprocessor variables (defined in the board config files) to describe the (tiny) differences between the boards.
I don't understand why you claim the ddr.c files were so different:
-> diff board/stxgp3/ddr.c board/stxssa/ddr.c | wc -l 0
As you can see, there is absolutely no difference between the existing ddr.c files - they are absolutely identical.
For all I can see, they don't have any common, vendor specific hardware.
Yet the code looks very much the same, doesn't it?
I still want my board supported, so I propose you decide how do you want them arranged (vendor/board/ or just board/) and I'll limit my contribution to my board's files exclusively.
After all, I don't work for Silicon Turnkey and it starts taking too much time.
I can understand your position, but I am not going to accept yet another copy of the same files. When the first board gets added, it is often next to impossible to know what is common code and what is board specific. When the second board gets added, it's still difficult to decide if it's just coincidence. But when the third board attempts to add the same stuff again, then the situation is clear. It's unfortunate for you that you are triggering the needed cleanup, but that's how it works. Not only for you, but for all of us.
Best regards,
Wolfgang Denk
Just a general observation: if you are not sure that
tlb/law files can be
safely factored out and most of the ddr.c files are
actually board specific
overrides (common part being less than 10 lines) why
had you requested me
to create a common board hierarchy for these STX
boards in the first place?
I am sure that the tlb/law files can be safely factored out, but that does not mean that you can simply use one of the files and force it upon the othe rboards. The differences between the boards must obviously been taken care of, for example by using preprocessor variables (defined in the board config files) to describe the (tiny) differences between the boards.
I don't understand why you claim the ddr.c files were so different:
-> diff board/stxgp3/ddr.c board/stxssa/ddr.c | wc -l 0
How exactly I'm related to this particular issue? My ddr.c is different due to different DDR settings overrides.
Then, there are plenty of nearly identical ddr.c/tlb.c/law.c files in the tree already (~25). Git will derive any such file from any other, because they are essentially the same.
However, the real issue here is whether you prefer a #define sprawl or having a couple of additional short files for each board in question. Until now, as I can see, the second option was preferred.
Dear Alex Dubov,
In message 963516.31353.qm@web37603.mail.mud.yahoo.com you wrote:
However, the real issue here is whether you prefer a #define sprawl or having a couple of additional short files for each board in question. Until now, as I can see, the second option was preferred.
I explained this before. If everything goes right (i. e. if reviewers find enough time for a careful review) we will start asking questions when we see a file being added that is the more or less exact copy of an already existent one. When we have already two semi-identical copies and someone attempts to add a third, we can be sure that there is a trend, and we will ask to factor out the common parts.
Your submission triggered such a cleanup. Your patch was the straw that broke the camel's back.
Best regards,
Wolfgang Denk
On Aug 4, 2009, at 6:01 AM, oakad@yahoo.com wrote:
From: Alex Dubov oakad@yahoo.com
Move board definition files for STx XTC, GP3 and SSA boards into common subdirectory and factor out common code.
"-mno-spe" flag common to all MPC85xx configurations does not work so change it to "-mspe=no" which does (GCC bug 37759).
Signed-off-by: Alex Dubov oakad@yahoo.com
Makefile | 6 +- board/{stxgp3 => stx/common}/Makefile | 20 +++-- board/{stxssa => stx/common}/ddr.c | 46 ++++++++--- board/{stxssa => stx/common}/law.c | 30 ++++--- board/{stxssa => stx/common}/tlb.c | 72 ++++++++++------- board/{ => stx}/stxgp3/Makefile | 3 - board/{ => stx}/stxgp3/config.mk | 0 board/{ => stx}/stxgp3/flash.c | 0 board/{ => stx}/stxgp3/stxgp3.c | 0 board/{ => stx}/stxgp3/u-boot.lds | 0 board/{ => stx}/stxssa/Makefile | 3 - board/{ => stx}/stxssa/config.mk | 0 board/{ => stx}/stxssa/stxssa.c | 0 board/{ => stx}/stxssa/u-boot.lds | 0 board/{ => stx}/stxxtc/Makefile | 0 board/{ => stx}/stxxtc/config.mk | 0 board/{ => stx}/stxxtc/stxxtc.c | 0 board/{ => stx}/stxxtc/u-boot.lds | 0 board/{ => stx}/stxxtc/u-boot.lds.debug | 0 board/stxgp3/ddr.c | 76 ------------------ board/stxgp3/law.c | 58 -------------- board/stxgp3/tlb.c | 130
cpu/mpc85xx/config.mk | 2 +- include/configs/stxgp3.h | 21 +++-- include/configs/stxssa.h | 28 ++++--- 25 files changed, 135 insertions(+), 360 deletions(-) copy board/{stxgp3 => stx/common}/Makefile (82%) rename board/{stxssa => stx/common}/ddr.c (57%) rename board/{stxssa => stx/common}/law.c (74%) rename board/{stxssa => stx/common}/tlb.c (59%) rename board/{ => stx}/stxgp3/Makefile (95%) rename board/{ => stx}/stxgp3/config.mk (100%) rename board/{ => stx}/stxgp3/flash.c (100%) rename board/{ => stx}/stxgp3/stxgp3.c (100%) rename board/{ => stx}/stxgp3/u-boot.lds (100%) rename board/{ => stx}/stxssa/Makefile (95%) rename board/{ => stx}/stxssa/config.mk (100%) rename board/{ => stx}/stxssa/stxssa.c (100%) rename board/{ => stx}/stxssa/u-boot.lds (100%) rename board/{ => stx}/stxxtc/Makefile (100%) rename board/{ => stx}/stxxtc/config.mk (100%) rename board/{ => stx}/stxxtc/stxxtc.c (100%) rename board/{ => stx}/stxxtc/u-boot.lds (100%) rename board/{ => stx}/stxxtc/u-boot.lds.debug (100%) delete mode 100644 board/stxgp3/ddr.c delete mode 100644 board/stxgp3/law.c delete mode 100644 board/stxgp3/tlb.c
Can you limit the patch that creates board/stx/ to doing just that and NOTHING else. Leave the other clean up and refactoring for other patches.
- k
participants (5)
-
Alex Dubov -
Kumar Gala -
oakad＠yahoo.com
-
Peter Tyser -
Wolfgang Denk