You can't actually have both, and with some coming changes to change the memory map for the board and support 36-bit physical, we need the extra BAT that is being consumed by having both.

I also make non-PCI configs build cleanly, for the sake of sanity.

Signed-off-by: Becky Bruce becky.bruce@freescale.com --- board/freescale/mpc8641hpcn/law.c | 7 ++++- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 11 ++++---- include/configs/MPC8641HPCN.h | 37 ++++++++++++++++++++++------- 3 files changed, 38 insertions(+), 17 deletions(-)

diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c index 8e13728..1ad186c 100644 --- a/board/freescale/mpc8641hpcn/law.c +++ b/board/freescale/mpc8641hpcn/law.c @@ -49,13 +49,16 @@ struct law_entry law_table[] = { #if !defined(CONFIG_SPD_EEPROM) SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), #endif +#ifdef CONFIG_PCI SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), +#elif defined(CONFIG_RIO) + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), +#endif + SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO) };

int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index c7e10d8..d6a0a56 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -135,17 +135,16 @@ extern void fsl_pci_init(struct pci_controller *hose);

void pci_init_board(void) { - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) - >> MPC8641_PORDEVSR_IO_SEL_SHIFT; - #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) + >> MPC8641_PORDEVSR_IO_SEL_SHIFT;

#ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0bf5888..c33047f 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -45,11 +45,18 @@

#define CONFIG_SYS_RESET_ADDRESS 0xfff00100

+/* + * set this to enable Rapid IO. PCI and RIO are mutually exclusive + */ +/*#define CONFIG_RIO 1*/ + +#ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ #define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */

#define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -422,26 +429,38 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U

/* - * BAT1 1G Cache-inhibited, guarded + * BAT1 unused + */ +#define CONFIG_SYS_DBAT1L 0 +#define CONFIG_SYS_DBAT1U 0 +#define CONFIG_SYS_IBAT1L 0 +#define CONFIG_SYS_IBAT1U 0 + +/* if CONFIG_PCI: + * BAT2 1G Cache-inhibited, guarded * 0x8000_0000 512M PCI-Express 1 Memory * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 - */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U - -/* + * + * if CONFIG_RIO * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ +#ifdef CONFIG_PCI +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ + | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G \ + | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ + | BATL_CACHEINHIBIT) +#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U +#else /* CONFIG_RIO */ #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U +#endif

/* * BAT3 4M Cache-inhibited, guarded