T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities

So, update the defines accordingly.

Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com --- Changes for v2: - Remove LIODIN changes. It will be send later

arch/powerpc/include/asm/config_mpc85xx.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 15e44de..b744049 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -20,6 +20,7 @@ #define CONFIG_PPC_SPINTABLE_COMPATIBLE

#define FSL_DDR_VER_4_7 47 +#define FSL_DDR_VER_5_0 50

/* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) @@ -626,22 +627,24 @@ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) #define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) +#define CONFIG_MAX_CPUS 2 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 16 -#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY