imx: imx8mq: mxc_get_clock for MXC_I2C_CLK is missing
Hi Peng,
I faced an issue with the I2C bus speed in SPL for the imx8mq. I figured out that the bus frequency is set to about 1MHz. While digging into that I found that the clk ID for the I2C is not returned for the imx8mq correctly.
Can you confirm that this is missing here.
This is what I added and now it looks better.
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 60e2218a3c..9e45ffd66b 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -363,6 +363,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_root_clk(USDHC1_CLK_ROOT); case MXC_ESDHC2_CLK: return get_root_clk(USDHC2_CLK_ROOT); + case MXC_I2C_CLK: + return get_root_clk(I2C1_CLK_ROOT); + case MXC_UART_CLK: + return get_root_clk(UART1_CLK_ROOT); + case MXC_QSPI_CLK: + return get_root_clk(QSPI_CLK_ROOT); default: return get_root_clk(clk); }
Hi,
Am Mi., 8. Sept. 2021 um 15:08 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi Peng,
I faced an issue with the I2C bus speed in SPL for the imx8mq. I figured out that the bus frequency is set to about 1MHz. While digging into that I found that the clk ID for the I2C is not returned for the imx8mq correctly.
Can you confirm that this is missing here.
This is what I added and now it looks better.
Just measured the frequency and it is still not ok. It changed from 1MHz to 400kHZ. But expected is 100KHz.
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 60e2218a3c..9e45ffd66b 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -363,6 +363,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_root_clk(USDHC1_CLK_ROOT); case MXC_ESDHC2_CLK: return get_root_clk(USDHC2_CLK_ROOT);
case MXC_I2C_CLK:return get_root_clk(I2C1_CLK_ROOT);case MXC_UART_CLK:return get_root_clk(UART1_CLK_ROOT);case MXC_QSPI_CLK:return get_root_clk(QSPI_CLK_ROOT); default: return get_root_clk(clk); }
-- Heiko
Hi,
Am Mi., 8. Sept. 2021 um 16:07 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi,
Am Mi., 8. Sept. 2021 um 15:08 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi Peng,
I faced an issue with the I2C bus speed in SPL for the imx8mq. I figured out that the bus frequency is set to about 1MHz. While digging into that I found that the clk ID for the I2C is not returned for the imx8mq correctly.
Can you confirm that this is missing here.
This is what I added and now it looks better.
Just measured the frequency and it is still not ok. It changed from 1MHz to 400kHZ. But expected is 100KHz.
Hi. I think now I understand that the SPL configures the I2C to 100kHz and after that U-Boot will configure the 400kHz frequency due to the dts configuration. I will measure the SPL vs U-Boot frequencies tomorrow. I will confirm that after that.
Hi,
Am Mi., 8. Sept. 2021 um 17:45 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi,
Am Mi., 8. Sept. 2021 um 16:07 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi,
Am Mi., 8. Sept. 2021 um 15:08 Uhr schrieb Heiko Thiery heiko.thiery@gmail.com:
Hi Peng,
I faced an issue with the I2C bus speed in SPL for the imx8mq. I figured out that the bus frequency is set to about 1MHz. While digging into that I found that the clk ID for the I2C is not returned for the imx8mq correctly.
Can you confirm that this is missing here.
This is what I added and now it looks better.
Just measured the frequency and it is still not ok. It changed from 1MHz to 400kHZ. But expected is 100KHz.
Hi. I think now I understand that the SPL configures the I2C to 100kHz and after that U-Boot will configure the 400kHz frequency due to the dts configuration. I will measure the SPL vs U-Boot frequencies tomorrow. I will confirm that after that.
As said before. With the proposed adding the right root clock for I2C the configuration can properly be done. The frequency of I2C1 is 100kHz in SPL [fix_spl_startup.PNG] and will be reconfigured according the DTS settings during u-boot init. In my case 400kHz [fix_spl_i2c_probe.PNG]. In the attached screenshots you can see that without the fix the value is about 1MHz [wrong_spl_startup.PNG].
-- Heiko
On 2021/9/8 21:08, Heiko Thiery wrote:
Hi Peng,
I faced an issue with the I2C bus speed in SPL for the imx8mq. I figured out that the bus frequency is set to about 1MHz. While digging into that I found that the clk ID for the I2C is not returned for the imx8mq correctly.
Can you confirm that this is missing here.
You are right! Thanks for spotting this.
Regards, Peng.
This is what I added and now it looks better.
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 60e2218a3c..9e45ffd66b 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -363,6 +363,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_root_clk(USDHC1_CLK_ROOT); case MXC_ESDHC2_CLK: return get_root_clk(USDHC2_CLK_ROOT);
case MXC_I2C_CLK:return get_root_clk(I2C1_CLK_ROOT);case MXC_UART_CLK:return get_root_clk(UART1_CLK_ROOT);case MXC_QSPI_CLK:return get_root_clk(QSPI_CLK_ROOT); default: return get_root_clk(clk); }
participants (2)
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Heiko Thiery -
Peng Fan (OSS)