[U-Boot] [PATCH 1/6] fsl: Clean up printing of PCI boot info
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like:
... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ...
Signed-off-by: Peter Tyser ptyser@xes-inc.com CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org --- This series assumes "fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware" has already been applied.
board/atum8548/atum8548.c | 12 ++++++------ board/freescale/corenet_ds/pci.c | 16 ++++++++-------- board/freescale/mpc8536ds/mpc8536ds.c | 16 ++++++++-------- board/freescale/mpc8540ads/mpc8540ads.c | 4 ++-- board/freescale/mpc8541cds/mpc8541cds.c | 6 +++--- board/freescale/mpc8544ds/mpc8544ds.c | 24 ++++++++++++------------ board/freescale/mpc8548cds/mpc8548cds.c | 16 ++++++++-------- board/freescale/mpc8555cds/mpc8555cds.c | 6 +++--- board/freescale/mpc8560ads/mpc8560ads.c | 4 ++-- board/freescale/mpc8568mds/mpc8568mds.c | 8 ++++---- board/freescale/mpc8569mds/mpc8569mds.c | 8 ++++---- board/freescale/mpc8572ds/mpc8572ds.c | 20 ++++++++++---------- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 20 ++++++++++---------- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 18 +++++++++--------- board/freescale/p1022ds/p1022ds.c | 8 ++++---- board/freescale/p1_p2_rdb/pci.c | 16 ++++++++-------- board/freescale/p2020ds/p2020ds.c | 24 ++++++++++++------------ board/pm854/pm854.c | 4 ++-- board/pm856/pm856.c | 4 ++-- board/sbc8548/sbc8548.c | 8 ++++---- board/sbc8641d/sbc8641d.c | 18 +++++++++--------- board/tqc/tqm85xx/tqm85xx.c | 8 ++++---- board/xes/common/fsl_8xxx_pci.c | 16 ++++++++-------- drivers/pci/fsl_pci_init.c | 10 +++++----- 24 files changed, 147 insertions(+), 147 deletions(-)
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 671f9e9..4fcbb18 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -218,14 +218,14 @@ void pci_init_board(void)
pcie1_hose.region_count = 1; #endif - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + printf ("PCIE1: connected to Slot as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); @@ -242,7 +242,7 @@ void pci_init_board(void) if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", @@ -254,7 +254,7 @@ void pci_init_board(void) first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI1: disabled\n"); }
puts("\n"); @@ -267,11 +267,11 @@ void pci_init_board(void) SET_STD_PCI_INFO(pci_info[num], 2); pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
- puts (" PCI2\n"); + puts("PCI2\n"); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI2: disabled\n"); + printf("PCI2: disabled\n"); } puts("\n"); #else diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index e1bca19..775b623 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -68,13 +68,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected to Slot 1 as %s (base addr %lx)\n", + printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */ @@ -90,13 +90,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf(" PCIE2 connected to Slot 3 as %s (base addr %lx)\n", + printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf (" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */ @@ -112,13 +112,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf(" PCIE3 connected to Slot 2 as %s (base addr %lx)\n", + printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); } else { - printf (" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ @@ -134,13 +134,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_4); SET_STD_PCIE_INFO(pci_info[num], 4); pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); - printf(" PCIE4 connected to as %s (base addr %lx)\n", + printf("PCIE4: connected to as %s (base addr %lx)\n", pcie_ep ? "End Point" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie4_hose, first_free_busno); } else { - printf (" PCIE4: disabled\n"); + printf("PCIE4: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index c8e0856..8ad7549 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -229,13 +229,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n", + printf("PCIE3: connected to Slot3 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); } else { - printf (" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); }
puts("\n"); @@ -253,13 +253,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n", + printf("PCIE1: connected to Slot1 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); @@ -277,13 +277,13 @@ void pci_init_board(void) LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n", + printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf (" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); }
puts("\n"); @@ -304,7 +304,7 @@ void pci_init_board(void) LAW_TRGT_IF_PCI); SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", @@ -316,7 +316,7 @@ void pci_init_board(void) first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index f9ff827..d354a26 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -47,10 +47,10 @@ int checkboard (void) puts("Board: ADS\n");
#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", + printf("PCI1: 32 bit, %d MHz (compiled)\n", CONFIG_SYS_CLK_FREQ / 1000000); #else - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); #endif
/* diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 0580fe7..59ec604 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -221,17 +221,17 @@ int checkboard (void) MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- printf (" PCI1: %d bit, %s MHz, %s\n", + printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, (pci1_speed == 33000000) ? "33" : (pci1_speed == 66000000) ? "66" : "unknown", pci1_clk_sel ? "sync" : "async");
if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", + printf("PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { - printf (" PCI2: disabled\n"); + printf("PCI2: disabled\n"); }
/* diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index da3a2b6..3bbf0c2 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -142,9 +142,9 @@ void pci_init_board(void)
pcie3_hose.region_count = 1; #endif - printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE3: connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno);
@@ -154,7 +154,7 @@ void pci_init_board(void) */ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); } else { - printf (" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } puts("\n"); #else @@ -177,14 +177,14 @@ void pci_init_board(void)
pcie1_hose.region_count = 1; #endif - printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); @@ -208,13 +208,13 @@ void pci_init_board(void)
pcie2_hose.region_count = 1; #endif - printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf (" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); }
puts("\n"); @@ -231,7 +231,7 @@ void pci_init_board(void) if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", @@ -243,7 +243,7 @@ void pci_init_board(void) first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 23e552b..14c902c 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -284,7 +284,7 @@ void pci_init_board(void) if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", @@ -308,7 +308,7 @@ void pci_init_board(void) } #endif } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); }
puts("\n"); @@ -321,10 +321,10 @@ void pci_init_board(void) uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", + printf("PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { - printf (" PCI2: disabled\n"); + printf("PCI2: disabled\n"); } } #else @@ -337,14 +337,14 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index b7e0e0c..edaba26 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -219,17 +219,17 @@ int checkboard (void) MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
- printf (" PCI1: %d bit, %s MHz, %s\n", + printf("PCI1: %d bit, %s MHz, %s\n", (pci1_32) ? 32 : 64, (pci1_speed == 33000000) ? "33" : (pci1_speed == 66000000) ? "66" : "unknown", pci1_clk_sel ? "sync" : "async");
if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", + printf("PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { - printf (" PCI2: disabled\n"); + printf("PCI2: disabled\n"); }
/* diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 423e9d7..1761431 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -252,10 +252,10 @@ int checkboard (void) puts("Board: ADS\n");
#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", + printf("PCI1: 32 bit, %d MHz (compiled)\n", CONFIG_SYS_CLK_FREQ / 1000000); #else - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); #endif
/* diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index bd859e4..d74fcac 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -378,7 +378,7 @@ void pci_init_board(void) if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", @@ -390,7 +390,7 @@ void pci_init_board(void) first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); }
puts("\n"); @@ -404,14 +404,14 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", + printf("PCIE1: connected to Slot as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 743e712..dc0884e 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -584,13 +584,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 6b96dfc..2125274 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -192,9 +192,9 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf (" PCIE3 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE3: connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); /* @@ -211,7 +211,7 @@ void pci_init_board(void) in_be32(p); } } else { - printf (" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } puts("\n"); #else @@ -224,13 +224,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf (" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); }
puts("\n"); @@ -244,13 +244,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index f67f3e3..61a635d 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -244,14 +244,14 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf (" PCIE1 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); }
puts("\n"); @@ -265,13 +265,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){ SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf (" PCIE2 connected to Slot as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected to Slot as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf (" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); }
puts("\n"); @@ -283,14 +283,14 @@ void pci_init_board(void) if (!(devdisr & MPC86xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf(" PCI connected to PCI slots as %s" \ + printf("PCI: connected to PCI slots as %s" \ " (base address %lx)\n", pci_agent ? "Agent" : "Host", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); }
puts("\n"); diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index 092ead6..812111d 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -157,9 +157,9 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno);
@@ -171,22 +171,22 @@ void pci_init_board(void) + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
} else { - puts(" PCIE1: disabled\n"); + puts("PCIE1: disabled\n"); } #else - puts(" PCIE1: disabled\n"); + puts("PCIE1: disabled\n"); #endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf(" PCIE2 connected as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); #else - puts(" PCIE2: disabled\n"); + puts("PCIE2: disabled\n"); #endif /* CONFIG_PCIE2 */
} diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index ee93e8b..7cb549b 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -225,7 +225,7 @@ static void configure_pcie(struct fsl_pci_info *info, set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law); set_next_law(info->io_phys, law_size_bits(info->io_size), info->law); is_endpoint = fsl_setup_hose(hose, info->regs); - printf(" PCIE%u connected to %s as %s (base addr %lx)\n", + printf("PCIE%u: connected to %s as %s (base addr %lx)\n", info->pci_num, connected, is_endpoint ? "Endpoint" : "Root Complex", info->regs); bus_number = fsl_pci_init_port(info, hose, bus_number); @@ -255,7 +255,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info, 1); configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1)); } else { - printf(" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ @@ -266,7 +266,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info, 2); configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2)); } else { - printf(" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ @@ -277,7 +277,7 @@ void pci_init_board(void) SET_STD_PCIE_INFO(pci_info, 3); configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3)); } else { - printf(" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 97d4f83..e2ed29c 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -65,13 +65,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf (" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); } puts("\n"); #else @@ -84,13 +84,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); } puts("\n"); #else diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 608ff91..f988272 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -218,9 +218,9 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf(" PCIE2 connected to ULI as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno);
@@ -245,7 +245,7 @@ void pci_init_board(void) } #endif } else { - printf(" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); } puts("\n"); #else @@ -258,13 +258,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); } else { - printf(" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } puts("\n"); #else @@ -277,13 +277,13 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf(" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); } puts("\n"); #else diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index a302b91..0b8ea81 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -59,10 +59,10 @@ int checkboard (void) puts("Board: MicroSys PM854\n");
#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", + printf("PCI1: 32 bit, %d MHz (compiled)\n", CONFIG_SYS_CLK_FREQ / 1000000); #else - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); #endif
/* diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index f9d92d9..4e059b0 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -213,10 +213,10 @@ int checkboard (void) puts("Board: MicroSys PM856\n");
#ifdef CONFIG_PCI - printf(" PCI1: 32 bit, %d MHz (compiled)\n", + printf("PCI1: 32 bit, %d MHz (compiled)\n", CONFIG_SYS_CLK_FREQ / 1000000); #else - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); #endif
/* diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 733979c..272428f 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -342,7 +342,7 @@ pci_init_board(void) uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
- printf (" PCI host: %d bit, %s MHz, %s, %s\n", + printf("PCI: Host, %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33000000) ? "33" : (pci_speed == 66000000) ? "66" : "unknown", @@ -353,7 +353,7 @@ pci_init_board(void) first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf (" PCI: disabled\n"); + printf("PCI: disabled\n"); }
puts("\n"); @@ -368,11 +368,11 @@ pci_init_board(void)
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); - printf (" PCIE at base address %lx\n", pci_info[num].regs); + printf("PCIE: base address %lx\n", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf (" PCIE: disabled\n"); + printf("PCIE: disabled\n"); }
puts("\n"); diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c index d954d2f..5bf2364 100644 --- a/board/sbc8641d/sbc8641d.c +++ b/board/sbc8641d/sbc8641d.c @@ -221,29 +221,29 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE1: connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - puts(" PCIE1: disabled\n"); + puts("PCIE1: disabled\n"); } #else - puts(" PCIE1: disabled\n"); + puts("PCIE1: disabled\n"); #endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf(" PCIE2 connected as %s (base addr %lx)\n", - pcie_ep ? "Endpoint" : "Root Complex", - pci_info[num].regs); + printf("PCIE2: connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); #else - puts(" PCIE2: disabled\n"); + puts("PCIE2: disabled\n"); #endif /* CONFIG_PCIE2 */ }
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 2c3885f..362b335 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -567,7 +567,7 @@ void pci_init_board (void) if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n", + printf("PCI1: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333333) ? "33" : (pci_speed == 66666666) ? "66" : "unknown", @@ -591,7 +591,7 @@ void pci_init_board (void) } #endif } else { - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); @@ -603,12 +603,12 @@ void pci_init_board (void) if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected as %s\n", + printf("PCIE1: connected as %s\n", pcie_ep ? "Endpoint" : "Root Complex"); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf(" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index f425cee..4a0965b 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -95,7 +95,7 @@ void pci_init_board(void) if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { SET_STD_PCI_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs); - printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n", + printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n", pci_32 ? 32 : 64, pcix ? "PCIX" : "PCI", pci_spd_norm ? ">=" : "<=", @@ -106,7 +106,7 @@ void pci_init_board(void) first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { - printf(" PCI1: disabled\n"); + printf("PCI1: disabled\n"); } #elif defined CONFIG_MPC8548 /* PCI1 not present on MPC8572 */ @@ -119,12 +119,12 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) { SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf(" PCIE1 connected as %s\n", + printf("PCIE1: connected as %s\n", pcie_ep ? "Endpoint" : "Root Complex"); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { - printf(" PCIE1: disabled\n"); + printf("PCIE1: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1); @@ -136,12 +136,12 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) { SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf(" PCIE2 connected as %s\n", + printf("PCIE2: connected as %s\n", pcie_ep ? "Endpoint" : "Root Complex"); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { - printf(" PCIE2: disabled\n"); + printf("PCIE2: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2); @@ -153,12 +153,12 @@ void pci_init_board(void) if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) { SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf(" PCIE3 connected as %s\n", + printf("PCIE3: connected as %s\n", pcie_ep ? "Endpoint" : "Root Complex"); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); } else { - printf(" PCIE3: disabled\n"); + printf("PCIE3: disabled\n"); } #else setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3); diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 45794da..21cbb3b 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -391,11 +391,11 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) * 1 == pci agent or pcie end-point */ if (!temp8) { - printf(" Scanning PCI bus %02x\n", + printf(" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); } else { - debug(" Not scanning PCI bus %02x. PI=%x\n", + debug(" Not scanning PCI bus %02x. PI=%x\n", hose->current_busno, temp8); hose->last_busno = hose->current_busno; } @@ -482,9 +482,9 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info, }
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); - printf(" PCI%s%x on bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? - "E" : "", pci_info->pci_num, - hose->first_busno, hose->last_busno); + printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ? + "E" : "", pci_info->pci_num, + hose->first_busno, hose->last_busno);
return(hose->last_busno + 1); }
Previously some mpc85xx boards printed indented messages such as the following on bootup: printf(" eTSEC4 is in sgmii mode.\n"); printf(" Serdes2 disalbed\n");
The bootup appearance looks cleaner if the indentation is removed which aligns these messages with other bootup output.
Signed-off-by: Peter Tyser ptyser@xes-inc.com CC: galak@kernel.crashing.org --- board/atum8548/atum8548.c | 8 ++++---- board/freescale/mpc8536ds/mpc8536ds.c | 8 ++++---- board/freescale/mpc8544ds/mpc8544ds.c | 4 ++-- board/freescale/mpc8572ds/mpc8572ds.c | 8 ++++---- board/freescale/p1_p2_rdb/pci.c | 2 +- board/freescale/p2020ds/p2020ds.c | 4 ++-- 6 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 4fcbb18..96581aa 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -193,13 +193,13 @@ void pci_init_board(void)
if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf (" eTSEC1 is in sgmii mode.\n"); + printf("eTSEC1 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf (" eTSEC2 is in sgmii mode.\n"); + printf("eTSEC2 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf (" eTSEC3 is in sgmii mode.\n"); + printf("eTSEC3 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) - printf (" eTSEC4 is in sgmii mode.\n"); + printf("eTSEC4 is in sgmii mode.\n"); }
#ifdef CONFIG_PCIE1 diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 8ad7549..cf92ba1 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -211,12 +211,12 @@ void pci_init_board(void) devdisr, sdrs2_io_sel, io_sel);
if (sdrs2_io_sel == 7) - printf(" Serdes2 disalbed\n"); + printf("Serdes2 disalbed\n"); else if (sdrs2_io_sel == 4) { - printf(" eTSEC1 is in sgmii mode.\n"); - printf(" eTSEC3 is in sgmii mode.\n"); + printf("eTSEC1 is in sgmii mode.\n"); + printf("eTSEC3 is in sgmii mode.\n"); } else if (sdrs2_io_sel == 6) - printf(" eTSEC1 is in sgmii mode.\n"); + printf("eTSEC1 is in sgmii mode.\n");
puts("\n"); #ifdef CONFIG_PCIE3 diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 3bbf0c2..fae1341 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -120,9 +120,9 @@ void pci_init_board(void)
if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf (" eTSEC1 is in sgmii mode.\n"); + printf("eTSEC1 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf (" eTSEC3 is in sgmii mode.\n"); + printf("eTSEC3 is in sgmii mode.\n"); } puts("\n");
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 2125274..b712e24 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -177,13 +177,13 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) - printf (" eTSEC1 is in sgmii mode.\n"); + printf("eTSEC1 is in sgmii mode.\n"); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf (" eTSEC2 is in sgmii mode.\n"); + printf("eTSEC2 is in sgmii mode.\n"); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf (" eTSEC3 is in sgmii mode.\n"); + printf("eTSEC3 is in sgmii mode.\n"); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) - printf (" eTSEC4 is in sgmii mode.\n"); + printf("eTSEC4 is in sgmii mode.\n");
puts("\n"); #ifdef CONFIG_PCIE3 diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index e2ed29c..5fd414e 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -56,7 +56,7 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf (" eTSEC2 is in sgmii mode.\n"); + printf("eTSEC2 is in sgmii mode.\n");
puts("\n"); #ifdef CONFIG_PCIE2 diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index f988272..b507677 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -207,9 +207,9 @@ void pci_init_board(void) debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) - printf(" eTSEC2 is in sgmii mode.\n"); + printf("eTSEC2 is in sgmii mode.\n"); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) - printf(" eTSEC3 is in sgmii mode.\n"); + printf("eTSEC3 is in sgmii mode.\n");
puts("\n"); #ifdef CONFIG_PCIE2
Dear Peter Tyser,
In message 1288393169-9814-2-git-send-email-ptyser@xes-inc.com you wrote:
Previously some mpc85xx boards printed indented messages such as the following on bootup: printf(" eTSEC4 is in sgmii mode.\n"); printf(" Serdes2 disalbed\n");
The bootup appearance looks cleaner if the indentation is removed which aligns these messages with other bootup output.
Signed-off-by: Peter Tyser ptyser@xes-inc.com CC: galak@kernel.crashing.org
board/atum8548/atum8548.c | 8 ++++---- board/freescale/mpc8536ds/mpc8536ds.c | 8 ++++---- board/freescale/mpc8544ds/mpc8544ds.c | 4 ++-- board/freescale/mpc8572ds/mpc8572ds.c | 8 ++++---- board/freescale/p1_p2_rdb/pci.c | 2 +- board/freescale/p2020ds/p2020ds.c | 4 ++-- 6 files changed, 17 insertions(+), 17 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
The "Scanning PCI bus X" message doesn't provide any real useful information, so remove it.
Original output: PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d
Updated output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser ptyser@xes-inc.com CC: galak@kernel.crashing.org --- drivers/pci/fsl_pci_init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 21cbb3b..5b34dcb 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -391,7 +391,7 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) * 1 == pci agent or pcie end-point */ if (!temp8) { - printf(" Scanning PCI bus %02x\n", + debug(" Scanning PCI bus %02x\n", hose->current_busno); hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno); } else {
Dear Peter Tyser,
In message 1288393169-9814-3-git-send-email-ptyser@xes-inc.com you wrote:
The "Scanning PCI bus X" message doesn't provide any real useful information, so remove it.
Original output: PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d
Updated output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser ptyser@xes-inc.com CC: galak@kernel.crashing.org
drivers/pci/fsl_pci_init.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
This change does the following: - Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation.
- Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ...
- Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus.
- Changes the general formatting of the PCI device output.
Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d
Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- common/cmd_pci.c | 66 +----------------------------- drivers/pci/pci.c | 117 ++++++++++++++++++++++++++++++++++++++++------------- include/pci.h | 1 + 3 files changed, 92 insertions(+), 92 deletions(-)
diff --git a/common/cmd_pci.c b/common/cmd_pci.c index ccf5ada..92631ea 100644 --- a/common/cmd_pci.c +++ b/common/cmd_pci.c @@ -104,68 +104,6 @@ void pciinfo(int BusNum, int ShortPCIListing) } }
-static char *pci_classes_str(u8 class) -{ - switch (class) { - case PCI_CLASS_NOT_DEFINED: - return "Build before PCI Rev2.0"; - break; - case PCI_BASE_CLASS_STORAGE: - return "Mass storage controller"; - break; - case PCI_BASE_CLASS_NETWORK: - return "Network controller"; - break; - case PCI_BASE_CLASS_DISPLAY: - return "Display controller"; - break; - case PCI_BASE_CLASS_MULTIMEDIA: - return "Multimedia device"; - break; - case PCI_BASE_CLASS_MEMORY: - return "Memory controller"; - break; - case PCI_BASE_CLASS_BRIDGE: - return "Bridge device"; - break; - case PCI_BASE_CLASS_COMMUNICATION: - return "Simple comm. controller"; - break; - case PCI_BASE_CLASS_SYSTEM: - return "Base system peripheral"; - break; - case PCI_BASE_CLASS_INPUT: - return "Input device"; - break; - case PCI_BASE_CLASS_DOCKING: - return "Docking station"; - break; - case PCI_BASE_CLASS_PROCESSOR: - return "Processor"; - break; - case PCI_BASE_CLASS_SERIAL: - return "Serial bus controller"; - break; - case PCI_BASE_CLASS_INTELLIGENT: - return "Intelligent controller"; - break; - case PCI_BASE_CLASS_SATELLITE: - return "Satellite controller"; - break; - case PCI_BASE_CLASS_CRYPT: - return "Cryptographic device"; - break; - case PCI_BASE_CLASS_SIGNAL_PROCESSING: - return "DSP"; - break; - case PCI_CLASS_OTHERS: - return "Does not fit any class"; - break; - default: - return "???"; - break; - }; -}
/* * Subroutine: pci_header_show_brief @@ -190,7 +128,7 @@ void pci_header_show_brief(pci_dev_t dev)
printf("0x%.4x 0x%.4x %-23s 0x%.2x\n", vendor, device, - pci_classes_str(class), subclass); + pci_class_str(class), subclass); }
/* @@ -225,7 +163,7 @@ void pci_header_show(pci_dev_t dev) PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, - pci_classes_str); + pci_class_str); PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 848746f..3dccf88 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -510,6 +510,71 @@ void pci_cfgfunc_do_nothing(struct pci_controller *hose, extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); extern void pciauto_config_init(struct pci_controller *hose);
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW) +const char * pci_class_str(u8 class) +{ + switch (class) { + case PCI_CLASS_NOT_DEFINED: + return "Build before PCI Rev2.0"; + break; + case PCI_BASE_CLASS_STORAGE: + return "Mass storage controller"; + break; + case PCI_BASE_CLASS_NETWORK: + return "Network controller"; + break; + case PCI_BASE_CLASS_DISPLAY: + return "Display controller"; + break; + case PCI_BASE_CLASS_MULTIMEDIA: + return "Multimedia device"; + break; + case PCI_BASE_CLASS_MEMORY: + return "Memory controller"; + break; + case PCI_BASE_CLASS_BRIDGE: + return "Bridge device"; + break; + case PCI_BASE_CLASS_COMMUNICATION: + return "Simple comm. controller"; + break; + case PCI_BASE_CLASS_SYSTEM: + return "Base system peripheral"; + break; + case PCI_BASE_CLASS_INPUT: + return "Input device"; + break; + case PCI_BASE_CLASS_DOCKING: + return "Docking station"; + break; + case PCI_BASE_CLASS_PROCESSOR: + return "Processor"; + break; + case PCI_BASE_CLASS_SERIAL: + return "Serial bus controller"; + break; + case PCI_BASE_CLASS_INTELLIGENT: + return "Intelligent controller"; + break; + case PCI_BASE_CLASS_SATELLITE: + return "Satellite controller"; + break; + case PCI_BASE_CLASS_CRYPT: + return "Cryptographic device"; + break; + case PCI_BASE_CLASS_SIGNAL_PROCESSING: + return "DSP"; + break; + case PCI_CLASS_OTHERS: + return "Does not fit any class"; + break; + default: + return "???"; + break; + }; +} +#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */ + int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) { /* @@ -568,44 +633,40 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus)
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
- if (vendor != 0xffff && vendor != 0x0000) { + if (vendor == 0xffff || vendor == 0x0000) + continue;
- if (!PCI_FUNC(dev)) - found_multi = header_type & 0x80; + if (!PCI_FUNC(dev)) + found_multi = header_type & 0x80;
- debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n", - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) ); + debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
- pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); - pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
- cfg = pci_find_config(hose, class, vendor, device, - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); - if (cfg) { - cfg->config_device(hose, dev, cfg); - sub_bus = max(sub_bus, hose->current_busno); + cfg = pci_find_config(hose, class, vendor, device, + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); + if (cfg) { + cfg->config_device(hose, dev, cfg); + sub_bus = max(sub_bus, hose->current_busno); #ifdef CONFIG_PCI_PNP - } else { - int n = pciauto_config_device(hose, dev); + } else { + int n = pciauto_config_device(hose, dev);
- sub_bus = max(sub_bus, n); + sub_bus = max(sub_bus, n); #endif - } - if (hose->fixup_irq) - hose->fixup_irq(hose, dev); + } + if (hose->fixup_irq) + hose->fixup_irq(hose, dev);
#ifdef CONFIG_PCI_SCAN_SHOW - if (pci_print_dev(hose, dev)) { - unsigned char int_line; - - pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE, - &int_line); - printf(" %02x %02x %04x %04x %04x %02x\n", - PCI_BUS(dev), PCI_DEV(dev), vendor, device, class, - int_line); - } -#endif + if (pci_print_dev(hose, dev)) { + printf(" %02x:%02x.%x - %04x:%04x - %s\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), + vendor, device, pci_class_str(class >> 8)); } +#endif }
return sub_bus; diff --git a/include/pci.h b/include/pci.h index 491f814..c456006 100644 --- a/include/pci.h +++ b/include/pci.h @@ -536,6 +536,7 @@ extern int pci_hose_config_device(struct pci_controller *hose, pci_addr_t mem, unsigned long command);
+const char * pci_class_str(u8 class); int pci_last_busno(void);
#ifdef CONFIG_MPC824X
Dear Peter Tyser,
In message 1288393169-9814-4-git-send-email-ptyser@xes-inc.com you wrote:
This change does the following:
Removes the printing of the PCI interrupt line value. This is normally set to 0 by U-Boot on bootup and is rarely used during everyday operation.
Prints out the PCI function number of a device. Previously a device with multiple functions would be printed identically 2 times, which is generally confusing. For example, on an Intel 2 port gigabit Ethernet card the following was displayed: ... 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 ...
Prints a text description of each device's PCI class instead of the raw PCI class code. The textual description makes it much easier to determine what devices are installed on a PCI bus.
Changes the general formatting of the PCI device output.
Previous output: PCIE1: connected as Root Complex 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d
Updated output: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d
Signed-off-by: Peter Tyser ptyser@xes-inc.com
common/cmd_pci.c | 66 +----------------------------- drivers/pci/pci.c | 117 ++++++++++++++++++++++++++++++++++++++++------------- include/pci.h | 1 + 3 files changed, 92 insertions(+), 92 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
Move the printing of PCI device information to before the PCI device is configured. This prevents the case where recursive scanning results in the deepest devices being printed first.
This change also makes PCI lockups during enumeration easier to diagnose since the device that is being configured is printed out prior to configuration. Previously, it was not possible to determine which device caused the PCI lockup.
Original example: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b
Updated example: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- drivers/pci/pci.c | 17 +++++++++-------- 1 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 3dccf88..78f7339 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -645,6 +645,14 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device); pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
+#ifdef CONFIG_PCI_SCAN_SHOW + if (pci_print_dev(hose, dev)) { + printf(" %02x:%02x.%x - %04x:%04x - %s\n", + PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), + vendor, device, pci_class_str(class >> 8)); + } +#endif + cfg = pci_find_config(hose, class, vendor, device, PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev)); if (cfg) { @@ -657,16 +665,9 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) sub_bus = max(sub_bus, n); #endif } + if (hose->fixup_irq) hose->fixup_irq(hose, dev); - -#ifdef CONFIG_PCI_SCAN_SHOW - if (pci_print_dev(hose, dev)) { - printf(" %02x:%02x.%x - %04x:%04x - %s\n", - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), - vendor, device, pci_class_str(class >> 8)); - } -#endif }
return sub_bus;
Dear Peter Tyser,
In message 1288393169-9814-5-git-send-email-ptyser@xes-inc.com you wrote:
Move the printing of PCI device information to before the PCI device is configured. This prevents the case where recursive scanning results in the deepest devices being printed first.
This change also makes PCI lockups during enumeration easier to diagnose since the device that is being configured is printed out prior to configuration. Previously, it was not possible to determine which device caused the PCI lockup.
Original example: PCIE1: connected as Root Complex 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 03:00.0 - 10b5:8112 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 02:02.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:00.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:01.0 - 10b5:8518 - Bridge device 07:02.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 01:00.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b
Updated example: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b
Signed-off-by: Peter Tyser ptyser@xes-inc.com
drivers/pci/pci.c | 17 +++++++++-------- 1 files changed, 9 insertions(+), 8 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as they are found during bootup, eg: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d
This information is useful, but its difficult to determine the PCI bus topology. To things clearer, we can use indention to make it more obvious how the PCI bus is organized. For the example above, the updated output with this change is:
PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d
In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch (01:00 and 02:0x), which is connected to another PEX8518 PCIe switch (06:00 and 07:0x), which then connects to a MPC8572 processor (08:00). Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00).
Signed-off-by: Peter Tyser ptyser@xes-inc.com --- drivers/pci/pci.c | 16 ++++++++++++++-- 1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 78f7339..702ac67 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -616,6 +616,9 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) unsigned char header_type; struct pci_config_table *cfg; pci_dev_t dev; +#ifdef CONFIG_PCI_SCAN_SHOW + static int indent = 0; +#endif
sub_bus = bus;
@@ -646,9 +649,14 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
#ifdef CONFIG_PCI_SCAN_SHOW + indent++; + + /* Print leading space, including bus indentation */ + printf("%*c", indent + 1, ' '); + if (pci_print_dev(hose, dev)) { - printf(" %02x:%02x.%x - %04x:%04x - %s\n", - PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), + printf("%02x:%02x.%-*x - %04x:%04x - %s\n", + PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev), vendor, device, pci_class_str(class >> 8)); } #endif @@ -666,6 +674,10 @@ int pci_hose_scan_bus(struct pci_controller *hose, int bus) #endif }
+#ifdef CONFIG_PCI_SCAN_SHOW + indent--; +#endif + if (hose->fixup_irq) hose->fixup_irq(hose, dev); }
Dear Peter Tyser,
In message 1288393169-9814-6-git-send-email-ptyser@xes-inc.com you wrote:
When CONFIG_PCI_SCAN_SHOW is defined U-Boot prints out PCI devices as they are found during bootup, eg: PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d
This information is useful, but its difficult to determine the PCI bus topology. To things clearer, we can use indention to make it more obvious how the PCI bus is organized. For the example above, the updated output with this change is:
PCIE1: connected as Root Complex 01:00.0 - 10b5:8518 - Bridge device 02:01.0 - 10b5:8518 - Bridge device 03:00.0 - 10b5:8112 - Bridge device 04:01.0 - 8086:1010 - Network controller 04:01.1 - 8086:1010 - Network controller 02:02.0 - 10b5:8518 - Bridge device 02:03.0 - 10b5:8518 - Bridge device 06:00.0 - 10b5:8518 - Bridge device 07:00.0 - 10b5:8518 - Bridge device 08:00.0 - 1957:0040 - Processor 07:01.0 - 10b5:8518 - Bridge device 09:00.0 - 10b5:8112 - Bridge device 07:02.0 - 10b5:8518 - Bridge device PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex 0d:00.0 - 1957:0040 - Processor PCIE2: Bus 0c - 0d
In the examples above, an MPC8640 is connected to a PEX8518 PCIe switch (01:00 and 02:0x), which is connected to another PEX8518 PCIe switch (06:00 and 07:0x), which then connects to a MPC8572 processor (08:00). Also, the MPC8640's PEX8518 PCIe switch is connected to a PCI ethernet card (04:01) via a PEX8112 PCIe-to-PCI bridge (03:00).
Signed-off-by: Peter Tyser ptyser@xes-inc.com
drivers/pci/pci.c | 16 ++++++++++++++-- 1 files changed, 14 insertions(+), 2 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
Dear Peter Tyser,
In message 1288393169-9814-1-git-send-email-ptyser@xes-inc.com you wrote:
Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like:
... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ...
Signed-off-by: Peter Tyser ptyser@xes-inc.com CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
This series assumes "fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware" has already been applied.
board/atum8548/atum8548.c | 12 ++++++------ board/freescale/corenet_ds/pci.c | 16 ++++++++-------- board/freescale/mpc8536ds/mpc8536ds.c | 16 ++++++++-------- board/freescale/mpc8540ads/mpc8540ads.c | 4 ++-- board/freescale/mpc8541cds/mpc8541cds.c | 6 +++--- board/freescale/mpc8544ds/mpc8544ds.c | 24 ++++++++++++------------ board/freescale/mpc8548cds/mpc8548cds.c | 16 ++++++++-------- board/freescale/mpc8555cds/mpc8555cds.c | 6 +++--- board/freescale/mpc8560ads/mpc8560ads.c | 4 ++-- board/freescale/mpc8568mds/mpc8568mds.c | 8 ++++---- board/freescale/mpc8569mds/mpc8569mds.c | 8 ++++---- board/freescale/mpc8572ds/mpc8572ds.c | 20 ++++++++++---------- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 20 ++++++++++---------- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 18 +++++++++--------- board/freescale/p1022ds/p1022ds.c | 8 ++++---- board/freescale/p1_p2_rdb/pci.c | 16 ++++++++-------- board/freescale/p2020ds/p2020ds.c | 24 ++++++++++++------------ board/pm854/pm854.c | 4 ++-- board/pm856/pm856.c | 4 ++-- board/sbc8548/sbc8548.c | 8 ++++---- board/sbc8641d/sbc8641d.c | 18 +++++++++--------- board/tqc/tqm85xx/tqm85xx.c | 8 ++++---- board/xes/common/fsl_8xxx_pci.c | 16 ++++++++-------- drivers/pci/fsl_pci_init.c | 10 +++++----- 24 files changed, 147 insertions(+), 147 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
participants (2)
-
Peter Tyser -
Wolfgang Denk