This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux.

Signed-off-by: Bhupesh Sharma bhupesh.sharma@freescale.com --- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 72 +++++++++++++++++++++++--- arch/arm/include/asm/arch-fsl-lsch3/config.h | 11 ++++ arch/arm/lib/Makefile | 1 + arch/arm/lib/ccn504.S | 61 ++++++++++++++++++++++ 4 files changed, 138 insertions(+), 7 deletions(-) create mode 100644 arch/arm/lib/ccn504.S

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 018c617..6b19d36 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -16,13 +16,71 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */

/* Add fully-coherent masters to DVM domain */ - ldr x1, =CCI_MN_BASE - ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] - str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] -1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] - mvn x0, x3 - tst x0, x3 /* Wait for domain addition to complete */ - b.ne 1b + ldr x0, =CCI_MN_BASE + ldr x1, =CCI_MN_RNF_NODEID_LIST + ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET + bl ccn504_add_masters_to_dvm + + /* Set all RN-I ports to QoS of 15 */ + ldr x0, =CCI_S0_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(0) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(2) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(6) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(12) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(16) + ldr x1, =0x00FF000C + bl ccn504_set_qos + + ldr x0, =CCI_S0_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S1_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos + ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) + ldr x1, =0x00FF000C + bl ccn504_set_qos

/* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index ca8d38c..c47950c 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -132,6 +132,17 @@ #define CCI_MN_DVM_DOMAIN_CTL 0x200 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210

+#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) +#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) +#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) +#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) +#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) +#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) + +#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) +#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) +#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) + /* Device Configuration */ #define DCFG_BASE 0x01e00000 #define DCFG_PORSR1 0x000 diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 31a5c8d..51497cc 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -42,6 +42,7 @@ obj-y += stack.o ifdef CONFIG_CPU_V7M obj-y += interrupts_m.o else ifdef CONFIG_ARM64 +obj-y += ccn504.o obj-y += gic_64.o obj-y += interrupts_64.o else diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S new file mode 100644 index 0000000..ce55fb1 --- /dev/null +++ b/arch/arm/lib/ccn504.S @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2015 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Extracted from gic_64.S + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> + +/************************************************************************* + * + * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST, + * CCI_MN_DVM_DOMAIN_CTL_SET); + * + * Add fully-coherent masters to DVM domain + * + *************************************************************************/ +ENTRY(ccn504_add_masters_to_dvm) + /* + * x0: CCI_MN_BASE + * x1: CCI_MN_RNF_NODEID_LIST + * x2: CCI_MN_DVM_DOMAIN_CTL_SET + */ + + /* Add fully-coherent masters to DVM domain */ + ldr x9, [x0, x1] + str x9, [x0, x2] +1: ldr x10, [x0, x2] + mvn x11, x10 + tst x11, x10 /* Wait for domain addition to complete */ + b.ne 1b + + ret +ENDPROC(ccn504_add_masters_to_dvm) + +/************************************************************************* + * + * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value); + * + * Initialize QoS settings for AR/AW override. + * Right now, this function sets the same QoS value for all RN-I ports + * + *************************************************************************/ +ENTRY(ccn504_set_qos) + /* + * x0: CCI_Sx_QOS_CONTROL_BASE + * x1: QoS Value + */ + + /* Set all RN-I ports to QoS of 15 */ + ldr x9, [x0] + mov x10, x1 + orr x9, x9, x10 + str x9, [x0] + + ret +ENDPROC(ccn504_set_qos) +