[U-Boot] [PATCH v1 1/7] mmc: fsl_esdhc: Add peripheral clock support
This patch is to add peripheral clock support
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 49 ++++++++++++------- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 45 ++++++++++++++++- .../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- .../asm/arch-fsl-layerscape/immap_lsch3.h | 1 + 4 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 9ece4b90e6..23391398ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -22,10 +22,12 @@ DECLARE_GLOBAL_DATA_PTR; void get_sys_info(struct sys_info *sys_info) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); -#if (defined(CONFIG_FSL_ESDHC) &&\ - defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\ - defined(CONFIG_SYS_DPAA_FMAN) - +/* rcw_tmp is needed to get FMan clock, or to get cluster group A + * mux 2 clock for LS1043A/LS1046A. + */ +#if defined(CONFIG_SYS_DPAA_FMAN) || \ + defined(CONFIG_TARGET_LS1046ARDB) || \ + defined(CONFIG_TARGET_LS1043ARDB) u32 rcw_tmp; #endif struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); @@ -122,32 +124,32 @@ void get_sys_info(struct sys_info *sys_info) } #endif
+#ifdef CONFIG_FSL_ESDHC #define HWA_CGA_M2_CLK_SEL 0x00000007 #define HWA_CGA_M2_CLK_SHIFT 0 -#ifdef CONFIG_FSL_ESDHC -#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK +#if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB) rcw_tmp = in_be32(&gur->rcwsr[15]); switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { case 1: - sys_info->freq_sdhc = freq_c_pll[1]; + sys_info->freq_cga_m2 = freq_c_pll[1]; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 2: - sys_info->freq_sdhc = freq_c_pll[1] / 2; + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; break; +#endif case 3: - sys_info->freq_sdhc = freq_c_pll[1] / 3; + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; break; +#if defined(CONFIG_TARGET_LS1046ARDB) case 6: - sys_info->freq_sdhc = freq_c_pll[0] / 2; + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; break; +#endif default: - printf("Error: Unknown ESDHC clock select!\n"); + printf("Error: Unknown peripheral clock select!\n"); break; } -#else - sys_info->freq_sdhc = (sys_info->freq_systembus / - CONFIG_SYS_FSL_PCLK_DIV) / - CONFIG_SYS_FSL_SDHC_CLK_DIV; #endif #endif
@@ -183,9 +185,22 @@ int get_clocks(void) gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_FSL_ESDHC - gd->arch.sdhc_clk = sys_info.freq_sdhc; +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1046ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS1043ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#if defined(CONFIG_TARGET_LS1012ARDB) + gd->arch.sdhc_clk = sys_info.freq_systembus; +#endif +#else + gd->arch.sdhc_clk = (sys_info.freq_systembus / + CONFIG_SYS_FSL_PCLK_DIV) / + CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif - if (gd->cpu_clk != 0) return 0; else diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index a5540f2b9d..b3e67321b4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,6 +64,9 @@ void get_sys_info(struct sys_info *sys_info) };
uint i, cluster; +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + uint rcw_tmp; +#endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = CONFIG_SYS_CLK_FREQ; @@ -127,8 +130,39 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_localbus = sys_info->freq_systembus / CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -}
+#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#define HWA_CGA_M2_CLK_SEL 0x00380000 +#define HWA_CGA_M2_CLK_SHIFT 19 + rcw_tmp = in_le32(&gur->rcwsr[5]); + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { + case 1: + sys_info->freq_cga_m2 = freq_c_pll[1]; + break; + case 2: + sys_info->freq_cga_m2 = freq_c_pll[1] / 2; + break; + case 3: + sys_info->freq_cga_m2 = freq_c_pll[1] / 3; + break; + case 4: + sys_info->freq_cga_m2 = freq_c_pll[1] / 4; + break; + case 6: + sys_info->freq_cga_m2 = freq_c_pll[0] / 2; + break; + case 7: + sys_info->freq_cga_m2 = freq_c_pll[0] / 3; + break; + default: + printf("Error: Unknown peripheral clock select!\n"); + break; + } +#endif +#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) + sys_info->freq_cga_m2 = sys_info->freq_systembus; +#endif +}
int get_clocks(void) { @@ -141,7 +175,16 @@ int get_clocks(void) gd->arch.mem2_clk = sys_info.freq_ddrbus2; #endif #if defined(CONFIG_FSL_ESDHC) +#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) +#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; +#endif +#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) + gd->arch.sdhc_clk = sys_info.freq_cga_m2; +#endif +#else gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV; +#endif #endif /* defined(CONFIG_FSL_ESDHC) */
if (gd->cpu_clk != 0) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index b4b7c3492e..3a59abb10e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -180,7 +180,7 @@ struct sys_info { unsigned long freq_systembus; unsigned long freq_ddrbus; unsigned long freq_localbus; - unsigned long freq_sdhc; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_DPAA_FMAN unsigned long freq_fman[CONFIG_SYS_NUM_FMAN]; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index ee9b33becf..3cea71ad75 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -255,6 +255,7 @@ struct sys_info { /* frequency of platform PLL */ unsigned long freq_systembus; unsigned long freq_ddrbus; + unsigned long freq_cga_m2; #ifdef CONFIG_SYS_FSL_HAS_DP_DDR unsigned long freq_ddrbus2; #endif
eSDHC supports two reference clocks (platform clock and peripheral clock). Peripheral clock which could provide higher clock frequency is required to be used for tuning of SD UHS mode and eMMC HS200/HS400 modes.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- drivers/mmc/Kconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 93588725f2..2106a6a197 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -136,7 +136,6 @@ config MMC_HS200_SUPPORT The HS200 mode is support by some eMMC. The bus frequency is up to 200MHz. This mode requires tuning the IO.
- config SPL_MMC_HS200_SUPPORT bool "enable HS200 support in SPL" help @@ -667,10 +666,19 @@ config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
config FSL_ESDHC bool "Freescale/NXP eSDHC controller support" + select FSL_ESDHC_USE_PERIPHERAL_CLK if MMC_HS200_SUPPORT || MMC_UHS_SUPPORT help This selects support for the eSDHC (Enhanced Secure Digital Host Controller) found on numerous Freescale/NXP SoCs.
+config FSL_ESDHC_USE_PERIPHERAL_CLK + bool "enable ESDHC peripheral clock support" + depends on FSL_ESDHC + help + eSDHC supports two reference clocks (platform clock and peripheral clock). + Peripheral clock which could provide higher clock frequency is required to + be used for tuning of SD UHS mode and eMMC HS200/HS400 modes. + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help
This patch is to add emmc hs200 support for ls1012ardb
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- arch/arm/dts/fsl-ls1012a-rdb.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi index f053e789c2..55155fd321 100644 --- a/arch/arm/dts/fsl-ls1012a-rdb.dtsi +++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi @@ -14,6 +14,10 @@ }; };
+&esdhc1 { + mmc-hs200-1_8v; +}; + &qspi { bus-num = <0>; status = "okay";
This patch is to add emmc hs200 support for lx2160ardb
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- arch/arm/dts/fsl-lx2160a-rdb.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 4b526449a1..3b928b6168 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -25,6 +25,7 @@
&esdhc1 { status = "okay"; + mmc-hs200-1_8v; };
&sata0 {
This patch is to add emmc hs200 support for ls1028ardb
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- arch/arm/dts/fsl-ls1028a-rdb.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 932cfa2275..44e9e33114 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -33,6 +33,7 @@
&esdhc1 { status = "okay"; + mmc-hs200-1_8v; };
&i2c0 {
Add eMMC hs200 mode support for increasing ls1028/ls1012/lx2160 eMMC work performance, but without tuning procedure which will cause mmc doesn't work. and this should be TODO work.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- drivers/mmc/fsl_esdhc.c | 34 +++++++++++++++++++--------------- include/fsl_esdhc.h | 4 ++++ 2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 07318472a7..28d2312ef7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -395,10 +395,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_write32(®s->cmdarg, cmd->cmdarg); esdhc_write32(®s->xfertyp, xfertyp);
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || - (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) - flags = IRQSTAT_BRR; - /* Wait for the command to complete */ start = get_timer(0); while (!(esdhc_read32(®s->irqstat) & flags)) { @@ -458,12 +454,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(priv, data); #else - flags = DATA_COMPLETE; - if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) || - (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) { - flags = IRQSTAT_BRR; - } - do { irqstat = esdhc_read32(®s->irqstat);
@@ -476,7 +466,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, err = -ECOMM; goto out; } - } while ((irqstat & flags) != flags); + } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
/* * Need invalidate the dcache here again to avoid any @@ -517,7 +507,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) int div = 1; int pre_div = 2; int ddr_pre_div = mmc->ddr_mode ? 2 : 1; - int sdhc_clk = priv->sdhc_clk; + unsigned int sdhc_clk = priv->sdhc_clk; + u32 time_out; + u32 value; uint clk;
if (clock < mmc->cfg->f_min) @@ -538,11 +530,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000); + time_out = 20; + value = PRSSTAT_SDSTB; + while (!(esdhc_read32(®s->prsstat) & value)) { + if (time_out == 0) { + printf("fsl_esdhc: Internal clock never stabilised.\n"); + break; + } + time_out--; + mdelay(1); + }
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); - - priv->clock = clock; }
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -1024,6 +1023,8 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; }
+ mmc_of_parse(dev, &plat->cfg); + mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev; @@ -1081,6 +1082,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, +#ifdef MMC_SUPPORTS_TUNING + .execute_tuning = fsl_esdhc_execute_tuning, +#endif }; #endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 7d7e946ab3..3f496b4cea 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -205,6 +205,10 @@ struct fsl_esdhc_cfg { int fsl_esdhc_mmc_init(bd_t *bis); int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, bd_t *bd); +#ifdef MMC_SUPPORTS_TUNING +static inline int fsl_esdhc_execute_tuning(struct udevice *dev, + uint32_t opcode) {return 0; } +#endif #else static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
Hi Peng
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Yinbo Zhu Sent: Tuesday, July 16, 2019 12:39 PM To: York Sun york.sun@nxp.com; u-boot@lists.denx.de Cc: Jiafei Pan jiafei.pan@nxp.com; Yinbo Zhu yinbo.zhu@nxp.com; Xiaobo Xie xiaobo.xie@nxp.com Subject: [U-Boot] [PATCH v1 6/7] mmc: fsl_esdhc: Add emmc hs200 support
Add eMMC hs200 mode support for increasing ls1028/ls1012/lx2160 eMMC work performance, but without tuning procedure which will cause mmc doesn't work. and this should be TODO work.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com
drivers/mmc/fsl_esdhc.c | 34 +++++++++++++++++++--------------- include/fsl_esdhc.h | 4 ++++ 2 files changed, 23 insertions(+), 15 deletions(-)
Can you please review and ack this patch. I will review other patches and send pull via my tree.
--pk
Subject: [U-Boot] [PATCH v1 6/7] mmc: fsl_esdhc: Add emmc hs200 support
Add eMMC hs200 mode support for increasing ls1028/ls1012/lx2160 eMMC work performance, but without tuning procedure which will cause mmc doesn't work. and this should be TODO work.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com
Acked-by: Peng Fan peng.fan@nxp.com
drivers/mmc/fsl_esdhc.c | 34 +++++++++++++++++++--------------- include/fsl_esdhc.h | 4 ++++ 2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 07318472a7..28d2312ef7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -395,10 +395,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_write32(®s->cmdarg, cmd->cmdarg); esdhc_write32(®s->xfertyp, xfertyp);
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))flags = IRQSTAT_BRR;- /* Wait for the command to complete */ start = get_timer(0); while (!(esdhc_read32(®s->irqstat) & flags)) { @@ -458,12 +454,6
@@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(priv, data); #else
flags = DATA_COMPLETE;if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)){
flags = IRQSTAT_BRR;}- do { irqstat = esdhc_read32(®s->irqstat);
@@ -476,7 +466,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, err = -ECOMM; goto out; }
} while ((irqstat & flags) != flags);
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);/*
- Need invalidate the dcache here again to avoid any @@ -517,7
+507,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) int div = 1; int pre_div = 2; int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- int sdhc_clk = priv->sdhc_clk;
unsigned int sdhc_clk = priv->sdhc_clk;
u32 time_out;
u32 value; uint clk;
if (clock < mmc->cfg->f_min)
@@ -538,11 +530,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000);
time_out = 20;
value = PRSSTAT_SDSTB;
while (!(esdhc_read32(®s->prsstat) & value)) {
if (time_out == 0) {printf("fsl_esdhc: Internal clock never stabilised.\n");break;}time_out--;mdelay(1);}
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
- priv->clock = clock;
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -1024,6 +1023,8 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; }
- mmc_of_parse(dev, &plat->cfg);
- mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev;
@@ -1081,6 +1082,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, +#ifdef MMC_SUPPORTS_TUNING
- .execute_tuning = fsl_esdhc_execute_tuning, #endif
}; #endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 7d7e946ab3..3f496b4cea 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -205,6 +205,10 @@ struct fsl_esdhc_cfg { int fsl_esdhc_mmc_init(bd_t *bis); int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, bd_t *bd); +#ifdef MMC_SUPPORTS_TUNING +static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
- uint32_t opcode) {return 0; }
+#endif #else static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} -- 2.17.1
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Hi York Sun,
Could you help me merge that series patch to uboot upstream tree.
Regards, Yinbo Zhu ----Original Message----- From: Peng Fan Sent: 2019年8月28日 9:04 To: Yinbo Zhu yinbo.zhu@nxp.com; York Sun york.sun@nxp.com; u-boot@lists.denx.de Cc: Jiafei Pan jiafei.pan@nxp.com; Yinbo Zhu yinbo.zhu@nxp.com; Xiaobo Xie xiaobo.xie@nxp.com Subject: RE: [U-Boot] [PATCH v1 6/7] mmc: fsl_esdhc: Add emmc hs200 support
Subject: [U-Boot] [PATCH v1 6/7] mmc: fsl_esdhc: Add emmc hs200 support
Add eMMC hs200 mode support for increasing ls1028/ls1012/lx2160 eMMC work performance, but without tuning procedure which will cause mmc doesn't work. and this should be TODO work.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com
Acked-by: Peng Fan peng.fan@nxp.com
drivers/mmc/fsl_esdhc.c | 34 +++++++++++++++++++--------------- include/fsl_esdhc.h | 4 ++++ 2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 07318472a7..28d2312ef7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -395,10 +395,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_write32(®s->cmdarg, cmd->cmdarg); esdhc_write32(®s->xfertyp, xfertyp);
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))flags = IRQSTAT_BRR;- /* Wait for the command to complete */ start = get_timer(0); while (!(esdhc_read32(®s->irqstat) & flags)) { @@ -458,12 +454,6
@@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(priv, data); #else
flags = DATA_COMPLETE;if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)){
flags = IRQSTAT_BRR;}- do { irqstat = esdhc_read32(®s->irqstat);
@@ -476,7 +466,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, err = -ECOMM; goto out; }
} while ((irqstat & flags) != flags);
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);/*
- Need invalidate the dcache here again to avoid any @@ -517,7
+507,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct +mmc *mmc, uint clock) int div = 1; int pre_div = 2; int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- int sdhc_clk = priv->sdhc_clk;
unsigned int sdhc_clk = priv->sdhc_clk;
u32 time_out;
u32 value; uint clk;
if (clock < mmc->cfg->f_min)
@@ -538,11 +530,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000);
time_out = 20;
value = PRSSTAT_SDSTB;
while (!(esdhc_read32(®s->prsstat) & value)) {
if (time_out == 0) {printf("fsl_esdhc: Internal clock never stabilised.\n");break;}time_out--;mdelay(1);}
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
- priv->clock = clock;
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -1024,6 +1023,8 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; }
- mmc_of_parse(dev, &plat->cfg);
- mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev;
@@ -1081,6 +1082,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, +#ifdef MMC_SUPPORTS_TUNING
- .execute_tuning = fsl_esdhc_execute_tuning, #endif
}; #endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 7d7e946ab3..3f496b4cea 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -205,6 +205,10 @@ struct fsl_esdhc_cfg { int fsl_esdhc_mmc_init(bd_t *bis); int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, bd_t *bd); +#ifdef MMC_SUPPORTS_TUNING +static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
- uint32_t opcode) {return 0; }
+#endif #else static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} -- 2.17.1
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Yinbo,
Priyanka is the maintainer now for NXP platforms.
York
On Sep 9, 2019, at 20:10, Yinbo Zhu yinbo.zhu@nxp.com wrote:
Hi York Sun,
Could you help me merge that series patch to uboot upstream tree.
Regards, Yinbo Zhu ----Original Message----- From: Peng Fan Sent: 2019年8月28日 9:04 To: Yinbo Zhu yinbo.zhu@nxp.com; York Sun york.sun@nxp.com; u-boot@lists.denx.de Cc: Jiafei Pan jiafei.pan@nxp.com; Yinbo Zhu yinbo.zhu@nxp.com; Xiaobo Xie xiaobo.xie@nxp.com Subject: RE: [U-Boot] [PATCH v1 6/7] mmc: fsl_esdhc: Add emmc hs200 support
Subject: [U-Boot] [PATCH v1 6/7] mmc: fsl_esdhc: Add emmc hs200 support
Add eMMC hs200 mode support for increasing ls1028/ls1012/lx2160 eMMC work performance, but without tuning procedure which will cause mmc doesn't work. and this should be TODO work.
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com
Acked-by: Peng Fan peng.fan@nxp.com
drivers/mmc/fsl_esdhc.c | 34 +++++++++++++++++++--------------- include/fsl_esdhc.h | 4 ++++ 2 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 07318472a7..28d2312ef7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -395,10 +395,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, esdhc_write32(®s->cmdarg, cmd->cmdarg); esdhc_write32(®s->xfertyp, xfertyp);
- if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))flags = IRQSTAT_BRR;- /* Wait for the command to complete */ start = get_timer(0); while (!(esdhc_read32(®s->irqstat) & flags)) { @@ -458,12 +454,6
@@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO esdhc_pio_read_write(priv, data); #else
flags = DATA_COMPLETE;if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||(cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)){
flags = IRQSTAT_BRR;}do { irqstat = esdhc_read32(®s->irqstat);@@ -476,7 +466,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, err = -ECOMM; goto out; }
} while ((irqstat & flags) != flags);
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); /* * Need invalidate the dcache here again to avoid any @@ -517,7+507,9 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct +mmc *mmc, uint clock) int div = 1; int pre_div = 2; int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
- int sdhc_clk = priv->sdhc_clk;
unsigned int sdhc_clk = priv->sdhc_clk;
u32 time_out;
u32 value; uint clk;
if (clock < mmc->cfg->f_min)
@@ -538,11 +530,18 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
- udelay(10000);
time_out = 20;
value = PRSSTAT_SDSTB;
while (!(esdhc_read32(®s->prsstat) & value)) {
if (time_out == 0) {printf("fsl_esdhc: Internal clock never stabilised.\n");break;}time_out--;mdelay(1);}
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
- priv->clock = clock;
}
#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK @@ -1024,6 +1023,8 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; }
- mmc_of_parse(dev, &plat->cfg);
- mmc = &plat->mmc; mmc->cfg = &plat->cfg; mmc->dev = dev;
@@ -1081,6 +1082,9 @@ static const struct dm_mmc_ops fsl_esdhc_ops = { .get_cd = fsl_esdhc_get_cd, .send_cmd = fsl_esdhc_send_cmd, .set_ios = fsl_esdhc_set_ios, +#ifdef MMC_SUPPORTS_TUNING
- .execute_tuning = fsl_esdhc_execute_tuning, #endif
}; #endif
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 7d7e946ab3..3f496b4cea 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -205,6 +205,10 @@ struct fsl_esdhc_cfg { int fsl_esdhc_mmc_init(bd_t *bis); int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); void fdt_fixup_esdhc(void *blob, bd_t *bd); +#ifdef MMC_SUPPORTS_TUNING +static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
- uint32_t opcode) {return 0; }
+#endif #else static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} -- 2.17.1
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This patch is to add CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK and CONFIG_MMC_HS200_SUPPORT
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK and CONFIG_MMC_HS200_SUPPORT
Signed-off-by: Yinbo Zhu yinbo.zhu@nxp.com --- configs/ls1012ardb_tfa_defconfig | 2 ++ configs/ls1028ardb_tfa_defconfig | 2 ++ configs/lx2160ardb_tfa_defconfig | 2 ++ 3 files changed, 6 insertions(+)
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 8acc07d3c8..e6b5e1c5e4 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -55,4 +55,6 @@ CONFIG_FSL_QSPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y +CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 2d0c2b1345..0803bfffb3 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -63,4 +63,6 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_WDT=y CONFIG_WDT_SP805=y +CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 94f58a832f..6aab95e22f 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -56,4 +56,6 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y +CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK=y +CONFIG_MMC_HS200_SUPPORT=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
participants (4)
-
Peng Fan -
Prabhakar Kushwaha -
Yinbo Zhu -
York Sun