This is in CVS as well as u-boot-1.1.2.tar.bz2 and as far back as at least u-boot-0.2.0.tar.bz2

File: include/ppc440.h Line:235 Context: #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ #define xbcid 0x23 /* external bus core id reg */ ^^^^ According to the 440GX user manual (mine's dated Nov 21, 2003) table 4-13 on page 186, EBC0_CID the "EBCO Peripheral Core ID Register" is located at offset 0x24. This register is not currently referenced by any code in the u-boot-1.1.2.tar.bz2 release, which explains why it has survied so long.

Also note that the header comment for this section has a typo, which is also corrected in the attached patch.

-- Andrew E. Mileski

diff -urN include/ppc440.h.orig include/ppc440.h --- include/ppc440.h.orig 2005-02-04 15:55:53.000000000 -0500 +++ include/ppc440.h 2005-02-04 16:13:20.000000000 -0500 @@ -207,7 +207,7 @@ #define mem_eccesr 0x0098 /* ECC error status */

/*----------------------------------------------------------------------------- - | Extrnal Bus Controller + | External Bus Controller +----------------------------------------------------------------------------*/ #define EBC_DCR_BASE 0x12 #define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ @@ -232,7 +232,7 @@ #define pbear 0x20 /* periph bus error addr reg */ #define pbesr 0x21 /* periph bus error status reg */ #define xbcfg 0x23 /* external bus configuration reg */ -#define xbcid 0x23 /* external bus core id reg */ +#define xbcid 0x24 /* external bus core id reg */

/*----------------------------------------------------------------------------- | Internal SRAM