[U-Boot] [PATCH v3 0/8] tegra2: Tidy up boot path
On Tegra2 the AVP runs the normal U-Boot code to a point, then halts and the A9 takes over. The current Tegra2 boot path is fairly complex, since it has a separate path and code for the Cortex-A9 and the AVP. In fact, they can largely execute the same code path.
This series cleans up this logic and removes some parallel and un-needed code.
Changes in v2: - Move Makefile armv4t flags from arch/arm/lib to Tegra's config.mk - Keep Tegra's config.mk file around so we can set the armv4t flags
Changes in v3: - Update comment and also make it match style - Fix cpu_init_cp15() name - Remove exporting of cpu_init_cp15() from start.S - Add test for ARMv7 CPU and skip CP15 init if not found - Add lowlevel_init function back in (though it does nothing) - Remove later CP15 init in board.c since this is not needed now - Rebase against master (due to CONFIG_SYS_CACHELINE_SIZE series)
Simon Glass (8): tegra2: Add arch_cpu_init() to fire up Cortex-A9 tegra2: Simplify tegra_start() boot path arm: Only do CP15 init on ARMv7 tegra2: Remove unneeded boot code tegra2: Remove unneeded config option tegra2: Remove unused low-level Tegra2 UART code tegra2: Remove unneeded 'dynamic ram size' message tegra2: Don't use board pointer before it is set up
arch/arm/cpu/armv7/start.S | 57 ++++++-------- arch/arm/cpu/armv7/tegra2/Makefile | 5 + arch/arm/cpu/armv7/tegra2/ap20.c | 54 +++++++------ arch/arm/cpu/armv7/tegra2/ap20.h | 10 +-- arch/arm/cpu/armv7/tegra2/board.c | 35 ++++----- arch/arm/cpu/armv7/tegra2/config.mk | 7 +- arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 115 +---------------------------- board/nvidia/common/board.c | 3 - board/nvidia/common/board.h | 1 - drivers/serial/Makefile | 1 - drivers/serial/serial_tegra2.c | 77 ------------------- drivers/serial/serial_tegra2.h | 29 ------- include/configs/tegra2-common.h | 5 +- 13 files changed, 86 insertions(+), 313 deletions(-) delete mode 100644 drivers/serial/serial_tegra2.c delete mode 100644 drivers/serial/serial_tegra2.h
We want to move away from a special Tegra2 start-up, and just use arch_cpu_init() instead. However, if we run board_init_f() from boot we need to build it for ARMv4T, since the Tegra's AVP start-up CPU does not support ARMv7.
The effect of this is to do the AVP init earlier, and in arch_cpu_init(), rather that board_early_init_f().
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Move Makefile armv4t flags from arch/arm/lib to Tegra's config.mk
arch/arm/cpu/armv7/tegra2/board.c | 15 +++++++++++++++ arch/arm/cpu/armv7/tegra2/config.mk | 6 ++++++ board/nvidia/common/board.c | 3 --- board/nvidia/common/board.h | 1 - include/configs/tegra2-common.h | 1 + 5 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 751102d..4530194 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -23,6 +23,7 @@
#include <common.h> #include <asm/io.h> +#include "ap20.h" #include <asm/arch/sys_proto.h> #include <asm/arch/tegra2.h> #include <asm/arch/pmc.h> @@ -86,3 +87,17 @@ int checkboard(void) return 0; } #endif /* CONFIG_DISPLAY_BOARDINFO */ + +#ifdef CONFIG_ARCH_CPU_INIT +/* + * Note this function is executed by the ARM7TDMI AVP. It does not return + * in this case. It is also called once the A9 starts up, but does nothing in + * that case. + */ +int arch_cpu_init(void) +{ + /* Fire up the Cortex A9 */ + tegra2_start(); + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index 96c0795..f84fdc8 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -26,3 +26,9 @@
# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI. PLATFORM_CPPFLAGS += -march=armv4 + +# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this +# file with compatible flags +ifdef CONFIG_TEGRA2 +CFLAGS_arch/arm/lib/board.o += -march=armv4t +endif diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 0f12de2..56850cc 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -125,9 +125,6 @@ int board_early_init_f(void)
/* Initialize periph GPIOs */ gpio_config_uart(); - - /* Init UART, scratch regs, and start CPU */ - tegra2_start(); return 0; } #endif /* EARLY_INIT */ diff --git a/board/nvidia/common/board.h b/board/nvidia/common/board.h index 35acbca..1f57086 100644 --- a/board/nvidia/common/board.h +++ b/board/nvidia/common/board.h @@ -24,7 +24,6 @@ #ifndef _BOARD_H_ #define _BOARD_H_
-void tegra2_start(void); void gpio_config_uart(void); int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index a9c665c..bdf7eab 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -35,6 +35,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ #define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
#include <asm/arch/tegra2.h> /* get chip and board defs */
On Monday 31 October 2011 18:03:05 Simon Glass wrote:
--- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk
# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI. PLATFORM_CPPFLAGS += -march=armv4
+# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this +# file with compatible flags +ifdef CONFIG_TEGRA2 +CFLAGS_arch/arm/lib/board.o += -march=armv4t +endif
do you need this CONFIG_TEGRA2 check ? this is in tegra2/config.mk already. -mike
Hi Mike,
On Thu, Nov 3, 2011 at 7:17 PM, Mike Frysinger vapier@gentoo.org wrote:
On Monday 31 October 2011 18:03:05 Simon Glass wrote:
--- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk
# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI. PLATFORM_CPPFLAGS += -march=armv4
+# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this +# file with compatible flags +ifdef CONFIG_TEGRA2 +CFLAGS_arch/arm/lib/board.o += -march=armv4t +endif
do you need this CONFIG_TEGRA2 check ? this is in tegra2/config.mk already. -mike
No not needed - will send a new patch with this removed.
Regards, Simon
The Tegra2 boot path is more complicated than it needs to be. Since we want to move to building most of U-Boot with ARMv7 and only a small part with ARMv4T (for AVP) it should be as simple as possible.
This makes tegra2_start() into a simple function which either does AVP init or A9 init depending on which core is running it. Both cores now following the same init path, beginning at _start, and the special Tegra2 boot path code is no longer required.
Only two files need to be built for ARMv4T, and this is handled in the Tegra2 CPU Makefile.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/cpu/armv7/tegra2/Makefile | 5 +++ arch/arm/cpu/armv7/tegra2/ap20.c | 54 +++++++++++++++++++---------------- arch/arm/cpu/armv7/tegra2/ap20.h | 3 ++ 3 files changed, 37 insertions(+), 25 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f0dc2ff..955c3b6 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -23,6 +23,11 @@ # MA 02111-1307 USA #
+# The AVP is ARMv4T architecture so we must use special compiler +# flags for any startup files it might use. +CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t +CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t + include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o diff --git a/arch/arm/cpu/armv7/tegra2/ap20.c b/arch/arm/cpu/armv7/tegra2/ap20.c index 5cb4b1b..4c44bb3 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.c +++ b/arch/arm/cpu/armv7/tegra2/ap20.c @@ -31,7 +31,12 @@ #include <asm/arch/scu.h> #include <common.h>
-u32 s_first_boot = 1; +/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */ +static int ap20_cpu_is_cortexa9(void) +{ + u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0); + return id == (PG_UP_TAG_0_PID_CPU & 0xff); +}
void init_pllx(void) { @@ -283,38 +288,37 @@ void init_pmc_scratch(void) writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20); }
-void cpu_start(void) +void tegra2_start(void) { struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
- /* enable JTAG */ - writel(0xC0, &pmt->pmt_cfg_ctl); + /* If we are the AVP, start up the first Cortex-A9 */ + if (!ap20_cpu_is_cortexa9()) { + /* enable JTAG */ + writel(0xC0, &pmt->pmt_cfg_ctl);
- if (s_first_boot) { /* - * Need to set this before cold-booting, - * otherwise we'll end up in an infinite loop. - */ - s_first_boot = 0; - cold_boot(); + * If we are ARM7 - give it a different stack. We are about to + * start up the A9 which will want to use this one. + */ + asm volatile("ldr sp, =%c0\n" + : : "i"(AVP_EARLY_BOOT_STACK_LIMIT)); + + start_cpu((u32)_start); + halt_avp(); + /* not reached */ } -}
-void tegra2_start() -{ - if (s_first_boot) { - /* Init Debug UART Port (115200 8n1) */ - uart_init(); + /* Init PMC scratch memory */ + init_pmc_scratch();
- /* Init PMC scratch memory */ - init_pmc_scratch(); - } + enable_scu();
-#ifdef CONFIG_ENABLE_CORTEXA9 - /* take the mpcore out of reset */ - cpu_start(); + /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x41\n" + "mcr p15, 0, r0, c1, c0, 1\n");
- /* configure cache */ - cache_configure(); -#endif + /* FIXME: should have ap20's L2 disabled too? */ } diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h index 49fe340..1bb48d6 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.h +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -102,3 +102,6 @@ void uart_init(void); void udelay(unsigned long); void cold_boot(void); void cache_configure(void); + +/* This is the main entry into U-Boot, used by the Cortex-A9 */ +extern void _start(void);
Some SOCs have do not start up with their 'main' CPU. The first U-Boot code may then be executed with a CPU which does not have a CP15.
Here we split the initialization of CP15 into a separate call, and only do it if we detect an ARMv7 chip.
The test for ARMv7 cannot use CP15, since this may trigger an undefined instruction exception on an ARM7TDMI, so we check for a Q bit in the APSR instead.
An alternative to this is to make boards set CONFIG_SKIP_LOWLEVEL_INIT and then call cpu_init_cp15() later. However after much discussion on the U-Boot mailing list this was rejected as undesirable.
See: http://patchwork.ozlabs.org/patch/119621/
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v3: - Update comment and also make it match style - Fix cpu_init_cp15() name - Remove exporting of cpu_init_cp15() from start.S - Add test for ARMv7 CPU and skip CP15 init if not found
arch/arm/cpu/armv7/start.S | 45 ++++++++++++++++++++++++------------------- 1 files changed, 25 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index db8e9d2..528585f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -168,7 +168,23 @@ next: #endif /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT - bl cpu_init_crit + @ Try to set the Q bit in the APSR. If this fails, we are not ARMv7 + @ An ARM7TDMI will see APSR_nzcvq as CPSR_f (they are equivalent) + @ and we use that syntax to be kind to older tool chains + msr CPSR_f, #0x08000000 @ set Q bit + mrs r0, CPSR @ see if it is still there + tst r0, #0x08000000 + blne cpu_init_cp15 @ if so, we are ARMv7, so init it! + + msr CPSR_f, #0x00 @ clear Q bit + + /* + * Jump to board specific initialization... + * The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle + * wake up conditions. + */ + bl lowlevel_init @ go setup pll,mux,memory #endif
/* Set stackpointer in internal RAM to call board_init_f */ @@ -307,15 +323,14 @@ _board_init_r_ofs:
#ifndef CONFIG_SKIP_LOWLEVEL_INIT -/************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing +/* + * cpu_init_cp15 * - *************************************************************************/ -cpu_init_crit: + * Setup CP15 registers (cache, MMU, TLBs) to initial reset values. The MMU + * and D-cache are turned off. The I-cache is turned on unless + * CONFIG_SYS_ICACHE_OFF is defined. + */ +cpu_init_cp15: /* * Invalidate L1 I/D */ @@ -340,18 +355,8 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache #endif mcr p15, 0, r0, c1, c0, 0 - - /* - * Jump to board specific initialization... - * The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle - * wake up conditions. - */ - mov ip, lr @ persevere link reg across call - bl lowlevel_init @ go setup pll,mux,memory - mov lr, ip @ restore link mov pc, lr @ back to my caller -#endif +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SPL_BUILD /*
Since we have cache support built in we can remove Tegra's existing cache initialization code amd other related dead code.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v2: - Keep Tegra's config.mk file around so we can set the armv4t flags
Changes in v3: - Add lowlevel_init function back in (though it does nothing)
arch/arm/cpu/armv7/start.S | 12 --- arch/arm/cpu/armv7/tegra2/ap20.h | 7 +-- arch/arm/cpu/armv7/tegra2/board.c | 8 -- arch/arm/cpu/armv7/tegra2/config.mk | 3 - arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 115 +---------------------------- 5 files changed, 2 insertions(+), 143 deletions(-)
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 528585f..1794475 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,18 +81,6 @@ _end_vect: _TEXT_BASE: .word CONFIG_SYS_TEXT_BASE
-#ifdef CONFIG_TEGRA2 -/* - * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s). - * U-Boot runs on the AVP first, setting things up for the CPU (PLLs, - * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU - * to pick up its reset vector, which points here. - */ -.globl _armboot_start -_armboot_start: - .word _start -#endif - /* * These are defined in the board-specific linker script. */ diff --git a/arch/arm/cpu/armv7/tegra2/ap20.h b/arch/arm/cpu/armv7/tegra2/ap20.h index 1bb48d6..a4b4d73 100644 --- a/arch/arm/cpu/armv7/tegra2/ap20.h +++ b/arch/arm/cpu/armv7/tegra2/ap20.h @@ -95,13 +95,8 @@ #define HALT_COP_EVENT_IRQ_1 (1 << 11) #define HALT_COP_EVENT_FIQ_1 (1 << 9)
-/* Prototypes */ - +/* Start up the tegra2 SOC */ void tegra2_start(void); -void uart_init(void); -void udelay(unsigned long); -void cold_boot(void); -void cache_configure(void);
/* This is the main entry into U-Boot, used by the Cortex-A9 */ extern void _start(void); diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index 4530194..e6fe4fd 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -55,14 +55,6 @@ unsigned int query_sdram_size(void) } }
-void s_init(void) -{ -#ifndef CONFIG_ICACHE_OFF - icache_enable(); -#endif - invalidate_dcache(); -} - int dram_init(void) { unsigned long rs; diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk index f84fdc8..8f9bdc9 100644 --- a/arch/arm/cpu/armv7/tegra2/config.mk +++ b/arch/arm/cpu/armv7/tegra2/config.mk @@ -24,9 +24,6 @@ # MA 02111-1307 USA #
-# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI. -PLATFORM_CPPFLAGS += -march=armv4 - # Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this # file with compatible flags ifdef CONFIG_TEGRA2 diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S index f24a2ff..df1bb6e 100644 --- a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S +++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S @@ -26,14 +26,6 @@ #include <config.h> #include <version.h>
- -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file - -.global invalidate_dcache -invalidate_dcache: - mov pc, lr - .align 5 .global reset_cpu reset_cpu: @@ -50,110 +42,5 @@ rstctl:
.globl lowlevel_init lowlevel_init: - ldr sp, SRAM_STACK - str ip, [sp] - mov ip, lr - bl s_init @ go setup pll, mux & memory - ldr ip, [sp] - mov lr, ip - + @ Nothing to do here mov pc, lr @ back to arch calling code - - -.globl startup_cpu -startup_cpu: - @ Initialize the AVP, clocks, and memory controller - @ SDRAM is guaranteed to be on at this point - - ldr r0, =cold_boot @ R0 = reset vector for CPU - bl start_cpu @ start the CPU - - @ Transfer control to the AVP code - bl halt_avp - - @ Should never get here -_loop_forever2: - b _loop_forever2 - -.globl cache_configure -cache_configure: - stmdb r13!,{r14} - @ invalidate instruction cache - mov r1, #0 - mcr p15, 0, r1, c7, c5, 0 - - @ invalidate the i&d tlb entries - mcr p15, 0, r1, c8, c5, 0 - mcr p15, 0, r1, c8, c6, 0 - - @ enable instruction cache - mrc p15, 0, r1, c1, c0, 0 - orr r1, r1, #(1<<12) - mcr p15, 0, r1, c1, c0, 0 - - bl enable_scu - - @ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #0x41 - mcr p15, 0, r0, c1, c0, 1 - - @ Now flush the Dcache - mov r0, #0 - @ 256 cache lines - mov r1, #256 - -invalidate_loop: - add r1, r1, #-1 - mov r0, r1, lsl #5 - @ invalidate d-cache using line (way0) - mcr p15, 0, r0, c7, c6, 2 - - orr r2, r0, #(1<<30) - @ invalidate d-cache using line (way1) - mcr p15, 0, r2, c7, c6, 2 - - orr r2, r0, #(2<<30) - @ invalidate d-cache using line (way2) - mcr p15, 0, r2, c7, c6, 2 - - orr r2, r0, #(3<<30) - @ invalidate d-cache using line (way3) - mcr p15, 0, r2, c7, c6, 2 - cmp r1, #0 - bne invalidate_loop - - @ FIXME: should have ap20's L2 disabled too? -invalidate_done: - ldmia r13!,{pc} - -.globl cold_boot -cold_boot: - msr cpsr_c, #0xD3 - @ Check current processor: CPU or AVP? - @ If CPU, go to CPU boot code, else continue on AVP path - - ldr r0, =NV_PA_PG_UP_BASE - ldr r1, [r0] - ldr r2, =PG_UP_TAG_AVP - - @ are we the CPU? - ldr sp, CPU_STACK - cmp r1, r2 - @ yep, we are the CPU - bne _armboot_start - - @ AVP initialization follows this path - ldr sp, AVP_STACK - @ Init AVP and start CPU - b startup_cpu - - @ the literal pools origin - .ltorg - -SRAM_STACK: - .word LOW_LEVEL_SRAM_STACK -AVP_STACK: - .word EARLY_AVP_STACK -CPU_STACK: - .word EARLY_CPU_STACK
CONFIG_ENABLE_CORTEXA9 and CONFIG_SKIP_RELOCATE_UBOOT are not needed, so remove them. Also we don't need to skip low-level init anymore.
Signed-off-by: Simon Glass sjg@chromium.org ---
include/configs/tegra2-common.h | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index bdf7eab..8a0ae20 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */ -#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
#include <asm/arch/tegra2.h> /* get chip and board defs */
@@ -46,9 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_OF_LIBFDT /* enable passing of devicetree */
This was used by the AVP in early boot but is no longer used. Unless we plan to enable it somehow it is not needed. In any case we should try to use the ns16550 driver instead as it has the same code.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/serial/Makefile | 1 - drivers/serial/serial_tegra2.c | 77 ---------------------------------------- drivers/serial/serial_tegra2.h | 29 --------------- 3 files changed, 0 insertions(+), 107 deletions(-) delete mode 100644 drivers/serial/serial_tegra2.c delete mode 100644 drivers/serial/serial_tegra2.h
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6309549..616b857 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -55,7 +55,6 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o -COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_tegra2.c b/drivers/serial/serial_tegra2.c deleted file mode 100644 index 8ff34ea..0000000 --- a/drivers/serial/serial_tegra2.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <ns16550.h> -#include <asm/io.h> -#include <asm/arch/tegra2.h> -#include "serial_tegra2.h" - -static void setup_uart(struct uart_ctlr *u) -{ - u32 reg; - - /* Prepare the divisor value */ - reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16; - - /* Set up UART parameters */ - writel(UART_LCR_DLAB, &u->uart_lcr); - writel(reg, &u->uart_thr_dlab_0); - writel(0, &u->uart_ier_dlab_0); - writel(0, &u->uart_lcr); /* clear DLAB */ - writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \ - UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr); - writel(0, &u->uart_ier_dlab_0); - writel(UART_LCR_WLS_8, &u->uart_lcr); /* 8N1 */ - writel(UART_MCR_RTS, &u->uart_mcr); - writel(0, &u->uart_msr); - writel(0, &u->uart_spr); - writel(0, &u->uart_irda_csr); - writel(0, &u->uart_asr); - writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr); - - /* Flush any old characters out of the RX FIFO */ - reg = readl(&u->uart_lsr); - - while (reg & UART_LSR_DR) { - reg = readl(&u->uart_thr_dlab_0); - reg = readl(&u->uart_lsr); - } -} - -/* - * Routine: uart_init - * Description: init the UART clocks, muxes, and baudrate/parity/etc. - */ -void uart_init(void) -{ - struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE; -#if defined(CONFIG_TEGRA2_ENABLE_UARTD) - setup_uart(uart); -#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ -#if defined(CONFIG_TEGRA2_ENABLE_UARTA) - uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE; - - setup_uart(uart); -#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ -} diff --git a/drivers/serial/serial_tegra2.h b/drivers/serial/serial_tegra2.h deleted file mode 100644 index 5704800..0000000 --- a/drivers/serial/serial_tegra2.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation <www.nvidia.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SERIAL_TEGRA_H_ -#define _SERIAL_TEGRA_H_ - -#include <asm/arch/uart.h> - -#endif /* _SERIAL_TEGRA_H_ */
This message is not required, since it is followed by an 'official' U-Boot message.
U-Boot 2011.03-00048-gd7cb0d3 (May 11 2011 - 17:17:23)
TEGRA2 Board: NVIDIA Seaboard dynamic ram_size = 1073741824 DRAM: 1 GiB
becomes:
TEGRA2 Board: NVIDIA Seaboard DRAM: 1 GiB
This is a separate commit since it changes behavior.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/cpu/armv7/tegra2/board.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index e6fe4fd..fbf189a 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -65,10 +65,8 @@ int dram_init(void)
/* Now check it dynamically */ rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size); - if (rs) { - printf("dynamic ram_size = %lu\n", rs); + if (rs) gd->bd->bi_dram[0].size = gd->ram_size = rs; - } return 0; }
In board_init_f() the gd->bd pointer is not valid when dram_init() is called. This only avoids dying because DRAM is at zero on Tegra2. The common ARM routine sets up the banks in the same way anyway, so we can just remove this code.
Signed-off-by: Simon Glass sjg@chromium.org --- Changes in v3: - Remove later CP15 init in board.c since this is not needed now - Rebase against master (due to CONFIG_SYS_CACHELINE_SIZE series)
arch/arm/cpu/armv7/tegra2/board.c | 10 +--------- 1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c index fbf189a..59dce8f 100644 --- a/arch/arm/cpu/armv7/tegra2/board.c +++ b/arch/arm/cpu/armv7/tegra2/board.c @@ -57,16 +57,8 @@ unsigned int query_sdram_size(void)
int dram_init(void) { - unsigned long rs; - /* We do not initialise DRAM here. We just query the size */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size(); - - /* Now check it dynamically */ - rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size); - if (rs) - gd->bd->bi_dram[0].size = gd->ram_size = rs; + gd->ram_size = query_sdram_size(); return 0; }
things generally look fine, but i don't know anything about low level SoC init, so i can't contribute much there -mike
Hi Mike,
On Thu, Nov 3, 2011 at 7:39 PM, Mike Frysinger vapier@gentoo.org wrote:
things generally look fine, but i don't know anything about low level SoC init, so i can't contribute much there -mike
Thanks for looking at them. Mostly this series is just trying to simplify things.
Regards, Simon
participants (2)
-
Mike Frysinger -
Simon Glass