[U-Boot] [PATCH v2 0/4] Exynos5: Fix warnings and enrich clock_get_periph_rate

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Akshay Saraswat

15 Jan 2015 15 Jan '15

2:31 p.m.

This patch series does following changes - 1. Removing compiler warnings for clock_get_periph_rate. 2. Adding and enabling support for Exynos542x in clock_get_periph_rate. 3. Replacing peripheral specific function calls with clock_get_periph_rate. 4. Remove code from clocks file which became useless due to introduction of clock_get_periph_rate.

Changes since v1: - Added 2 new patches.

Akshay Saraswat (6): Exynos5: Fix compiler warnings due to clock_get_periph_rate Exynos542x: Move exynos5420_get_pll_clk up and rename Exynos542x: Add and enable get_periph_rate support Exynos5: Fix exynos5_get_periph_rate calculations Exynos5: Use clock_get_periph_rate generic API Exynos5: Remove dead code for fetching clocks

arch/arm/cpu/armv7/exynos/clock.c | 574 ++++++++++++++++----------------- arch/arm/include/asm/arch-exynos/clk.h | 5 +- 2 files changed, 274 insertions(+), 305 deletions(-)

-- 1.9.1

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Akshay Saraswat

15 Jan 15 Jan

2:31 p.m.

New subject: [U-Boot] [PATCH v2 1/6] Exynos5: Fix compiler warnings due to clock_get_periph_rate

Apparently, members of clk_bit_info array do not map correctly to the members of enum periph_id. This mapping got broken after we changed periph_id(s) to reflect interrupt number instead of their position in a sequence. This patch intends to fix above mentioned issue.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v1: - Removed exynos5_bit_info array name.

arch/arm/cpu/armv7/exynos/clock.c | 81 ++++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 31 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b31c13b..519928c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -20,42 +20,49 @@ * positions of the peripheral clocks of the src and div registers */ struct clk_bit_info { + enum periph_id id; int8_t src_bit; int8_t div_bit; int8_t prediv_bit; };

-/* src_bit div_bit prediv_bit */ +/* periph_id src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[] = { - {0, 0, -1}, - {4, 4, -1}, - {8, 8, -1}, - {12, 12, -1}, - {0, 0, 8}, - {4, 16, 24}, - {8, 0, 8}, - {12, 16, 24}, - {-1, -1, -1}, - {16, 0, 8}, - {20, 16, 24}, - {24, 0, 8}, - {0, 0, 4}, - {4, 12, 16}, - {-1, -1, -1}, - {-1, -1, -1}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {-1, 24, 0}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, - {24, 0, -1}, + {PERIPH_ID_UART0, 0, 0, -1}, + {PERIPH_ID_UART1, 4, 4, -1}, + {PERIPH_ID_UART2, 8, 8, -1}, + {PERIPH_ID_UART3, 12, 12, -1}, + {PERIPH_ID_I2C0, -1, 24, 0}, + {PERIPH_ID_I2C1, -1, 24, 0}, + {PERIPH_ID_I2C2, -1, 24, 0}, + {PERIPH_ID_I2C3, -1, 24, 0}, + {PERIPH_ID_I2C4, -1, 24, 0}, + {PERIPH_ID_I2C5, -1, 24, 0}, + {PERIPH_ID_I2C6, -1, 24, 0}, + {PERIPH_ID_I2C7, -1, 24, 0}, + {PERIPH_ID_SPI0, 16, 0, 8}, + {PERIPH_ID_SPI1, 20, 16, 24}, + {PERIPH_ID_SPI2, 24, 0, 8}, + {PERIPH_ID_SDMMC0, 0, 0, 8}, + {PERIPH_ID_SDMMC1, 4, 16, 24}, + {PERIPH_ID_SDMMC2, 8, 0, 8}, + {PERIPH_ID_SDMMC3, 12, 16, 24}, + {PERIPH_ID_I2C8, -1, -1, -1}, + {PERIPH_ID_I2C9, -1, -1, -1}, + {PERIPH_ID_I2S0, 0, 0, 4}, + {PERIPH_ID_I2S1, 4, 12, 16}, + {PERIPH_ID_SROMC, -1, -1, -1}, + {PERIPH_ID_SPI3, 0, 0, 4}, + {PERIPH_ID_SPI4, 4, 12, 16}, + {PERIPH_ID_SDMMC4, 16, 0, 8}, + {PERIPH_ID_PWM0, 24, 0, -1}, + {PERIPH_ID_PWM1, 24, 0, -1}, + {PERIPH_ID_PWM2, 24, 0, -1}, + {PERIPH_ID_PWM3, 24, 0, -1}, + {PERIPH_ID_PWM4, 24, 0, -1}, + {PERIPH_ID_I2C10, -1, -1, -1}, + + {PERIPH_ID_NONE, -1, -1, -1}, };

/* Epll Clock division values to achive different frequency output */ @@ -260,9 +267,21 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; }

+static struct clk_bit_info *get_clk_bit_info(int peripheral) +{ + int i; + + for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) { + if (clk_bit_info[i].id == peripheral) + break; + } + + return &clk_bit_info[i]; +} + static unsigned long exynos5_get_periph_rate(int peripheral) { - struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); unsigned long sclk, sub_clk; unsigned int src, div, sub_div; struct exynos5_clock *clk =

-- 1.9.1

Jaehoon Chung

16 Jan 16 Jan

3:49 a.m.

New subject: [U-Boot] [PATCH v2 1/6] Exynos5: Fix compiler warnings due to clock_get_periph_rate

Hi,

On 01/15/2015 10:31 PM, Akshay Saraswat wrote:

...

Apparently, members of clk_bit_info array do not map correctly to the members of enum periph_id. This mapping got broken after we changed periph_id(s) to reflect interrupt number instead of their position in a sequence. This patch intends to fix above mentioned issue.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com

Changes since v1:

Removed exynos5_bit_info array name.

arch/arm/cpu/armv7/exynos/clock.c | 81 ++++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 31 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index b31c13b..519928c 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -20,42 +20,49 @@

positions of the peripheral clocks of the src and div registers

*/ struct clk_bit_info {

enum periph_id id; int8_t src_bit; int8_t div_bit; int8_t prediv_bit;

};

-/* src_bit div_bit prediv_bit */ +/* periph_id src_bit div_bit prediv_bit */ static struct clk_bit_info clk_bit_info[] = {

{0, 0, -1},

{4, 4, -1},

{8, 8, -1},

{12, 12, -1},

{0, 0, 8},

{4, 16, 24},

{8, 0, 8},

{12, 16, 24},

{-1, -1, -1},

{16, 0, 8},

{20, 16, 24},

{24, 0, 8},

{0, 0, 4},

{4, 12, 16},

{-1, -1, -1},

{-1, -1, -1},

{-1, 24, 0},

{-1, 24, 0},

{-1, 24, 0},

{-1, 24, 0},

{-1, 24, 0},

{-1, 24, 0},

{-1, 24, 0},

{-1, 24, 0},

{24, 0, -1},

{24, 0, -1},

{24, 0, -1},

{24, 0, -1},

{24, 0, -1},

{PERIPH_ID_UART0, 0, 0, -1},

{PERIPH_ID_UART1, 4, 4, -1},

{PERIPH_ID_UART2, 8, 8, -1},

{PERIPH_ID_UART3, 12, 12, -1},

{PERIPH_ID_I2C0, -1, 24, 0},

{PERIPH_ID_I2C1, -1, 24, 0},

{PERIPH_ID_I2C2, -1, 24, 0},

{PERIPH_ID_I2C3, -1, 24, 0},

{PERIPH_ID_I2C4, -1, 24, 0},

{PERIPH_ID_I2C5, -1, 24, 0},

{PERIPH_ID_I2C6, -1, 24, 0},

{PERIPH_ID_I2C7, -1, 24, 0},

{PERIPH_ID_SPI0, 16, 0, 8},

{PERIPH_ID_SPI1, 20, 16, 24},

{PERIPH_ID_SPI2, 24, 0, 8},

{PERIPH_ID_SDMMC0, 0, 0, 8},

{PERIPH_ID_SDMMC1, 4, 16, 24},

{PERIPH_ID_SDMMC2, 8, 0, 8},

{PERIPH_ID_SDMMC3, 12, 16, 24},

{PERIPH_ID_I2C8, -1, -1, -1},

{PERIPH_ID_I2C9, -1, -1, -1},

{PERIPH_ID_I2S0, 0, 0, 4},

{PERIPH_ID_I2S1, 4, 12, 16},

{PERIPH_ID_SROMC, -1, -1, -1},

{PERIPH_ID_SPI3, 0, 0, 4},

{PERIPH_ID_SPI4, 4, 12, 16},

{PERIPH_ID_SDMMC4, 16, 0, 8},

{PERIPH_ID_PWM0, 24, 0, -1},

{PERIPH_ID_PWM1, 24, 0, -1},

{PERIPH_ID_PWM2, 24, 0, -1},

{PERIPH_ID_PWM3, 24, 0, -1},

{PERIPH_ID_PWM4, 24, 0, -1},

{PERIPH_ID_I2C10, -1, -1, -1},

{PERIPH_ID_NONE, -1, -1, -1},

};

/* Epll Clock division values to achive different frequency output */ @@ -260,9 +267,21 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; }

+static struct clk_bit_info *get_clk_bit_info(int peripheral) +{
int i;

for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
if (clk_bit_info[i].id == peripheral)
	break;
}

If don't match anything, it gets wrong bit_info. I think good that print the warning message or other.

Best Regards, Jaehoon Chung

...

return &clk_bit_info[i];

+}

static unsigned long exynos5_get_periph_rate(int peripheral) {

struct clk_bit_info *bit_info = &clk_bit_info[peripheral];

struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); unsigned long sclk, sub_clk; unsigned int src, div, sub_div; struct exynos5_clock *clk =

Akshay Saraswat

15 Jan 15 Jan

2:31 p.m.

New subject: [U-Boot] [PATCH v2 2/6] Exynos542x: Move exynos5420_get_pll_clk up and rename

Moving exynos5420_get_pll_clk function definition up in the code to keep it together with rest of SoC_get_pll_clk functions. This makes code more legible and also removes the need of declaration when called before the position of definition in code. Also, renaming exynos5420_get_pll_clk to exynos542x_get_pll_clk because it is being used for both Exynos 5420 and 5800.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v1: - New patch.

arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 519928c..6a1b05f 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -267,6 +267,46 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; }

+/* exynos5420: return pll clock frequency */ +static unsigned long exynos542x_get_pll_clk(int pllreg) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + case BPLL: + r = readl(&clk->bpll_con0); + break; + case RPLL: + r = readl(&clk->rpll_con0); + k = readl(&clk->rpll_con1); + break; + case SPLL: + r = readl(&clk->spll_con0); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + static struct clk_bit_info *get_clk_bit_info(int peripheral) { int i; @@ -383,46 +423,6 @@ unsigned long clock_get_periph_rate(int peripheral) return 0; }

-/* exynos5420: return pll clock frequency */ -static unsigned long exynos5420_get_pll_clk(int pllreg) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long r, k = 0; - - switch (pllreg) { - case APLL: - r = readl(&clk->apll_con0); - break; - case MPLL: - r = readl(&clk->mpll_con0); - break; - case EPLL: - r = readl(&clk->epll_con0); - k = readl(&clk->epll_con1); - break; - case VPLL: - r = readl(&clk->vpll_con0); - k = readl(&clk->vpll_con1); - break; - case BPLL: - r = readl(&clk->bpll_con0); - break; - case RPLL: - r = readl(&clk->rpll_con0); - k = readl(&clk->rpll_con1); - break; - case SPLL: - r = readl(&clk->spll_con0); - break; - default: - printf("Unsupported PLL (%d)\n", pllreg); - return 0; - } - - return exynos_get_pll_clk(pllreg, r, k); -} - /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { @@ -1604,7 +1604,7 @@ unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) { if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_pll_clk(pllreg); + return exynos542x_get_pll_clk(pllreg); return exynos5_get_pll_clk(pllreg); } else { if (proid_is_exynos4412())

-- 1.9.1

Joonyoung Shim

16 Jan 16 Jan

3:47 a.m.

New subject: [U-Boot] [PATCH v2 2/6] Exynos542x: Move exynos5420_get_pll_clk up and rename

Hi,

On 01/15/2015 10:31 PM, Akshay Saraswat wrote:

...

Moving exynos5420_get_pll_clk function definition up in the code to keep it together with rest of SoC_get_pll_clk functions. This makes code more legible and also removes the need of declaration when called before the position of definition in code. Also, renaming exynos5420_get_pll_clk to exynos542x_get_pll_clk because it is being used for both Exynos 5420 and 5800.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com

Changes since v1:

New patch.

arch/arm/cpu/armv7/exynos/clock.c | 82 +++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 519928c..6a1b05f 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -267,6 +267,46 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; }

+/* exynos5420: return pll clock frequency */

exynos5420 -> exynos542x

Thanks.

Akshay Saraswat

15 Jan 15 Jan

2:31 p.m.

New subject: [U-Boot] [PATCH v2 3/6] Exynos542x: Add and enable get_periph_rate support

We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v1: - Changes suuport -> support in commit message. - Removed position change of exynos5420_get_pll_clk. - Removed #ifdef.

arch/arm/cpu/armv7/exynos/clock.c | 151 +++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 5 +- 2 files changed, 148 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 6a1b05f..1ef4f49 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -27,7 +27,7 @@ struct clk_bit_info { };

/* periph_id src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[] = { +static struct clk_bit_info exynos5_bit_info[] = { {PERIPH_ID_UART0, 0, 0, -1}, {PERIPH_ID_UART1, 4, 4, -1}, {PERIPH_ID_UART2, 8, 8, -1}, @@ -65,6 +65,44 @@ static struct clk_bit_info clk_bit_info[] = { {PERIPH_ID_NONE, -1, -1, -1}, };

+static struct clk_bit_info exynos542x_bit_info[] = { + {PERIPH_ID_UART0, 4, 8, -1}, + {PERIPH_ID_UART1, 8, 12, -1}, + {PERIPH_ID_UART2, 12, 16, -1}, + {PERIPH_ID_UART3, 16, 20, -1}, + {PERIPH_ID_I2C0, -1, 8, -1}, + {PERIPH_ID_I2C1, -1, 8, -1}, + {PERIPH_ID_I2C2, -1, 8, -1}, + {PERIPH_ID_I2C3, -1, 8, -1}, + {PERIPH_ID_I2C4, -1, 8, -1}, + {PERIPH_ID_I2C5, -1, 8, -1}, + {PERIPH_ID_I2C6, -1, 8, -1}, + {PERIPH_ID_I2C7, -1, 8, -1}, + {PERIPH_ID_SPI0, 20, 20, 8}, + {PERIPH_ID_SPI1, 24, 24, 16}, + {PERIPH_ID_SPI2, 28, 28, 24}, + {PERIPH_ID_SDMMC0, 0, 0, -1}, + {PERIPH_ID_SDMMC1, 4, 10, -1}, + {PERIPH_ID_SDMMC2, 8, 20, -1}, + {PERIPH_ID_SDMMC3, -1, -1, -1}, + {PERIPH_ID_I2C8, -1, 8, -1}, + {PERIPH_ID_I2C9, -1, 8, -1}, + {PERIPH_ID_I2S0, 0, 0, 4}, + {PERIPH_ID_I2S1, 4, 12, 16}, + {PERIPH_ID_SROMC, -1, -1, -1}, + {PERIPH_ID_SPI3, 12, 16, 0}, + {PERIPH_ID_SPI4, 16, 20, 8}, + {PERIPH_ID_SDMMC4, 16, 0, 8}, + {PERIPH_ID_PWM0, 24, 28, -1}, + {PERIPH_ID_PWM1, 24, 28, -1}, + {PERIPH_ID_PWM2, 24, 28, -1}, + {PERIPH_ID_PWM3, 24, 28, -1}, + {PERIPH_ID_PWM4, 24, 28, -1}, + {PERIPH_ID_I2C10, -1, 8, -1}, + + {PERIPH_ID_NONE, -1, -1, -1}, +}; + /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -310,13 +348,19 @@ static unsigned long exynos542x_get_pll_clk(int pllreg) static struct clk_bit_info *get_clk_bit_info(int peripheral) { int i; + struct clk_bit_info *info;

- for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) { - if (clk_bit_info[i].id == peripheral) + if (proid_is_exynos5420() || proid_is_exynos5800()) + info = exynos542x_bit_info; + else + info = exynos5_bit_info; + + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { + if (info[i].id == peripheral) break; }

- return &clk_bit_info[i]; + return &info[i]; }

static unsigned long exynos5_get_periph_rate(int peripheral) @@ -415,12 +459,107 @@ static unsigned long exynos5_get_periph_rate(int peripheral) return sub_clk; }

+static unsigned long exynos542x_get_periph_rate(int peripheral) +{ + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); + unsigned long sclk, sub_clk; + unsigned int src, div, sub_div = 0; + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); + break; + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + sub_div = readl(&clk->div_peric4); + break; + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->src_isp); + div = readl(&clk->div_isp1); + sub_div = readl(&clk->div_isp1); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + case PERIPH_ID_I2C8: + case PERIPH_ID_I2C9: + case PERIPH_ID_I2C10: + sclk = exynos542x_get_pll_clk(MPLL); + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) + & 0x7) + 1; + return sclk / sub_div; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS542x_SRC_MPLL: + sclk = exynos542x_get_pll_clk(MPLL); + break; + case EXYNOS542x_SRC_EPLL: + sclk = exynos542x_get_pll_clk(EPLL); + break; + case EXYNOS542x_SRC_RPLL: + sclk = exynos542x_get_pll_clk(RPLL); + break; + default: + return 0; + } + + /* Ratio clock division for this peripheral */ + div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (div + 1); + + if (bit_info->prediv_bit >= 0) { + sub_div = (sub_div >> bit_info->prediv_bit) & 0xff; + return sub_clk / (sub_div + 1); + } + + return sub_clk; +} + unsigned long clock_get_periph_rate(int peripheral) { - if (cpu_is_exynos5()) + if (cpu_is_exynos5()) { + if (proid_is_exynos5420() || proid_is_exynos5800()) + return exynos542x_get_periph_rate(peripheral); return exynos5_get_periph_rate(peripheral); - else + } else { return 0; + } }

/* exynos4: return ARM clock frequency */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..606b3ef 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -23,8 +23,9 @@ #define SET_RATIO(x, y) ((y & 0xf) << (x << 4))

enum pll_src_bit { - EXYNOS_SRC_MPLL = 6, - EXYNOS_SRC_EPLL, + EXYNOS542x_SRC_MPLL = 3, + EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6, + EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, EXYNOS_SRC_VPLL, };

-- 1.9.1

Joonyoung Shim

16 Jan 16 Jan

5:58 a.m.

New subject: [U-Boot] [PATCH v2 3/6] Exynos542x: Add and enable get_periph_rate support

Hi,

On 01/15/2015 10:31 PM, Akshay Saraswat wrote:

...

We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com

Changes since v1:

Changes suuport -> support in commit message.

Removed position change of exynos5420_get_pll_clk.

Removed #ifdef.

arch/arm/cpu/armv7/exynos/clock.c | 151 +++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 5 +- 2 files changed, 148 insertions(+), 8 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 6a1b05f..1ef4f49 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -27,7 +27,7 @@ struct clk_bit_info { };

/* periph_id src_bit div_bit prediv_bit */ -static struct clk_bit_info clk_bit_info[] = { +static struct clk_bit_info exynos5_bit_info[] = { {PERIPH_ID_UART0, 0, 0, -1}, {PERIPH_ID_UART1, 4, 4, -1}, {PERIPH_ID_UART2, 8, 8, -1}, @@ -65,6 +65,44 @@ static struct clk_bit_info clk_bit_info[] = { {PERIPH_ID_NONE, -1, -1, -1}, };

+static struct clk_bit_info exynos542x_bit_info[] = {

{PERIPH_ID_UART0, 4, 8, -1},

{PERIPH_ID_UART1, 8, 12, -1},

{PERIPH_ID_UART2, 12, 16, -1},

{PERIPH_ID_UART3, 16, 20, -1},

{PERIPH_ID_I2C0, -1, 8, -1},

{PERIPH_ID_I2C1, -1, 8, -1},

{PERIPH_ID_I2C2, -1, 8, -1},

{PERIPH_ID_I2C3, -1, 8, -1},

{PERIPH_ID_I2C4, -1, 8, -1},

{PERIPH_ID_I2C5, -1, 8, -1},

{PERIPH_ID_I2C6, -1, 8, -1},

{PERIPH_ID_I2C7, -1, 8, -1},

{PERIPH_ID_SPI0, 20, 20, 8},

{PERIPH_ID_SPI1, 24, 24, 16},

{PERIPH_ID_SPI2, 28, 28, 24},

{PERIPH_ID_SDMMC0, 0, 0, -1},

{PERIPH_ID_SDMMC1, 4, 10, -1},

{PERIPH_ID_SDMMC2, 8, 20, -1},

{PERIPH_ID_SDMMC3, -1, -1, -1},

{PERIPH_ID_I2C8, -1, 8, -1},

{PERIPH_ID_I2C9, -1, 8, -1},

{PERIPH_ID_I2S0, 0, 0, 4},

{PERIPH_ID_I2S1, 4, 12, 16},

{PERIPH_ID_SROMC, -1, -1, -1},

{PERIPH_ID_SPI3, 12, 16, 0},

{PERIPH_ID_SPI4, 16, 20, 8},

{PERIPH_ID_SDMMC4, 16, 0, 8},

{PERIPH_ID_PWM0, 24, 28, -1},

{PERIPH_ID_PWM1, 24, 28, -1},

{PERIPH_ID_PWM2, 24, 28, -1},

{PERIPH_ID_PWM3, 24, 28, -1},

{PERIPH_ID_PWM4, 24, 28, -1},

{PERIPH_ID_I2C10, -1, 8, -1},

{PERIPH_ID_NONE, -1, -1, -1},

+};

/* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -310,13 +348,19 @@ static unsigned long exynos542x_get_pll_clk(int pllreg) static struct clk_bit_info *get_clk_bit_info(int peripheral) { int i;

struct clk_bit_info *info;
for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) {
if (clk_bit_info[i].id == peripheral)
if (proid_is_exynos5420() || proid_is_exynos5800())
info = exynos542x_bit_info;
else
info = exynos5_bit_info;
for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
if (info[i].id == peripheral)
break;
}
return &clk_bit_info[i];

return &info[i];

}

static unsigned long exynos5_get_periph_rate(int peripheral) @@ -415,12 +459,107 @@ static unsigned long exynos5_get_periph_rate(int peripheral) return sub_clk; }

+static unsigned long exynos542x_get_periph_rate(int peripheral) +{
struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);

unsigned long sclk, sub_clk;

unsigned int src, div, sub_div = 0;

struct exynos5420_clock *clk =
	(struct exynos5420_clock *)samsung_get_base_clock();
switch (peripheral) {

case PERIPH_ID_UART0:

case PERIPH_ID_UART1:

case PERIPH_ID_UART2:

case PERIPH_ID_UART3:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
case PERIPH_ID_PWM0:

case PERIPH_ID_PWM1:

case PERIPH_ID_PWM2:

case PERIPH_ID_PWM3:

case PERIPH_ID_PWM4:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;

UARTx and PWMx use same register, so you can remove duplicated codes.

...

case PERIPH_ID_SPI0:

case PERIPH_ID_SPI1:

case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric1);
sub_div = readl(&clk->div_peric4);
break;
case PERIPH_ID_SPI3:

case PERIPH_ID_SPI4:
src = readl(&clk->src_isp);
div = readl(&clk->div_isp1);
sub_div = readl(&clk->div_isp1);
break;
case PERIPH_ID_SDMMC0:

case PERIPH_ID_SDMMC1:

case PERIPH_ID_SDMMC2:

case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_I2C0:

case PERIPH_ID_I2C1:

case PERIPH_ID_I2C2:

case PERIPH_ID_I2C3:

case PERIPH_ID_I2C4:

case PERIPH_ID_I2C5:

case PERIPH_ID_I2C6:

case PERIPH_ID_I2C7:

case PERIPH_ID_I2C8:

case PERIPH_ID_I2C9:

case PERIPH_ID_I2C10:
sclk = exynos542x_get_pll_clk(MPLL);
sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
						& 0x7) + 1;
return sclk / sub_div;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};

src = (src >> bit_info->src_bit) & 0xf;

switch (src) {

case EXYNOS542x_SRC_MPLL:
sclk = exynos542x_get_pll_clk(MPLL);
break;
case EXYNOS542x_SRC_EPLL:
sclk = exynos542x_get_pll_clk(EPLL);
break;
case EXYNOS542x_SRC_RPLL:
sclk = exynos542x_get_pll_clk(RPLL);
break;
default:
return 0;
}

/* Ratio clock division for this peripheral */

div = (div >> bit_info->div_bit) & 0xf;

sub_clk = sclk / (div + 1);

if (bit_info->prediv_bit >= 0) {
sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (sub_div + 1);
}

return sub_clk;
+}

unsigned long clock_get_periph_rate(int peripheral) {

if (cpu_is_exynos5())
if (cpu_is_exynos5()) {
if (proid_is_exynos5420() || proid_is_exynos5800())
	return exynos542x_get_periph_rate(peripheral);
return exynos5_get_periph_rate(peripheral);
else

} else { return 0;

}

}

/* exynos4: return ARM clock frequency */ diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..606b3ef 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -23,8 +23,9 @@ #define SET_RATIO(x, y) ((y & 0xf) << (x << 4))

enum pll_src_bit {

EXYNOS_SRC_MPLL = 6,

EXYNOS_SRC_EPLL,

EXYNOS542x_SRC_MPLL = 3,

EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6,

EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, EXYNOS_SRC_VPLL,

};

Could you use one item by one line like below?

diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..da9bfcd 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -26,6 +26,9 @@ enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, EXYNOS_SRC_VPLL, + EXYNOS542x_SRC_MPLL = 3, + EXYNOS542x_SRC_EPLL = 6, + EXYNOS542x_SRC_RPLL, };

unsigned long get_pll_clk(int pllreg);

Thanks.

Joonyoung Shim

6:10 a.m.

New subject: [U-Boot] [PATCH v2 3/6] Exynos542x: Add and enable get_periph_rate support

Hi,

On 01/16/2015 01:58 PM, Joonyoung Shim wrote:

...

Hi,

On 01/15/2015 10:31 PM, Akshay Saraswat wrote:

...
We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com

Changes since v1:

Changes suuport -> support in commit message.

Removed position change of exynos5420_get_pll_clk.

Removed #ifdef.

arch/arm/cpu/armv7/exynos/clock.c | 151 +++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-exynos/clk.h | 5 +- 2 files changed, 148 insertions(+), 8 deletions(-)

[snip]

...

...
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..606b3ef 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -23,8 +23,9 @@ #define SET_RATIO(x, y) ((y & 0xf) << (x << 4))

enum pll_src_bit {

EXYNOS_SRC_MPLL = 6,

EXYNOS_SRC_EPLL,

EXYNOS542x_SRC_MPLL = 3,

EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6,

EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, EXYNOS_SRC_VPLL,

};

CC arch/arm/cpu/armv7/exynos/clock.o In file included from arch/arm/cpu/armv7/exynos/clock.c:11:0: ./arch/arm/include/asm/arch/clk.h:27:20: error: ‘EXYNOS542x_SRC_EPLL’ undeclared here (not in a function) EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6, ^ ./arch/arm/include/asm/arch/clk.h:28:20: error: ‘EXYNOS542x_SRC_RPLL’ undeclared here (not in a function) EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, ^ make[2]: *** [arch/arm/cpu/armv7/exynos/clock.o] Error 1 make[1]: *** [arch/arm/cpu/armv7/exynos] Error 2 make: *** [arch/arm/cpu/armv7] Error 2

Thanks.

...

Could you use one item by one line like below?

diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..da9bfcd 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -26,6 +26,9 @@ enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, EXYNOS_SRC_VPLL,

EXYNOS542x_SRC_MPLL = 3,

EXYNOS542x_SRC_EPLL = 6,

EXYNOS542x_SRC_RPLL,

};

unsigned long get_pll_clk(int pllreg);

Thanks. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

Akshay Saraswat

15 Jan 15 Jan

2:31 p.m.

New subject: [U-Boot] [PATCH v2 4/6] Exynos5: Fix exynos5_get_periph_rate calculations

exynos5_get_periph_rate function reads incorrect div for SDMMC2 & 3. It also reads prediv and does division only for SDMMC0 & 2 when actually various other peripherals need that. Adding changes to fix these mistakes in periph rate calculation.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v1: - New patch.

arch/arm/cpu/armv7/exynos/clock.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 1ef4f49..a43e5af 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -406,10 +406,13 @@ static unsigned long exynos5_get_periph_rate(int peripheral) break; case PERIPH_ID_SDMMC0: case PERIPH_ID_SDMMC1: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: src = readl(&clk->src_fsys); - div = readl(&clk->div_fsys1); + div = readl(&clk->div_fsys2); break; case PERIPH_ID_I2C0: case PERIPH_ID_I2C1: @@ -450,8 +453,7 @@ static unsigned long exynos5_get_periph_rate(int peripheral) sub_div = (div >> bit_info->div_bit) & 0xf; sub_clk = sclk / (sub_div + 1);

- /* Pre-ratio clock division for SDMMC0 and 2 */ - if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + if (bit_info->prediv_bit >= 0) { div = (div >> bit_info->prediv_bit) & 0xff; return sub_clk / (div + 1); }

-- 1.9.1

Akshay Saraswat

2:31 p.m.

New subject: [U-Boot] [PATCH v2 5/6] Exynos5: Use clock_get_periph_rate generic API

Replacing SoC and peripheral specific function calls with generic clock_get_periph_rate calls to get the peripheral clocks.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v1: - Separated exynos5_get_periph_rate fixes into another patch.

arch/arm/cpu/armv7/exynos/clock.c | 52 ++++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 9 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index a43e5af..191f794 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1768,7 +1768,7 @@ unsigned long get_arm_clk(void) unsigned long get_i2c_clk(void) { if (cpu_is_exynos5()) { - return exynos5_get_i2c_clk(); + return clock_get_periph_rate(PERIPH_ID_I2C0); } else if (cpu_is_exynos4()) { return exynos4_get_i2c_clk(); } else { @@ -1780,8 +1780,6 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_pwm_clk(); return clock_get_periph_rate(PERIPH_ID_PWM0); } else { if (proid_is_exynos4412()) @@ -1792,10 +1790,28 @@ unsigned long get_pwm_clk(void)

unsigned long get_uart_clk(int dev_index) { + enum periph_id id; + + switch (dev_index) { + case 0: + id = PERIPH_ID_UART0; + break; + case 1: + id = PERIPH_ID_UART1; + break; + case 2: + id = PERIPH_ID_UART2; + break; + case 3: + id = PERIPH_ID_UART3; + break; + default: + debug("%s: invalid UART index %d", __func__, dev_index); + return -1; + } + if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_uart_clk(dev_index); - return exynos5_get_uart_clk(dev_index); + return clock_get_periph_rate(id); } else { if (proid_is_exynos4412()) return exynos4x12_get_uart_clk(dev_index); @@ -1805,10 +1821,28 @@ unsigned long get_uart_clk(int dev_index)

unsigned long get_mmc_clk(int dev_index) { + enum periph_id id; + + switch (dev_index) { + case 0: + id = PERIPH_ID_SDMMC0; + break; + case 1: + id = PERIPH_ID_SDMMC1; + break; + case 2: + id = PERIPH_ID_SDMMC2; + break; + case 3: + id = PERIPH_ID_SDMMC3; + break; + default: + debug("%s: invalid MMC index %d", __func__, dev_index); + return -1; + } + if (cpu_is_exynos5()) { - if (proid_is_exynos5420() || proid_is_exynos5800()) - return exynos5420_get_mmc_clk(dev_index); - return exynos5_get_mmc_clk(dev_index); + return clock_get_periph_rate(id); } else { return exynos4_get_mmc_clk(dev_index); }

-- 1.9.1

Akshay Saraswat

2:31 p.m.

New subject: [U-Boot] [PATCH v2 6/6] Exynos5: Remove dead code for fetching clocks

Removing dead code of peripheral and SoC specific function implementations which was used for fetching peripheral clocks. This code is not being used anymore because of the introduction of generic clock_get_periph_rate function.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- Changes since v1: - No change.

arch/arm/cpu/armv7/exynos/clock.c | 226 -------------------------------------- 1 file changed, 226 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 191f794..c0ac8fb 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -687,27 +687,6 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; }

-/* exynos5420: return pwm clock frequency */ -static unsigned long exynos5420_get_pwm_clk(void) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int ratio; - - /* - * CLK_DIV_PERIC0 - * PWM_RATIO [31:28] - */ - ratio = readl(&clk->div_peric0); - ratio = (ratio >> 28) & 0xf; - sclk = get_pll_clk(MPLL); - - pclk = sclk / (ratio + 1); - - return pclk; -} - /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) { @@ -800,100 +779,6 @@ static unsigned long exynos4x12_get_uart_clk(int dev_index) return uclk; }

-/* exynos5: return uart clock frequency */ -static unsigned long exynos5_get_uart_clk(int dev_index) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_PERIC0 - * UART0_SEL [3:0] - * UART1_SEL [7:4] - * UART2_SEL [8:11] - * UART3_SEL [12:15] - * UART4_SEL [16:19] - * UART5_SEL [23:20] - */ - sel = readl(&clk->src_peric0); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - /* - * CLK_DIV_PERIC0 - * UART0_RATIO [3:0] - * UART1_RATIO [7:4] - * UART2_RATIO [8:11] - * UART3_RATIO [12:15] - * UART4_RATIO [16:19] - * UART5_RATIO [23:20] - */ - ratio = readl(&clk->div_peric0); - ratio = (ratio >> (dev_index << 2)) & 0xf; - - uclk = sclk / (ratio + 1); - - return uclk; -} - -/* exynos5420: return uart clock frequency */ -static unsigned long exynos5420_get_uart_clk(int dev_index) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel; - unsigned int ratio; - - /* - * CLK_SRC_PERIC0 - * UART0_SEL [6:4] - * UART1_SEL [10:8] - * UART2_SEL [14:12] - * UART3_SEL [18:16] - * generalised calculation as follows - * sel = (sel >> ((dev_index * 4) + 4)) & mask; - */ - sel = readl(&clk->src_peric0); - sel = (sel >> ((dev_index * 4) + 4)) & 0x7; - - if (sel == 0x3) - sclk = get_pll_clk(MPLL); - else if (sel == 0x6) - sclk = get_pll_clk(EPLL); - else if (sel == 0x7) - sclk = get_pll_clk(RPLL); - else - return 0; - - /* - * CLK_DIV_PERIC0 - * UART0_RATIO [11:8] - * UART1_RATIO [15:12] - * UART2_RATIO [19:16] - * UART3_RATIO [23:20] - * generalised calculation as follows - * ratio = (ratio >> ((dev_index * 4) + 8)) & mask; - */ - ratio = readl(&clk->div_peric0); - ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf; - - uclk = sclk / (ratio + 1); - - return uclk; -} - static unsigned long exynos4_get_mmc_clk(int dev_index) { struct exynos4_clock *clk = @@ -943,94 +828,6 @@ static unsigned long exynos4_get_mmc_clk(int dev_index) return uclk; }

-static unsigned long exynos5_get_mmc_clk(int dev_index) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel, ratio, pre_ratio; - int shift = 0; - - sel = readl(&clk->src_fsys); - sel = (sel >> (dev_index << 2)) & 0xf; - - if (sel == 0x6) - sclk = get_pll_clk(MPLL); - else if (sel == 0x7) - sclk = get_pll_clk(EPLL); - else if (sel == 0x8) - sclk = get_pll_clk(VPLL); - else - return 0; - - switch (dev_index) { - case 0: - case 1: - ratio = readl(&clk->div_fsys1); - pre_ratio = readl(&clk->div_fsys1); - break; - case 2: - case 3: - ratio = readl(&clk->div_fsys2); - pre_ratio = readl(&clk->div_fsys2); - break; - default: - return 0; - } - - if (dev_index == 1 || dev_index == 3) - shift = 16; - - ratio = (ratio >> shift) & 0xf; - pre_ratio = (pre_ratio >> (shift + 8)) & 0xff; - uclk = (sclk / (ratio + 1)) / (pre_ratio + 1); - - return uclk; -} - -static unsigned long exynos5420_get_mmc_clk(int dev_index) -{ - struct exynos5420_clock *clk = - (struct exynos5420_clock *)samsung_get_base_clock(); - unsigned long uclk, sclk; - unsigned int sel, ratio; - - /* - * CLK_SRC_FSYS - * MMC0_SEL [10:8] - * MMC1_SEL [14:12] - * MMC2_SEL [18:16] - * generalised calculation as follows - * sel = (sel >> ((dev_index * 4) + 8)) & mask - */ - sel = readl(&clk->src_fsys); - sel = (sel >> ((dev_index * 4) + 8)) & 0x7; - - if (sel == 0x3) - sclk = get_pll_clk(MPLL); - else if (sel == 0x4) - sclk = get_pll_clk(SPLL); - else if (sel == 0x6) - sclk = get_pll_clk(EPLL); - else - return 0; - - /* - * CLK_DIV_FSYS1 - * MMC0_RATIO [9:0] - * MMC1_RATIO [19:10] - * MMC2_RATIO [29:20] - * generalised calculation as follows - * ratio = (ratio >> (dev_index * 10)) & mask - */ - ratio = readl(&clk->div_fsys1); - ratio = (ratio >> (dev_index * 10)) & 0x3ff; - - uclk = (sclk / (ratio + 1)); - - return uclk; -} - /* exynos4: set the mmc clock */ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { @@ -1409,29 +1206,6 @@ void exynos4_set_mipi_clk(void) clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); }

-/* - * I2C - * - * exynos5: obtaining the I2C clock - */ -static unsigned long exynos5_get_i2c_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long aclk_66, aclk_66_pre, sclk; - unsigned int ratio; - - sclk = get_pll_clk(MPLL); - - ratio = (readl(&clk->div_top1)) >> 24; - ratio &= 0x7; - aclk_66_pre = sclk / (ratio + 1); - ratio = readl(&clk->div_top0); - ratio &= 0x7; - aclk_66 = aclk_66_pre / (ratio + 1); - return aclk_66; -} - int exynos5_set_epll_clk(unsigned long rate) { unsigned int epll_con, epll_con_k;

-- 1.9.1

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Akshay Saraswat
Jaehoon Chung
Joonyoung Shim