According to De Morgan's Law[1]: !(A && B) = !A || !B !(A || B) = !A && !B

There are 5 places in the code where we find: #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) and 4 places in the code where we find: #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))

In words, the construct: !defined(CONFIG_SYS_[DI]CACHE_OFF) means: "is the [DI]CACHE on?" and the construct: defined(CONFIG_SYS_[DI]CACHE_OFF) means: "is the [DI]CACHE off?"

Therefore !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) means: "the opposite of 'are they both off?'" in other words: "are either or both on?" and: (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) means: "are either or both on?"

As a result, I've converted the 4 instances of '(!A || !B)' to '!(A && B)' for consistency.

[1] https://en.wikipedia.org/wiki/De_Morgan%27s_laws

Signed-off-by: Trevor Woerner trevor@toganlabs.com ---

Changes in v3: None Changes in v2: None

arch/arm/cpu/arm11/cpu.c | 2 +- arch/nds32/cpu/n1213/start.S | 2 +- arch/nds32/lib/cache.c | 2 +- arch/xtensa/cpu/start.S | 3 +-- 4 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 41feeefec1..4aa704b9ee 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -97,7 +97,7 @@ void flush_dcache_all(void) } #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */

-#if !defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) void enable_caches(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index cf966e2132..4e6a0e7a31 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -129,7 +129,7 @@ set_ivb: mfsr $r1, $mr8 and $r1, $r1, $r0 mtsr $r1, $mr8 -#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) /* * MMU_CTL NTC0 Cacheable/Write-Back */ diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c index 9ab30d1965..3e5aa7cda8 100644 --- a/arch/nds32/lib/cache.c +++ b/arch/nds32/lib/cache.c @@ -6,7 +6,7 @@ */

#include <common.h> -#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) static inline unsigned long CACHE_SET(unsigned char cache) { if (cache == ICACHE) diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S index 66acb4c610..0fafb1c4f8 100644 --- a/arch/xtensa/cpu/start.S +++ b/arch/xtensa/cpu/start.S @@ -164,8 +164,7 @@ _start: * enable data/instruction cache for relocated image. */ #if XCHAL_HAVE_SPANNING_WAY && \ - (!defined(CONFIG_SYS_DCACHE_OFF) || \ - !defined(CONFIG_SYS_ICACHE_OFF)) + !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF)) srli a7, a4, 29 slli a7, a7, 29 addi a7, a7, XCHAL_SPANNING_WAY

This config is the only config that uses: #define CONFIG_SYS_DCACHE_OFF 1 in its #define.

Remove the superfluous "1" so this cache #define is like all the others.

Signed-off-by: Trevor Woerner trevor@toganlabs.com ---

Changes in v3: None Changes in v2: None

include/configs/origen.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/origen.h b/include/configs/origen.h index 1075084ba3..1b2ed315a7 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -14,7 +14,7 @@ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_ORIGEN 1 /* working with ORIGEN*/

-#define CONFIG_SYS_DCACHE_OFF 1 +#define CONFIG_SYS_DCACHE_OFF

/* ORIGEN has 4 bank of DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000

Eventually these configuration items will be converted to Kconfig, therefore there's little point in leaving commented-out versions of them in include/configs.

Signed-off-by: Trevor Woerner trevor@toganlabs.com ---

Changes in v3: None Changes in v2: None

include/configs/uniphier.h | 4 ---- include/configs/xilinx_versal_mini.h | 1 - 2 files changed, 5 deletions(-)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 31a9c59ed5..60ea07540f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -45,10 +45,6 @@ * MMU and Cache Setting *----------------------------------------------------------------------*/

-/* Comment out the following to enable L1 cache */ -/* #define CONFIG_SYS_ICACHE_OFF */ -/* #define CONFIG_SYS_DCACHE_OFF */ - #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

#define CONFIG_TIMESTAMP diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index c15fb5fc3b..b18c0bdc5a 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H

-/* #define CONFIG_SYS_DCACHE_OFF */ #define CONFIG_SYS_ICACHE_OFF

#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000

CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig parameters; only for the ARC architecture. This patch turns these two parameters into Kconfig items everywhere else they are found.

All of the include/configs/* and defconfig changes in this patch are for arm machines only. The Kconfig changes for arc, nds32, riscv, and xtensa have been included since these symbols are found in code under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined include/configs/* or defconfigs for these architectures exist which include these symbols.

These results have been confirmed with tools/moveconfig.py.

Acked-by: Alexey Brodkin abrodkin@snopsys.com Signed-off-by: Trevor Woerner trevor@toganlabs.com

---

Changes in v3: - rebase on top of U-Boot master: b4ee6daad7 Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Changes in v2: - rebased on top of U-Boot master: 3fbd2dce35 Merge branch '2019-04-22-master-imports' - fixed up configs/xilinx_zynqmp_mini_qspi_defconfig

README | 2 -- arch/arc/Kconfig | 8 ++++++-- arch/arm/Kconfig | 12 ++++++++++++ arch/arm/mach-kirkwood/include/mach/config.h | 6 ------ arch/nds32/Kconfig | 12 ++++++++++++ arch/riscv/Kconfig | 12 ++++++++++++ arch/xtensa/Kconfig | 12 ++++++++++++ configs/SBx81LIFKW_defconfig | 1 + configs/SBx81LIFXCAT_defconfig | 1 + configs/armadillo-800eva_defconfig | 1 + configs/bcm23550_w1d_defconfig | 2 ++ configs/colibri_pxa270_defconfig | 1 + configs/d2net_v2_defconfig | 1 + configs/devkit3250_defconfig | 2 ++ configs/dns325_defconfig | 1 + configs/dockstar_defconfig | 1 + configs/dreamplug_defconfig | 1 + configs/ds109_defconfig | 1 + configs/evb-ast2500_defconfig | 1 + configs/flea3_defconfig | 1 + configs/goflexhome_defconfig | 1 + configs/gplugd_defconfig | 1 + configs/guruplug_defconfig | 1 + configs/highbank_defconfig | 1 + configs/ib62x0_defconfig | 1 + configs/iconnect_defconfig | 1 + configs/inetspace_v2_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2g_evm_defconfig | 1 + configs/k2g_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/km_kirkwood_128m16_defconfig | 1 + configs/km_kirkwood_defconfig | 1 + configs/km_kirkwood_pci_defconfig | 1 + configs/kmcoge5un_defconfig | 1 + configs/kmnusa_defconfig | 1 + configs/kmsugp1_defconfig | 1 + configs/kmsuv31_defconfig | 1 + configs/lschlv2_defconfig | 1 + configs/lsxhl_defconfig | 1 + configs/mgcoge3un_defconfig | 1 + configs/nas220_defconfig | 1 + configs/net2big_v2_defconfig | 1 + configs/netspace_lite_v2_defconfig | 1 + configs/netspace_max_v2_defconfig | 1 + configs/netspace_mini_v2_defconfig | 1 + configs/netspace_v2_defconfig | 1 + configs/nsa310s_defconfig | 1 + configs/openrd_base_defconfig | 1 + configs/openrd_client_defconfig | 1 + configs/openrd_ultimate_defconfig | 1 + configs/origen_defconfig | 1 + configs/pogo_e02_defconfig | 1 + configs/portl2_defconfig | 1 + configs/sheevaplug_defconfig | 1 + configs/stv0991_defconfig | 1 + configs/woodburn_defconfig | 1 + configs/woodburn_sd_defconfig | 1 + configs/work_92105_defconfig | 2 ++ configs/xilinx_versal_mini_defconfig | 1 + configs/xilinx_versal_mini_emmc0_defconfig | 1 + configs/xilinx_versal_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc0_defconfig | 1 + configs/xilinx_zynqmp_mini_emmc1_defconfig | 1 + configs/xilinx_zynqmp_mini_nand_defconfig | 1 + configs/xilinx_zynqmp_mini_qspi_defconfig | 1 + configs/zynq_cse_nand_defconfig | 2 ++ configs/zynq_cse_nor_defconfig | 2 ++ configs/zynq_cse_qspi_defconfig | 2 ++ include/configs/armadillo-800eva.h | 1 - include/configs/aspeed-common.h | 3 --- include/configs/bcm23550_w1d.h | 2 -- include/configs/colibri_pxa270.h | 3 --- include/configs/devkit3250.h | 2 -- include/configs/flea3.h | 2 -- include/configs/gplugd.h | 3 --- include/configs/highbank.h | 2 -- include/configs/origen.h | 2 -- include/configs/stv0991.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - include/configs/woodburn_common.h | 2 -- include/configs/work_92105.h | 2 -- include/configs/xilinx_versal_mini.h | 2 -- include/configs/xilinx_zynqmp_mini_emmc.h | 1 - include/configs/xilinx_zynqmp_mini_nand.h | 1 - include/configs/xilinx_zynqmp_mini_qspi.h | 1 - include/configs/zynq_cse.h | 2 -- 92 files changed, 127 insertions(+), 43 deletions(-)

diff --git a/README b/README index c65448c1ec..a3758d74f5 100644 --- a/README +++ b/README @@ -634,8 +634,6 @@ The following options need to be configured: the defaults discussed just above.

- Cache Configuration: - CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot - CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot

- Cache Configuration for ARM: diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 50369d5983..240d3bbedc 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -109,12 +109,16 @@ config CPU_BIG_ENDIAN Build kernel for Big Endian Mode of ARC CPU

config SYS_ICACHE_OFF - bool "Do not use Instruction Cache" + bool "Do not enable icache" default n + help + Do not enable instruction cache in U-Boot.

config SYS_DCACHE_OFF - bool "Do not use Data Cache" + bool "Do not enable dcache" default n + help + Do not enable data cache in U-Boot.

menuconfig ARC_DBG bool "ARC debugging" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e84f3d7deb..1eeac28b61 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -74,6 +74,18 @@ config ARM_ASM_UNIFIED config THUMB2_KERNEL bool

+config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + config SYS_ARM_CACHE_CP15 bool "CP15 based cache enabling support" help diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 893bd3f763..b6cf629c4f 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -26,12 +26,6 @@ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ -/* - * Disable the dcache. Currently the network driver (mvgbe.c) and USB - * EHCI driver (ehci-marvell.c) and possibly others rely on the data - * cache being disabled. - */ -#define CONFIG_SYS_DCACHE_OFF

/* * By default kwbimage.cfg from board specific folder is used diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index d72ff46113..89d8af5142 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -16,6 +16,18 @@ config TARGET_ADP_AE3XX

endchoice

+config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + source "board/AndesTech/adp-ag101p/Kconfig" source "board/AndesTech/adp-ae3xx/Kconfig"

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ae8ff7b765..b22f00ad0b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -19,6 +19,18 @@ config TARGET_SIFIVE_FU540

endchoice

+config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 2ba7132c20..c8b72ebf05 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -16,6 +16,18 @@ config TARGET_XTFPGA

endchoice

+config SYS_ICACHE_OFF + bool "Do not enable icache" + default n + help + Do not enable instruction cache in U-Boot. + +config SYS_DCACHE_OFF + bool "Do not enable dcache" + default n + help + Do not enable data cache in U-Boot. + source "board/cadence/xtfpga/Kconfig"

endmenu diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index afda7eda59..5be9fec4e2 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x00600000 CONFIG_TARGET_SBx81LIFKW=y CONFIG_IDENT_STRING="\nSBx81LIFKW" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 4cb4797a11..b50b7a66e9 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x00600000 CONFIG_TARGET_SBx81LIFXCAT=y CONFIG_IDENT_STRING="\nSBx81LIFXCAT" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig index b1d923c069..8c0536a414 100644 --- a/configs/armadillo-800eva_defconfig +++ b/configs/armadillo-800eva_defconfig @@ -6,6 +6,7 @@ CONFIG_ARCH_RMOBILE_BOARD_STRING="Armadillo-800EVA Board" CONFIG_R8A7740=y CONFIG_TARGET_ARMADILLO_800EVA=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig index 214a6a66fe..cee99e59fa 100644 --- a/configs/bcm23550_w1d_defconfig +++ b/configs/bcm23550_w1d_defconfig @@ -3,6 +3,8 @@ CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM23550_W1D=y CONFIG_SYS_TEXT_BASE=0x9f000000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index 6cd948e159..caff48a825 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_COLIBRI_PXA270=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=tty0 console=ttyS0,115200" # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 9a4d770180..afb000f9ab 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NET2BIG_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" D2 v2" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index b41a97f756..7ff2c620e3 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -6,6 +6,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index 20c6628956..ae497b7f3b 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DNS325=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nD-Link DNS-325" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_CONSOLE_MUX=y diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 41a70c9e3f..2319c73ea9 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DOCKSTAR=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="DockStar> " diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 728b470b94..d3f03c8150 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DREAMPLUG=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-DreamPlug" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig index 22996e893d..51cd1e1b24 100644 --- a/configs/ds109_defconfig +++ b/configs/ds109_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_DS109=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_FLASH is not set diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 7fb52d2732..259cf29bbf 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -5,6 +5,7 @@ CONFIG_ASPEED_AST2500=y CONFIG_TARGET_EVB_AST2500=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_DCACHE_OFF=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw" CONFIG_PRE_CONSOLE_BUFFER=y diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig index 19c96768db..336d2aaa86 100644 --- a/configs/flea3_defconfig +++ b/configs/flea3_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_FLEA3=y CONFIG_SYS_TEXT_BASE=0xA0000000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_DCACHE_OFF=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index c9abfb505c..02c492f9d0 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_GOFLEXHOME=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nSeagate GoFlex Home" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 CONFIG_CONSOLE_MUX=y diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index b12dec28ae..c8bae0cbb8 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_GPLUGD=y CONFIG_SYS_TEXT_BASE=0x00f00000 CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-gplugD" +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index c0e798e412..3c0fafa07d 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_GURUPLUG=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-GuruPlug" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index ea64ca7755..ba0f4a61b7 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_HIGHBANK=y CONFIG_SYS_TEXT_BASE=0x00008000 CONFIG_NR_DRAM_BANKS=0 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index 5cadc56515..b8a91f964c 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_IB62X0=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index e1fb3c7bbe..b76e776714 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_ICONNECT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" Iomega iConnect" +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="iconnect => " diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 2d43a67606..7fd043c9e8 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" IS v2" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index d68045bd24..662145420a 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2E_EVM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index bcc8a693a9..655220bae4 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0xC000060 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_K2E_EVM=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index 0c554dfc7f..3780f89d29 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2G_EVM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig index 00138c0b66..0f2194b171 100644 --- a/configs/k2g_hs_evm_defconfig +++ b/configs/k2g_hs_evm_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0xC000060 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_K2G_EVM=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 37308aa336..952c0831c0 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2HK_EVM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index cfa595956a..99d87c9c2d 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0xC000060 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_K2HK_EVM=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index cbe1fdff45..a1db8fc27b 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_K2L_EVM=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 66f48a1922..1cc8d83b0e 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0xC000060 CONFIG_TI_COMMON_CMD_OPTIONS=y CONFIG_TARGET_K2L_EVM=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index 92fb248111..a401f5ed76 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index b1a95cb381..d2a2a458f2 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Kirkwood" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index 443399daf2..e37d17392c 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index 7ec728149d..d84228957e 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile COGE5UN" CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index 34ece1888a..1c13eddd87 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile NUSA" CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index 63c5925fdc..b3a24a4ec8 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile SUGP1" CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index b2d62320a4..63e2221a9f 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile SUV31" CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 906800c2fd..bf97d989d9 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_LSXL=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_IDENT_STRING=" LS-CHLv2" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 038f9d1bb6..9fddacfd9d 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_LSXL=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_IDENT_STRING=" LS-XHL" CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="LSXHL" diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index d85a216ddb..eb5a4d6277 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile COGE3UN" CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index 5ca8223490..3a9e670547 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NAS220=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nNAS 220" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index cec280ba5a..b48c57df01 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NET2BIG_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" 2Big v2" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 3fa5938b81..7549cc980e 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS v2 Lite" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index 3367889753..c4d3c8e876 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS Max v2" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 9a0afaa2cf..43f5b79ab6 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS v2 Mini" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 2f3f4d35aa..d29c848b85 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NETSPACE_V2=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING=" NS v2" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index eb29a70157..9419210cf1 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_NSA310S=y CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index 151e3c25f9..bbdc8a42d9 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_OPENRD=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nOpenRD-Base" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" CONFIG_BOOTDELAY=3 CONFIG_LOGLEVEL=2 diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index c5404eff9c..9c6cfc46e8 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_OPENRD=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nOpenRD-Client" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" CONFIG_BOOTDELAY=3 CONFIG_LOGLEVEL=2 diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index d6dcbb6cc7..811b789a06 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_OPENRD=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nOpenRD-Ultimate" +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" CONFIG_BOOTDELAY=3 CONFIG_LOGLEVEL=2 diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 9d5bf7e150..108b1a455c 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_ARCH_EXYNOS4=y CONFIG_TARGET_ORIGEN=y CONFIG_SPL=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_IDENT_STRING=" for ORIGEN" CONFIG_DISTRO_DEFAULTS=y # CONFIG_USE_BOOTCOMMAND is not set diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index 943a5008af..d8db3fdd60 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_POGO_E02=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nPogo E02" +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="PogoE02> " diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig index 7e0abaa837..fcaeb4bde8 100644 --- a/configs/portl2_defconfig +++ b/configs/portl2_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x07d00000 CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Port-L2" CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2" +CONFIG_SYS_DCACHE_OFF=y CONFIG_MISC_INIT_R=y CONFIG_VERSION_VARIABLE=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index e290c38bc2..073a5385a4 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x600000 CONFIG_TARGET_SHEEVAPLUG=y CONFIG_NR_DRAM_BANKS=2 CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" +CONFIG_SYS_DCACHE_OFF=y # CONFIG_SYS_MALLOC_F is not set CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 78810529c8..d682065177 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_STV0991=y CONFIG_SYS_TEXT_BASE=0x00010000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="STV0991" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig index a5cc579ce5..40365e1d77 100644 --- a/configs/woodburn_defconfig +++ b/configs/woodburn_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_WOODBURN=y CONFIG_SYS_TEXT_BASE=0xA0000000 CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index 087c83ad1c..103c40ae09 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 2cfcf4d337..ecb7fc894d 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -9,6 +9,8 @@ CONFIG_CMD_MAX6957=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS2,115200n8" diff --git a/configs/xilinx_versal_mini_defconfig b/configs/xilinx_versal_mini_defconfig index 186c1641bf..f6e7bc5685 100644 --- a/configs/xilinx_versal_mini_defconfig +++ b/configs/xilinx_versal_mini_defconfig @@ -7,6 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x2000 CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_SYS_ICACHE_OFF=y # CONFIG_IMAGE_FORMAT_LEGACY is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/xilinx_versal_mini_emmc0_defconfig b/configs/xilinx_versal_mini_emmc0_defconfig index 7f12da62ac..1bfe5b0a20 100644 --- a/configs/xilinx_versal_mini_emmc0_defconfig +++ b/configs/xilinx_versal_mini_emmc0_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/xilinx_versal_mini_emmc1_defconfig b/configs/xilinx_versal_mini_emmc1_defconfig index 720b0dda87..582e81f462 100644 --- a/configs/xilinx_versal_mini_emmc1_defconfig +++ b/configs/xilinx_versal_mini_emmc1_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_COUNTER_FREQUENCY=2720000 +CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_R=y diff --git a/configs/xilinx_zynqmp_mini_defconfig b/configs/xilinx_zynqmp_mini_defconfig index e54c81cb48..eb20db84e7 100644 --- a/configs/xilinx_zynqmp_mini_defconfig +++ b/configs/xilinx_zynqmp_mini_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_ICACHE_OFF=y CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi" CONFIG_ARCH_ZYNQMP=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 91d7c6993f..d1dd4774a4 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_ICACHE_OFF=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 4515b2047d..89dce95671 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_ICACHE_OFF=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_zynqmp_mini_nand_defconfig b/configs/xilinx_zynqmp_mini_nand_defconfig index 6dc0690fe2..de0e4cf421 100644 --- a/configs/xilinx_zynqmp_mini_nand_defconfig +++ b/configs/xilinx_zynqmp_mini_nand_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_TEXT_BASE=0x10000 CONFIG_ENV_SIZE=0x80 CONFIG_NR_DRAM_BANKS=1 # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_ICACHE_OFF=y CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/xilinx_zynqmp_mini_qspi_defconfig b/configs/xilinx_zynqmp_mini_qspi_defconfig index 3fe9820ad3..5701c19f2c 100644 --- a/configs/xilinx_zynqmp_mini_qspi_defconfig +++ b/configs/xilinx_zynqmp_mini_qspi_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_MEM_RSVD_FOR_MMU=y CONFIG_ZYNQMP_NO_DDR=y # CONFIG_PSCI_RESET is not set # CONFIG_CMD_ZYNQMP is not set +CONFIG_SYS_ICACHE_OFF=y # CONFIG_EXPERT is not set # CONFIG_IMAGE_FORMAT_LEGACY is not set # CONFIG_BOARD_LATE_INIT is not set diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index 23f9549bee..f4db2df8a4 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0x100000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_MALLOC_LEN=0x1000 # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index d2bddecc27..8f1df5f0b1 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_SYS_MALLOC_LEN=0x1000 # CONFIG_BOARD_LATE_INIT is not set # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 2d33b6231e..1edd0cbf4b 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -5,6 +5,8 @@ CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y +CONFIG_SYS_ICACHE_OFF=y +CONFIG_SYS_DCACHE_OFF=y CONFIG_DEBUG_UART_BASE=0x0 CONFIG_DEBUG_UART_CLOCK=0 # CONFIG_ZYNQ_DDRC_INIT is not set diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 771189d877..0cb40e721c 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4) -#define CONFIG_SYS_DCACHE_OFF

/* STACK */ #define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 46062492cd..6815c5ff2c 100644 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -15,9 +15,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG

-/* Enable cache controller */ -#define CONFIG_SYS_DCACHE_OFF - #define CONFIG_SYS_SDRAM_BASE 0x80000000

#ifdef CONFIG_PRE_CON_BUF_SZ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h index d0c7de34a0..deafb7b702 100644 --- a/include/configs/bcm23550_w1d.h +++ b/include/configs/bcm23550_w1d.h @@ -100,8 +100,6 @@

#define CONFIG_USBID_ADDR 0x34052c46

-#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_L2CACHE_OFF

#endif /* __BCM23550_W1D_H */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 622b02492d..d4802f9914 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -16,9 +16,6 @@ /* Avoid overwriting factory configuration block */ #define CONFIG_BOARD_SIZE_LIMIT 0x40000

-/* We will never enable dcache because we have to setup MMU first */ -#define CONFIG_SYS_DCACHE_OFF - /* * Environment settings */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index ae9e4d4a2c..c93a5deb99 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -14,8 +14,6 @@

#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250

-#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #if !defined(CONFIG_SPL_BUILD) #define CONFIG_SKIP_LOWLEVEL_INIT #endif diff --git a/include/configs/flea3.h b/include/configs/flea3.h index e7f8b7a2ae..4cd823fa36 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -17,8 +17,6 @@ /* High Level Configuration Options */ #define CONFIG_MX35

-#define CONFIG_SYS_DCACHE_OFF - #define CONFIG_MACH_TYPE MACH_TYPE_FLEA3

/* Set TEXT at the beginning of the NOR flash */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index a8c4ddf0fd..7da8739a19 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -33,9 +33,6 @@ * Commands configuration */

-/* Disable DCACHE */ -#define CONFIG_SYS_DCACHE_OFF - /* Network configuration */ #ifdef CONFIG_CMD_NET #define CONFIG_ARMADA100_FEC diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 2566867e82..c0e295b6b7 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -6,8 +6,6 @@ #ifndef __CONFIG_H #define __CONFIG_H

-#define CONFIG_SYS_DCACHE_OFF - #define CONFIG_SYS_BOOTMAPSZ (16 << 20)

#define CONFIG_SYS_TIMER_RATE (150000000/256) diff --git a/include/configs/origen.h b/include/configs/origen.h index 1b2ed315a7..44561acbf4 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -14,8 +14,6 @@ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_ORIGEN 1 /* working with ORIGEN*/

-#define CONFIG_SYS_DCACHE_OFF - /* ORIGEN has 4 bank of DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 3177b7a759..e5262085fc 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -6,7 +6,6 @@

#ifndef __CONFIG_STV0991_H #define __CONFIG_STV0991_H -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH

/* ram memory-related information */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 6c867671cf..b44b51bbd1 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -17,7 +17,6 @@ /* SoC Configuration */ #define CONFIG_ARCH_CPU_INIT #define CONFIG_SPL_TARGET "u-boot-spi.gph" -#define CONFIG_SYS_DCACHE_OFF

/* Memory Configuration */ #define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index 82c57b65e6..5ad3dab51c 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -17,8 +17,6 @@ #define CONFIG_MX35_HCLK_FREQ 24000000 #define CONFIG_SYS_FSL_CLK

-#define CONFIG_SYS_DCACHE_OFF - #define CONFIG_MACH_TYPE MACH_TYPE_FLEA3

/* This is required to setup the ESDC controller */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 8d97905a59..e260a637d6 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -19,8 +19,6 @@ */ #define CONFIG_MACH_TYPE 736

-#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #if !defined(CONFIG_SPL_BUILD) #define CONFIG_SKIP_LOWLEVEL_INIT #endif diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h index b18c0bdc5a..4b3691b407 100644 --- a/include/configs/xilinx_versal_mini.h +++ b/include/configs/xilinx_versal_mini.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_VERSAL_MINI_H #define __CONFIG_VERSAL_MINI_H

-#define CONFIG_SYS_ICACHE_OFF - #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000

#define CONFIG_EXTRA_ENV_SETTINGS diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h index 8fdff50528..a7ae30d4d7 100644 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ b/include/configs/xilinx_zynqmp_mini_emmc.h @@ -12,7 +12,6 @@

#include <configs/xilinx_zynqmp_mini.h>

-#define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x800000

diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h index aaa9eee009..692f6e5d1a 100644 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ b/include/configs/xilinx_zynqmp_mini_nand.h @@ -12,7 +12,6 @@

#include <configs/xilinx_zynqmp_mini.h>

-#define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_SDRAM_SIZE 0x1000000 #define CONFIG_SYS_SDRAM_BASE 0x0 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h index 679ad0be3e..129af6e932 100644 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ b/include/configs/xilinx_zynqmp_mini_qspi.h @@ -12,7 +12,6 @@

#include <configs/xilinx_zynqmp_mini.h>

-#define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) #define CONFIG_SYS_MALLOC_LEN 0x2000

diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h index e7a4d4108a..daf7d75d30 100644 --- a/include/configs/zynq_cse.h +++ b/include/configs/zynq_cse.h @@ -10,8 +10,6 @@ #define __CONFIG_ZYNQ_CSE_H

#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_ICACHE_OFF

#include <configs/zynq-common.h>

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required.

Acked-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Trevor Woerner trevor@toganlabs.com ---

Changes in v3: None Changes in v2: None

arch/arc/Kconfig | 14 ++++++++++++++ arch/arc/lib/start.S | 4 ++-- arch/arm/Kconfig | 14 ++++++++++++++ arch/arm/cpu/arm11/cpu.c | 12 ++++++------ arch/arm/cpu/arm926ejs/cache.c | 12 ++++++------ arch/arm/cpu/arm926ejs/cpu.c | 2 +- arch/arm/cpu/arm926ejs/start.S | 4 ++-- arch/arm/cpu/armv7/cache_v7.c | 8 ++++---- arch/arm/cpu/armv7/iproc-common/hwinit-common.c | 2 +- arch/arm/cpu/armv7/kona-common/hwinit-common.c | 2 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 4 ++-- arch/arm/cpu/armv7/start.S | 4 ++-- arch/arm/cpu/armv7/vf610/generic.c | 2 +- arch/arm/cpu/armv7m/cache.c | 8 ++++---- arch/arm/cpu/armv8/cache_v8.c | 12 ++++++------ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 ++-- arch/arm/cpu/armv8/s32v234/cpu.c | 2 +- arch/arm/cpu/pxa/cache.c | 6 +++--- arch/arm/cpu/pxa/pxa2xx.c | 4 ++-- arch/arm/include/asm/global_data.h | 2 +- arch/arm/lib/cache-cp15.c | 6 +++--- arch/arm/lib/cache.c | 2 +- arch/arm/mach-exynos/soc.c | 2 +- arch/arm/mach-imx/cache.c | 2 +- arch/arm/mach-imx/imx8/cpu.c | 2 +- arch/arm/mach-imx/mx5/soc.c | 2 +- arch/arm/mach-keystone/init.c | 2 +- arch/arm/mach-omap2/Makefile | 2 +- arch/arm/mach-omap2/omap5/sec_entry_cpu1.S | 6 +++--- arch/arm/mach-omap2/sec-common.c | 4 ++-- arch/arm/mach-rmobile/cpu_info.c | 2 +- arch/arm/mach-rockchip/rk3036-board.c | 2 +- arch/arm/mach-rockchip/rk3128-board.c | 2 +- arch/arm/mach-rockchip/rk3188-board.c | 2 +- arch/arm/mach-rockchip/rk322x-board.c | 2 +- arch/arm/mach-rockchip/rk3288-board.c | 2 +- arch/arm/mach-rockchip/rv1108/rv1108.c | 2 +- arch/arm/mach-s5pc1xx/cache.c | 2 +- arch/arm/mach-socfpga/misc.c | 4 ++-- arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-tegra/board.c | 2 +- arch/arm/mach-zynq/cpu.c | 2 +- arch/nds32/Kconfig | 14 ++++++++++++++ arch/nds32/cpu/n1213/start.S | 8 ++++---- arch/nds32/lib/cache.c | 6 +++--- arch/riscv/Kconfig | 14 ++++++++++++++ arch/riscv/cpu/ax25/cache.c | 8 ++++---- arch/xtensa/Kconfig | 14 ++++++++++++++ arch/xtensa/cpu/start.S | 7 ++++--- board/st/stih410-b2260/board.c | 2 +- cmd/bdinfo.c | 2 +- common/board_f.c | 2 +- common/lcd.c | 2 +- configs/bitmain_antminer_s9_defconfig | 1 + configs/imx8mq_evk_defconfig | 2 ++ configs/imx8qxp_mek_defconfig | 2 ++ configs/smartweb_defconfig | 2 ++ configs/syzygy_hub_defconfig | 1 + configs/taurus_defconfig | 2 ++ configs/topic_miami_defconfig | 1 + configs/topic_miamilite_defconfig | 1 + configs/topic_miamiplus_defconfig | 1 + configs/zynq_cse_nand_defconfig | 1 + configs/zynq_cse_nor_defconfig | 1 + configs/zynq_cse_qspi_defconfig | 1 + drivers/dma/apbh_dma.c | 2 +- drivers/mtd/nand/raw/mxs_nand.c | 2 +- drivers/net/dwc_eth_qos.c | 2 +- drivers/net/rtl8169.c | 2 +- drivers/net/sh_eth.c | 3 ++- drivers/video/video-uclass.c | 2 +- include/configs/imx8mq_evk.h | 2 -- include/configs/imx8qxp_mek.h | 2 -- include/configs/mx7ulp_evk.h | 2 +- include/configs/smartweb.h | 5 ----- include/configs/taurus.h | 4 ---- include/configs/zynq-common.h | 5 ----- 77 files changed, 188 insertions(+), 118 deletions(-)

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 240d3bbedc..7d00666a3b 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -114,12 +114,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot.

+config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default n + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot.

+config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default n + help + Do not enable data cache in SPL. + menuconfig ARC_DBG bool "ARC debugging" default n diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 84959b41bd..8c744f5be7 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -16,7 +16,7 @@ ENTRY(_start) lr r5, [ARC_BCR_IC_BUILD] breq r5, 0, 1f ; I$ doesn't exist lr r5, [ARC_AUX_IC_CTRL] -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) bclr r5, r5, 0 ; 0 - Enable, 1 is Disable #else bset r5, r5, 0 ; I$ exists, but is not used @@ -37,7 +37,7 @@ ENTRY(_start) breq r5, 0, 1f ; D$ doesn't exist lr r5, [ARC_AUX_DC_CTRL] bclr r5, r5, 6 ; Invalidate (discard w/o wback) -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) bclr r5, r5, 0 ; Enable (+Inv) #else bset r5, r5, 0 ; Disable (+Inv) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1eeac28b61..504769ca5a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -80,12 +80,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot.

+config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default n + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot.

+config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default n + help + Do not enable data cache in SPL. + config SYS_ARM_CACHE_CP15 bool "CP15 based cache enabling support" help diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 4aa704b9ee..8aee1539a9 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -51,7 +51,7 @@ static void cache_flush(void) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); @@ -87,7 +87,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); }

-#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -95,15 +95,15 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 22a55f52e0..16eea693d1 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -6,7 +6,7 @@ #include <linux/types.h> #include <common.h>

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); @@ -46,7 +46,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)

asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0)); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -54,7 +54,7 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

/* * Stub implementations for l2 cache operations @@ -66,7 +66,7 @@ __weak void l2_cache_disable(void) {} __weak void invalidate_l2_cache(void) {} #endif

-#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) /* Invalidate entire I-cache and branch predictor array */ void invalidate_icache_all(void) { @@ -80,10 +80,10 @@ void invalidate_icache_all(void) {}

void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index c3f1ee1fd1..d7cffe8b69 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -44,7 +44,7 @@ int cleanup_before_linux (void) /* flush I/D-cache */ static void cache_flush (void) { -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) unsigned long i = 0;

asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 1045673292..ff592ba810 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -84,7 +84,7 @@ flush_dcache:

/* * disable MMU and D cache - * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined + * enable I cache if SYS_ICACHE_OFF is not defined */ mrc p15, 0, r0, c1, c0, 0 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */ @@ -95,7 +95,7 @@ flush_dcache: bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */ #endif orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ #endif mcr p15, 0, r0, c1, c0, 0 diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 99484c2636..0dc4ebf694 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -12,7 +12,7 @@ #define ARMV7_DCACHE_INVAL_RANGE 1 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)

/* Asm functions from cache_v7_asm.S */ void v7_flush_dcache_all(void); @@ -149,7 +149,7 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) flush_dcache_range(start, stop); v7_inval_tlb(); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -177,9 +177,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) void arm_init_domains(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

-#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) /* Invalidate entire I-cache and branch predictor array */ void invalidate_icache_all(void) { diff --git a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c index 8bf06a3e48..70431ecf6b 100644 --- a/arch/arm/cpu/armv7/iproc-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/iproc-common/hwinit-common.c @@ -5,7 +5,7 @@

#include <common.h>

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/cpu/armv7/kona-common/hwinit-common.c b/arch/arm/cpu/armv7/kona-common/hwinit-common.c index 8783893cf6..10e7488879 100644 --- a/arch/arm/cpu/armv7/kona-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/kona-common/hwinit-common.c @@ -6,7 +6,7 @@ #include <common.h> #include <linux/sizes.h>

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 7c4018ed11..ecf9e86985 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -26,7 +26,7 @@

DECLARE_GLOBAL_DATA_PTR;

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)

/* * Bit[1] of the descriptor indicates the descriptor type, @@ -215,7 +215,7 @@ void enable_caches(void) invalidate_dcache_all(); set_cr(get_cr() | CR_C); } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

uint get_svr(void) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 0cb6dd39cc..dcb4195d7b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -97,7 +97,7 @@ ENTRY(c_runtime_cpu_setup) /* * If I-cache is enabled invalidate it */ -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) mcr p15, 0, r0, c7, c5, 0 @ invalidate icache mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB @@ -155,7 +155,7 @@ ENTRY(cpu_init_cp15) bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB -#ifdef CONFIG_SYS_ICACHE_OFF +#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache #else orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 90fa695e98..f962903484 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -360,7 +360,7 @@ int get_clocks(void) return 0; }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c index 815e623c29..1106bead41 100644 --- a/arch/arm/cpu/armv7m/cache.c +++ b/arch/arm/cpu/armv7m/cache.c @@ -54,7 +54,7 @@ enum cache_action { FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */ };

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) struct dcache_config { u32 ways; u32 sets; @@ -292,7 +292,7 @@ void invalidate_dcache_all(void) } #endif

-#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)

void invalidate_icache_all(void) { @@ -349,10 +349,10 @@ int icache_status(void)

void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 038405173e..e6ab584e9d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -13,7 +13,7 @@

DECLARE_GLOBAL_DATA_PTR;

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)

/* * With 4k page granule, a virtual address is split into 4 lookup parts @@ -647,7 +647,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) __asm_invalidate_tlb_all(); }

-#else /* CONFIG_SYS_DCACHE_OFF */ +#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

/* * For SPL builds, we may want to not have dcache enabled. Any real U-Boot @@ -684,9 +684,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, { }

-#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

-#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)

void icache_enable(void) { @@ -710,7 +710,7 @@ void invalidate_icache_all(void) __asm_invalidate_l3_icache(); }

-#else /* CONFIG_SYS_ICACHE_OFF */ +#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */

void icache_enable(void) { @@ -729,7 +729,7 @@ void invalidate_icache_all(void) { }

-#endif /* CONFIG_SYS_ICACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */

/* * Enable dCache & iCache, whether cache is actually enabled diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 978d46b32f..12d709e23e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -388,7 +388,7 @@ void cpu_name(char *name) strcpy(name, "unknown"); }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* * To start MMU before DDR is available, we create MMU table in SRAM. * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three @@ -611,7 +611,7 @@ void enable_caches(void) icache_enable(); dcache_enable(); } -#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

#ifdef CONFIG_TFABOOT enum boot_src __get_boot_src(u32 porsr1) diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c index 1fa6841eaf..b4cb67a66a 100644 --- a/arch/arm/cpu/armv8/s32v234/cpu.c +++ b/arch/arm/cpu/armv8/s32v234/cpu.c @@ -16,7 +16,7 @@ u32 cpu_mask(void) return readl(MC_ME_CS); }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)

#define S32V234_IRAM_BASE 0x3e800000UL #define S32V234_IRAM_SIZE 0x800000UL diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c index 8b932b10e1..5cd4a9524b 100644 --- a/arch/arm/cpu/pxa/cache.c +++ b/arch/arm/cpu/pxa/cache.c @@ -6,7 +6,7 @@ #include <linux/types.h> #include <common.h>

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void invalidate_dcache_all(void) { /* Flush/Invalidate I cache */ @@ -35,7 +35,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop) { return invalidate_dcache_range(start, stop); } -#else /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#else /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ void invalidate_dcache_all(void) { } @@ -43,7 +43,7 @@ void invalidate_dcache_all(void) void flush_dcache_all(void) { } -#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ +#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */

/* * Stub implementations for l2 cache operations diff --git a/arch/arm/cpu/pxa/pxa2xx.c b/arch/arm/cpu/pxa/pxa2xx.c index b9fd41ece2..0b28f0a3ef 100644 --- a/arch/arm/cpu/pxa/pxa2xx.c +++ b/arch/arm/cpu/pxa/pxa2xx.c @@ -286,10 +286,10 @@ void reset_cpu(ulong ignored)

void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index c3ee5f0c7b..a81b1061df 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -35,7 +35,7 @@ struct arch_global_data { unsigned int tbl; unsigned long lastinc; unsigned long long timer_reset_value; -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) unsigned long tlb_addr; unsigned long tlb_size; #if defined(CONFIG_ARM64) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0688f1e6a6..b2913e8165 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -10,7 +10,7 @@ #include <linux/compiler.h> #include <asm/armv7_mpu.h>

-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))

DECLARE_GLOBAL_DATA_PTR;

@@ -246,7 +246,7 @@ static void cache_disable(uint32_t cache_bit) } #endif

-#ifdef CONFIG_SYS_ICACHE_OFF +#if CONFIG_IS_ENABLED(SYS_ICACHE_OFF) void icache_enable (void) { return; @@ -278,7 +278,7 @@ int icache_status(void) } #endif

-#ifdef CONFIG_SYS_DCACHE_OFF +#if CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void dcache_enable (void) { return; diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 565fbbe109..449544d11c 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -87,7 +87,7 @@ void noncached_init(void) noncached_end = end; noncached_next = start;

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) mmu_set_region_dcache_behaviour(noncached_start, size, DCACHE_OFF); #endif } diff --git a/arch/arm/mach-exynos/soc.c b/arch/arm/mach-exynos/soc.c index 589e16c5ad..2ae9a43b4e 100644 --- a/arch/arm/mach-exynos/soc.c +++ b/arch/arm/mach-exynos/soc.c @@ -25,7 +25,7 @@ void reset_cpu(ulong addr) #endif }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index 75e1f54c6a..a605942503 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -37,7 +37,7 @@ static void enable_ca7_smp(void) } }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 2c425357b5..53f9a8735a 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -446,7 +446,7 @@ void enable_caches(void) dcache_enable(); }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); diff --git a/arch/arm/mach-imx/mx5/soc.c b/arch/arm/mach-imx/mx5/soc.c index 43d6c08b42..bbb335e275 100644 --- a/arch/arm/mach-imx/mx5/soc.c +++ b/arch/arm/mach-imx/mx5/soc.c @@ -62,7 +62,7 @@ u32 __weak get_board_rev(void) } #endif

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index f43b3dcbfa..3dee300d77 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -204,7 +204,7 @@ void reset_cpu(ulong addr)

void enable_caches(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); #endif diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 0777a0c998..bb01eab80e 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o endif endif

-ifeq ($(CONFIG_SYS_DCACHE_OFF),) +ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif

diff --git a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S index 6dc92a6bfa..32de9d3d4f 100644 --- a/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S +++ b/arch/arm/mach-omap2/omap5/sec_entry_cpu1.S @@ -16,7 +16,7 @@

.arch_extension sec

-#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) .global flush_dcache_range #endif

@@ -79,7 +79,7 @@ ENTRY(omap_smc_sec_cpu1) push {r4, r5, lr} ldr r4, =omap_smc_sec_cpu1_args stm r4, {r0,r1,r2,r3} @ Save args to memory -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) mov r0, r4 mov r1, #CONFIG_SYS_CACHELINE_SIZE add r1, r0, r1 @ dcache is not enabled on CPU1, so @@ -109,7 +109,7 @@ ENDPROC(omap_smc_sec_cpu1) */ .section .data omap_smc_sec_cpu1_args: -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) .balign CONFIG_SYS_CACHELINE_SIZE .rept CONFIG_SYS_CACHELINE_SIZE/4 .word 0 diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 600a31280c..b45d3ee544 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -333,7 +333,7 @@ int secure_tee_install(u32 addr) debug("tee_info.tee_arg0 = %08X\n", tee_info.tee_arg0); debug("tee_file_size = %d\n", tee_file_size);

-#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) flush_dcache_range( rounddown((u32)loadptr, ARCH_DMA_MINALIGN), roundup((u32)loadptr + tee_file_size, ARCH_DMA_MINALIGN)); @@ -356,7 +356,7 @@ int secure_tee_install(u32 addr) /* Reuse the tee_info buffer for SMC params */ smc_cpu1_params = (u32 *)&tee_info; smc_cpu1_params[0] = 0; -#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) flush_dcache_range((u32)smc_cpu1_params, (u32)smc_cpu1_params + roundup(sizeof(u32), ARCH_DMA_MINALIGN)); #endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index aa5be52dfd..499b3cdd43 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -17,7 +17,7 @@ int arch_cpu_init(void)

/* R-Car Gen3 D-cache is enabled in memmap-gen3.c */ #ifndef CONFIG_RCAR_GEN3 -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 872bed9606..a9a44539b5 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -48,7 +48,7 @@ int dram_init(void) } #endif

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c index 7fd667a0b8..2c28099a75 100644 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -57,7 +57,7 @@ int dram_init_banksize(void) return 0; }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 3802395bc0..e32bd922e8 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -75,7 +75,7 @@ err: #endif }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index 5659248178..8627deb62a 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -85,7 +85,7 @@ int dram_init_banksize(void) return 0; }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9c4f7f219f..9feb823722 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -186,7 +186,7 @@ err: #endif }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-rockchip/rv1108/rv1108.c b/arch/arm/mach-rockchip/rv1108/rv1108.c index 33596f628c..66aeb3ffcc 100644 --- a/arch/arm/mach-rockchip/rv1108/rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/rv1108.c @@ -6,7 +6,7 @@

#include <common.h>

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-s5pc1xx/cache.c b/arch/arm/mach-s5pc1xx/cache.c index 12c9d7ce3a..0b879b545d 100644 --- a/arch/arm/mach-s5pc1xx/cache.c +++ b/arch/arm/mach-s5pc1xx/cache.c @@ -9,7 +9,7 @@

#include <common.h>

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { dcache_enable(); diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..8b311137f5 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -48,10 +48,10 @@ int dram_init(void)

void enable_caches(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) icache_enable(); #endif -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) dcache_enable(); #endif } diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index c6dd7b8e54..7f5b633e01 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -300,7 +300,7 @@ void reset_cpu(ulong addr) #endif }

-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index f8fc042a1d..4e159075d3 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -226,7 +226,7 @@ U_BOOT_DEVICE(ns16550_com1) = { }; #endif

-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index a3422cd5cf..e5f557716b 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -83,7 +83,7 @@ void reset_cpu(ulong addr) ; }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index 89d8af5142..feeec4448d 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -22,12 +22,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot.

+config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default n + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot.

+config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default n + help + Do not enable data cache in SPL. + source "board/AndesTech/adp-ag101p/Kconfig" source "board/AndesTech/adp-ae3xx/Kconfig"

diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 4e6a0e7a31..691888157f 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -129,7 +129,7 @@ set_ivb: mfsr $r1, $mr8 and $r1, $r1, $r0 mtsr $r1, $mr8 -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) /* * MMU_CTL NTC0 Cacheable/Write-Back */ @@ -139,7 +139,7 @@ set_ivb: mtsr $r1, $mr0 #endif

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_ARCH_MAP_SYSMEM /* * MMU_CTL NTC1 Non-cacheable @@ -158,14 +158,14 @@ set_ivb: #endif #endif

-#if !defined(CONFIG_SYS_ICACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) li $r0, 0x1 mfsr $r1, $mr8 or $r1, $r1, $r0 mtsr $r1, $mr8 #endif

-#if !defined(CONFIG_SYS_DCACHE_OFF) +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) li $r0, 0x2 mfsr $r1, $mr8 or $r1, $r1, $r0 diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c index 3e5aa7cda8..27065136dd 100644 --- a/arch/nds32/lib/cache.c +++ b/arch/nds32/lib/cache.c @@ -6,7 +6,7 @@ */

#include <common.h> -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) static inline unsigned long CACHE_SET(unsigned char cache) { if (cache == ICACHE) @@ -38,7 +38,7 @@ static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) } #endif

-#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) void invalidate_icache_all(void) { unsigned long end, line_size; @@ -133,7 +133,7 @@ int icache_status(void)

#endif

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void dcache_wbinval_all(void) { unsigned long end, line_size; diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b22f00ad0b..54362d7a45 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,12 +25,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot.

+config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default n + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot.

+config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default n + help + Do not enable data cache in SPL. + # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 228fc55f56..cd95058d9d 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -30,7 +30,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end)

void icache_enable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -43,7 +43,7 @@ void icache_enable(void)

void icache_disable(void) { -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence.i\n\t" @@ -57,7 +57,7 @@ void icache_disable(void)

void dcache_enable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "csrr t1, mcache_ctl\n\t" @@ -70,7 +70,7 @@ void dcache_enable(void)

void dcache_disable(void) { -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE asm volatile ( "fence\n\t" diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index c8b72ebf05..f437b98409 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -22,12 +22,26 @@ config SYS_ICACHE_OFF help Do not enable instruction cache in U-Boot.

+config SPL_SYS_ICACHE_OFF + bool "Do not enable icache in SPL" + depends on SPL + default n + help + Do not enable instruction cache in SPL. + config SYS_DCACHE_OFF bool "Do not enable dcache" default n help Do not enable data cache in U-Boot.

+config SPL_SYS_DCACHE_OFF + bool "Do not enable dcache in SPL" + depends on SPL + default n + help + Do not enable data cache in SPL. + source "board/cadence/xtfpga/Kconfig"

endmenu diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S index 0fafb1c4f8..38d2fa2fe1 100644 --- a/arch/xtensa/cpu/start.S +++ b/arch/xtensa/cpu/start.S @@ -164,18 +164,19 @@ _start: * enable data/instruction cache for relocated image. */ #if XCHAL_HAVE_SPANNING_WAY && \ - !(defined(CONFIG_SYS_DCACHE_OFF) && defined(CONFIG_SYS_ICACHE_OFF)) + !(CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && \ + CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) srli a7, a4, 29 slli a7, a7, 29 addi a7, a7, XCHAL_SPANNING_WAY -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) rdtlb1 a8, a7 srli a8, a8, 4 slli a8, a8, 4 addi a8, a8, CA_WRITEBACK wdtlb a8, a7 #endif -#ifndef CONFIG_SYS_ICACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) ritlb1 a8, a7 srli a8, a8, 4 slli a8, a8, 4 diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index b4fc8f3ce1..111e64b995 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -26,7 +26,7 @@ int dram_init_banksize(void) return 0; }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index cbeba6ba28..f576e226ee 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -321,7 +321,7 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, print_eths(); #endif print_baudrate(); -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) print_num("TLB addr", gd->arch.tlb_addr); #endif print_num("relocaddr", gd->relocaddr); diff --git a/common/board_f.c b/common/board_f.c index 7ef20f2042..c25eb188fb 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -381,7 +381,7 @@ static int reserve_round_4k(void) #ifdef CONFIG_ARM __weak int reserve_mmu(void) { -#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; gd->relocaddr -= gd->arch.tlb_size; diff --git a/common/lcd.c b/common/lcd.c index cd630405d4..95526b1e17 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -61,7 +61,7 @@ void lcd_sync(void) * architectures do not actually implement it. Is there a way to find * out whether it exists? For now, ARM is safe. */ -#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF) +#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) int line_length;

if (lcd_flush_dcache) diff --git a/configs/bitmain_antminer_s9_defconfig b/configs/bitmain_antminer_s9_defconfig index 63acd28c7e..3787a9573a 100644 --- a/configs/bitmain_antminer_s9_defconfig +++ b/configs/bitmain_antminer_s9_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_VENDOR="bitmain" CONFIG_SYS_BOARD="antminer_s9" CONFIG_SYS_CONFIG_NAME="bitmain_antminer_s9" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_ENV_OFFSET=0x300000 CONFIG_SPL_STACK_R_ADDR=0x200000 diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 989dc445d0..9a962b3da7 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_IMX8MQ_EVK=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 2fb2fdf7ff..6bee2d1024 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x80020000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 005b6e9044..ffe50b1fd7 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_SPL_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x23000000 CONFIG_TARGET_SMARTWEB=y diff --git a/configs/syzygy_hub_defconfig b/configs/syzygy_hub_defconfig index 896232a715..5616b3e23a 100644 --- a/configs/syzygy_hub_defconfig +++ b/configs/syzygy_hub_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_VENDOR="opalkelly" CONFIG_SYS_CONFIG_NAME="syzygy_hub" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 0da77d8c94..684a0ede73 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_SPL_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_AT91=y CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig index b55885669d..bb8d37a370 100644 --- a/configs/topic_miami_defconfig +++ b/configs/topic_miami_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_VENDOR="topic" CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig index 6983245173..87af8c81d3 100644 --- a/configs/topic_miamilite_defconfig +++ b/configs/topic_miamilite_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_VENDOR="topic" CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig index 89461ee6d2..874ca8a746 100644 --- a/configs/topic_miamiplus_defconfig +++ b/configs/topic_miamiplus_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_VENDOR="topic" CONFIG_SYS_CONFIG_NAME="topic_miami" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_SPL_STACK_R_ADDR=0x200000 CONFIG_SPL=y diff --git a/configs/zynq_cse_nand_defconfig b/configs/zynq_cse_nand_defconfig index f4db2df8a4..2d0ecb1fdd 100644 --- a/configs/zynq_cse_nand_defconfig +++ b/configs/zynq_cse_nand_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_cse" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0x100000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 diff --git a/configs/zynq_cse_nor_defconfig b/configs/zynq_cse_nor_defconfig index 8f1df5f0b1..23e15da651 100644 --- a/configs/zynq_cse_nor_defconfig +++ b/configs/zynq_cse_nor_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_cse" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 diff --git a/configs/zynq_cse_qspi_defconfig b/configs/zynq_cse_qspi_defconfig index 1edd0cbf4b..b81198b339 100644 --- a/configs/zynq_cse_qspi_defconfig +++ b/configs/zynq_cse_qspi_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SYS_CONFIG_NAME="zynq_cse" CONFIG_ARCH_ZYNQ=y +CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_SYS_TEXT_BASE=0xFFFC0000 CONFIG_ENV_SIZE=0x190 CONFIG_SPL_STACK_R_ADDR=0x200000 diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 017cc89a89..ac589feeb7 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -81,7 +81,7 @@ static int mxs_dma_read_semaphore(int channel) return tmp; }

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) void mxs_dma_flush_desc(struct mxs_dma_desc *desc) { uint32_t addr; diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index be4ee2c7f8..b93d77a395 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -50,7 +50,7 @@ struct nand_ecclayout fake_ecc_layout; /* * Cache management functions */ -#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) static void mxs_nand_flush_data_buf(struct mxs_nand_info *info) { uint32_t addr = (uint32_t)info->data_buf; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9f1c5af46e..590e756f5c 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -241,7 +241,7 @@ struct eqos_tegra186_regs { */ #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ - !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) + !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) #warning Cache line size is larger than descriptor size #endif #endif diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index a78f3d233f..70dc362650 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -301,7 +301,7 @@ static unsigned char rxdata[RX_BUF_LEN]; */ #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ - !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) + !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) #warning cache-line size is larger than descriptor size #endif #endif diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 4646f2ba4e..741c58453f 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -34,7 +34,8 @@ # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif

-#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF) +#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \ + !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define flush_cache_wback(addr, len) \ flush_dcache_range((u32)addr, \ (u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE))) diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 14aac88d6d..b19bfb4f2f 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -149,7 +149,7 @@ void video_sync(struct udevice *vid, bool force) * architectures do not actually implement it. Is there a way to find * out whether it exists? For now, ARM is safe. */ -#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_DCACHE_OFF) +#if defined(CONFIG_ARM) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) struct video_priv *priv = dev_get_uclass_priv(vid);

if (priv->flush_dcache) { diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index aaecf6f053..bdfd82de2c 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -36,8 +36,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF

/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_MALLOC_F_ADDR 0x182000 diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 18ea5a8fb6..e847158b92 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -23,8 +23,6 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x00120000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF #define CONFIG_MALLOC_F_ADDR 0x00120000

#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index b8dcaa1036..34970ba7a2 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -168,7 +168,7 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

-#ifndef CONFIG_SYS_DCACHE_OFF +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #define CONFIG_CMD_CACHE #endif

diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 0d0c6bdc69..776d7d7970 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -216,11 +216,6 @@ #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) #define CONFIG_SYS_AT91_PLLB 0x10483f0e

-#if defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#endif - #define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS #define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO

diff --git a/include/configs/taurus.h b/include/configs/taurus.h index c3353d74a9..ce784f90ab 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -21,10 +21,6 @@ #include <asm/hardware.h> #include <linux/sizes.h>

-#if defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF -#endif /* * Warning: changing CONFIG_SYS_TEXT_BASE requires * adapting the initial boot program. diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 523d4da56b..143dc7bb22 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -284,11 +284,6 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif

-/* Disable dcache for SPL just for sure */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_DCACHE_OFF -#endif - /* Address in RAM where the parameters must be copied by SPL. */ #define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000