[PATCH v2 0/6] riscv: Make SBI v0.2 the default SBI version to work with OpenSBI v0.7
This series makes SBI v0.2 the default SBI version to work with OpenSBI v0.7, that is scheduled to be released soon.
Hart State Management (HSM) SBI extension is supported from OpenSBI v0.7. HSM extension allows S-mode software to boot all the harts a defined order rather than legacy method of random booting of harts. S-mode U-Boot doesn't need to support HSM extension, as it doesn't need to boot all the harts. The operating system should be capable enough to bring up all other non-booting harts using HSM extension.
This patch depends on the following Kbuild patch by Masahiro: http://patchwork.ozlabs.org/project/uboot/patch/20200416043826.490120-4-masa...
With the updated Kbuild, the following patch in v1 is dropped: [PATCH 6/7] riscv: Remove CONFIG_IS_ENABLED(SMP) in global data
Changes in v2: - add "!RISCV_SMODE" to the dependency - drop patch: "riscv: Remove CONFIG_IS_ENABLED(SMP) in global data"
Bin Meng (6): riscv: qemu: Remove the simple-bus driver for the SoC node riscv: Merge unnecessary SMP ifdefs in start.S riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL riscv: Add SMP Kconfig option dependency for U-Boot proper riscv: Add Kconfig option for SBI v0.2 riscv: Make SBI v0.2 the default SBI version
arch/riscv/Kconfig | 34 ++++++++++++++++++++++++++++++++-- arch/riscv/cpu/generic/cpu.c | 14 -------------- arch/riscv/cpu/start.S | 18 +++++++----------- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/Makefile | 2 +- arch/riscv/lib/spl.c | 2 +- common/spl/spl_opensbi.c | 2 +- doc/board/emulation/qemu-riscv.rst | 2 +- 8 files changed, 44 insertions(+), 32 deletions(-)
Prior to QEMU v3.1.0, QEMU generated the 'virt' SoC node with a "riscv-virtio-soc" compatible string, and a "simple-bus" driver was created to accommodate that special case in U-Boot.
Starting from QEMU v3.1.0, the SoC node was set as a "simple-bus", hence the special simple-bus driver is no longer needed.
Update the doc to mention the latest tested QEMU version 4.2.0.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
Changes in v2: None
arch/riscv/cpu/generic/cpu.c | 14 -------------- doc/board/emulation/qemu-riscv.rst | 2 +- 2 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c index c0a5288..13a69ef 100644 --- a/arch/riscv/cpu/generic/cpu.c +++ b/arch/riscv/cpu/generic/cpu.c @@ -4,7 +4,6 @@ */
#include <common.h> -#include <dm.h> #include <irq_func.h>
/* @@ -21,16 +20,3 @@ int cleanup_before_linux(void)
return 0; } - -/* To enumerate devices on the /soc/ node, create a "simple-bus" driver */ -static const struct udevice_id riscv_virtio_soc_ids[] = { - { .compatible = "riscv-virtio-soc" }, - { } -}; - -U_BOOT_DRIVER(riscv_virtio_soc) = { - .name = "riscv_virtio_soc", - .id = UCLASS_SIMPLE_BUS, - .of_match = riscv_virtio_soc_ids, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/doc/board/emulation/qemu-riscv.rst b/doc/board/emulation/qemu-riscv.rst index fe7505e..c390006 100644 --- a/doc/board/emulation/qemu-riscv.rst +++ b/doc/board/emulation/qemu-riscv.rst @@ -56,7 +56,7 @@ For instructions on how to run U-Boot in supervisor mode on QEMU with OpenSBI, see the documentation available with OpenSBI: https://github.com/riscv/opensbi/blob/master/docs/platform/qemu_virt.md
-These have been tested in QEMU 3.0.0. +These have been tested in QEMU 4.2.0.
Running U-Boot SPL ------------------
Two consecutive SMP ifdefs blocks can be combined into one.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Atish Patra atish.patra@wdc.com ---
Changes in v2: None
arch/riscv/cpu/start.S | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 6b3ff99..ecf0482 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -58,9 +58,7 @@ _start: /* tp: hart id */ li t0, CONFIG_NR_CPUS bge tp, t0, hart_out_of_bounds_loop -#endif
-#ifdef CONFIG_SMP /* set xSIE bit to receive IPIs */ #if CONFIG_IS_ENABLED(RISCV_MMODE) li t0, MIE_MSIE @@ -377,9 +375,7 @@ hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi j hart_out_of_bounds_loop -#endif
-#ifdef CONFIG_SMP /* SMP relocation entry */ secondary_hart_relocate: /* a1: new sp */
With SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
For U-Boot running in SPL, SMP can be turned on, while in U-Boot proper, SMP can be optionally turned off if using SBI v0.2 HSM.
Introduce a new SPL_SMP Kconfig option to support this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Atish Patra atish.patra@wdc.com ---
Changes in v2: None
arch/riscv/Kconfig | 13 ++++++++++++- arch/riscv/cpu/start.S | 14 +++++++------- arch/riscv/include/asm/global_data.h | 2 +- arch/riscv/lib/Makefile | 2 +- arch/riscv/lib/spl.c | 2 +- common/spl/spl_opensbi.c | 2 +- 6 files changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3061bf8..5ef6849 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -200,10 +200,21 @@ config SMP machine. If you say Y here, U-Boot will run on many, but not all, single processor machines.
+config SPL_SMP + bool "Symmetric Multi-Processing in SPL" + depends on SPL && SPL_RISCV_MMODE + default y + help + This enables support for systems with more than one CPU in SPL. + If you say N here, U-Boot SPL will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor + machine. If you say Y here, U-Boot SPL will run on many, but not + all, single processor machines. + config NR_CPUS int "Maximum number of CPUs (2-32)" range 2 32 - depends on SMP + depends on SMP || SPL_SMP default 8 help On multiprocessor machines, U-Boot sets up a stack for each CPU. diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index ecf0482..fce0982 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -53,7 +53,7 @@ _start: /* mask all interrupts */ csrw MODE_PREFIX(ie), zero
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* check if hart is within range */ /* tp: hart id */ li t0, CONFIG_NR_CPUS @@ -91,7 +91,7 @@ call_board_init_f_0: mv gp, a0
/* setup stack */ -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, a0, t0 @@ -182,7 +182,7 @@ spl_stack_gd_setup: mv s0, a0
/* setup stack on main hart */ -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s0, t0 @@ -231,7 +231,7 @@ relocate_code: *Set up the stack */ stack_setup: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* tp: hart id */ slli t0, tp, CONFIG_STACK_SIZE_SHIFT sub sp, s2, t0 @@ -326,7 +326,7 @@ clbss_l: blt t0, t1, clbss_l
relocate_secondary_harts: -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) /* send relocation IPI */ la t0, secondary_hart_relocate add a0, t0, t6 @@ -370,7 +370,7 @@ call_board_init_r: */ jr t4 /* jump to board_init_r() */
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) hart_out_of_bounds_loop: /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */ wfi @@ -393,7 +393,7 @@ secondary_hart_relocate: secondary_hart_loop: wfi
-#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) csrr t0, MODE_PREFIX(ip) #if CONFIG_IS_ENABLED(RISCV_MMODE) andi t0, t0, MIE_MSIE diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b74bd7e..72fb4b4 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,7 +24,7 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLMT void __iomem *plmt; /* plmt base address */ #endif -#ifdef CONFIG_SMP +#if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif #ifndef CONFIG_XIP diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index adadbf4..bd7b2c4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -22,7 +22,7 @@ endif obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o -obj-$(CONFIG_SMP) += smp.o +obj-$(CONFIG_$(SPL_)SMP) += smp.o obj-$(CONFIG_SPL_BUILD) += spl.o
# For building EFI apps diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index ae07bbe..4ca038b 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -41,7 +41,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) invalidate_icache_all();
debug("image entry point: 0x%lX\n", spl_image->entry_point); -#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP ret = smp_call_function(spl_image->entry_point, (ulong)fdt_blob, 0, 0); if (ret) hang(); diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c index a136073..3519c34 100644 --- a/common/spl/spl_opensbi.c +++ b/common/spl/spl_opensbi.c @@ -76,7 +76,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image) opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point; invalidate_icache_all();
-#ifdef CONFIG_SMP +#ifdef CONFIG_SPL_SMP /* * Start OpenSBI on all secondary harts and wait for acknowledgment. *
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v2: - add "!RISCV_SMODE" to the dependency
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5ef6849..a252cdb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing" + depends on SBI_V01 || !RISCV_SMODE help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor
On Thu, Apr 16, 2020 at 8:18 AM Bin Meng bmeng.cn@gmail.com wrote:
U-Boot proper running in S-mode only need SMP support when using SBI v0.1. With SBI v0.2 HSM extension, it does not need implement multicore boot in U-Boot proper.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v2:
- add "!RISCV_SMODE" to the dependency
arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 5ef6849..a252cdb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -193,6 +193,7 @@ config SYS_MALLOC_F_LEN
config SMP bool "Symmetric Multi-Processing"
depends on SBI_V01 || !RISCV_SMODE help This enables support for systems with more than one CPU. If you say N here, U-Boot will run on single and multiprocessor-- 2.7.4
Reviewed-by: Atish Patra atish.patra@wdc.com
SBI v0.2 is more scalable and extendable to handle future needs for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM extension, only a single hart need to boot and enter operating system. The booting hart can bring up secondary harts one by one afterwards.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Atish Patra atish.patra@wdc.com ---
Changes in v2: None
arch/riscv/Kconfig | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index a252cdb..c729871 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -226,14 +226,32 @@ config SBI bool default y if RISCV_SMODE || SPL_RISCV_SMODE
+choice + prompt "SBI support" + default SBI_V01 + config SBI_V01 bool "SBI v0.1 support" - default y depends on SBI help This config allows kernel to use SBI v0.1 APIs. This will be deprecated in future once legacy M-mode software are no longer in use.
+config SBI_V02 + bool "SBI v0.2 support" + depends on SBI + help + This config allows kernel to use SBI v0.2 APIs. SBI v0.2 is more + scalable and extendable to handle future needs for RISC-V supervisor + interfaces. For example, with SBI v0.2 HSM extension, only a single + hart need to boot and enter operating system. The booting hart can + bring up secondary harts one by one afterwards. + + Choose this option if OpenSBI v0.7 or above release is used together + with U-Boot. + +endchoice + config SBI_IPI bool depends on SBI
To work with latest OpenSBI release (v0.7 or above) that has the HSM extension support, select the SBI v0.2 support by default.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Atish Patra atish.patra@wdc.com
---
Changes in v2: - drop patch: "riscv: Remove CONFIG_IS_ENABLED(SMP) in global data"
arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c729871..fb5fe5a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -228,7 +228,7 @@ config SBI
choice prompt "SBI support" - default SBI_V01 + default SBI_V02
config SBI_V01 bool "SBI v0.1 support"
participants (2)
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Atish Patra -
Bin Meng