Number of ECC status registers i.e. (ECCSTATx) has been increased in IFC version 2.0.0 due to increase in SRAM size. This is causing eccstat array to over flow.

So, replace eccstat array with u32 variable to make it fail-safe and independent of number of ECC status registers or SRAM size.

Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Jagdish Gediya jagdish.gediya@nxp.com --- Changes for v2: - Resolve checkpatch error - Give suitable name to variable and do proper initialization.

drivers/mtd/nand/fsl_ifc_nand.c | 32 ++++++++++++-------------------- include/fsl_ifc.h | 4 ++-- 2 files changed, 14 insertions(+), 22 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index d1165f7..6eb44c3 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -270,14 +270,9 @@ static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,

/* returns nonzero if entire page is blank */ static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, - u32 *eccstat, unsigned int bufnum) + u32 eccstat, unsigned int bufnum) { - u32 reg = eccstat[bufnum / 4]; - int errors; - - errors = (reg >> ((3 - bufnum % 4) * 8)) & 15; - - return errors; + return (eccstat >> ((3 - bufnum % 4) * 8)) & 15; }

/* @@ -291,7 +286,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) struct fsl_ifc_runtime *ifc = ctrl->regs.rregs; u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; u32 time_start; - u32 eccstat[8] = {0}; + u32 eccstat; int i;

/* set the chip select for NAND Transaction */ @@ -321,20 +316,17 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) if (ctrl->eccread) { int errors; int bufnum = ctrl->page & priv->bufnum_mask; - int sector = bufnum * chip->ecc.steps; - int sector_end = sector + chip->ecc.steps - 1; - - for (i = sector / 4; i <= sector_end / 4; i++) { - if (i >= ARRAY_SIZE(eccstat)) { - printf("%s: eccstat too small for %d\n", - __func__, i); - return -EIO; - } + int sector_start = bufnum * chip->ecc.steps; + int sector_end = sector_start + chip->ecc.steps - 1; + u32 *eccstat_regs;

- eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); - } + eccstat_regs = ifc->ifc_nand.nand_eccstat; + eccstat = ifc_in32(&eccstat_regs[sector_start / 4]); + + for (i = sector_start; i <= sector_end; i++) { + if (!(i % 4)) + eccstat = ifc_in32(&eccstat_regs[i / 4]);

- for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i);

if (errors == 15) { diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 29aa687..4bff019 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -892,8 +892,8 @@ struct fsl_ifc_nand { u32 nand_erattr1; u32 res19[0x10]; u32 nand_fsr; - u32 res20[0x3]; - u32 nand_eccstat[6]; + u32 res20[0x1]; + u32 nand_eccstat[8]; u32 res21[0x1c]; u32 nanndcr; u32 res22[0x2];