[PATCH 0/2] sunxi: Fix two H616 DRAM bugs
At closer inspection of H616 DRAM code I found two issues: 1. ODT is never configured due to missing CONFIG_ prefix in check 2. Dual rank read calibration never exits calibration mode
Only first issue is important to fix for currently supported boards. Fixing second one is future proofing.
Please take a look.
Best regards, Jernej
Jernej Skrabec (2): sunxi: fix H616 DRAM ODT support sunxi: Fix H616 DRAM read calibration for dual rank
arch/arm/mach-sunxi/dram_sun50i_h616.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Kconfig symbol is missing CONFIG_ prefix, so compiler will always skip ODT configuration.
Fix symbol name.
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index acdfb3ceef8c..76f520f4e780 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -720,7 +720,7 @@ static bool mctl_phy_init(struct dram_para *para) writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc); writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
- if (IS_ENABLED(DRAM_ODT_EN)) + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) mctl_phy_configure_odt();
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
On Sat, 29 Jan 2022 16:58:42 +0100 Jernej Skrabec jernej.skrabec@gmail.com wrote:
Kconfig symbol is missing CONFIG_ prefix, so compiler will always skip ODT configuration.
Fix symbol name.
Oops, nice catch!
Reviewed-by: Andre Przywara andre.przywara@arm.com
Applied to sunxi/master.
Cheers, Andre
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com
arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index acdfb3ceef8c..76f520f4e780 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -720,7 +720,7 @@ static bool mctl_phy_init(struct dram_para *para) writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc); writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c);
- if (IS_ENABLED(DRAM_ODT_EN))
if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) mctl_phy_configure_odt();
clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa);
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that it has to be set before read calibration and cleared afterwards. This is already done for first rank, but not for second (copy & paste error.)
Fix it.
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 76f520f4e780..83e8abc2f8d8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para) } }
- setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); }
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
On Sat, 29 Jan 2022 16:58:43 +0100 Jernej Skrabec jernej.skrabec@gmail.com wrote:
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that it has to be set before read calibration and cleared afterwards. This is already done for first rank, but not for second (copy & paste error.)
Indeed looks like it, from the logic point of view.
Fix it.
Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec jernej.skrabec@gmail.com
Reviewed-by: Andre Przywara andre.przywara@arm.com
Applied to sunxi/master.
Cheers, Andre
arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 76f520f4e780..83e8abc2f8d8 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para) } }
setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1);}
clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30);
participants (2)
-
Andre Przywara -
Jernej Skrabec