[U-Boot] [PATCH v2 0/4] DaVinci DA8xx: tidy up clock IDs
This small series of patches tidies up the clock IDs that are used to interact with the PLL controllers on the DaVinci DA8xx processors.
It more clearly defines the structure and meaning of the IDs and untangles some model-specific code that can't be shared among the family. This tidying allows three bugs to be identified and resolved: - on the DA850, UART2's clock may come from ASYNC3, unlike the DA830; - the DA830 doesn't have a DDR2/mDDR PHY, or a PLL controller for it; - the DSP speed reported by bdinfo was not being initialised on the DA8xx family.
Laurence Withers (4): DaVinci DA8xx: tidy up clock ID definition DaVinci DA850: UART2 clock ID comes from ASYNC3 DaVinci DA8xx: replace magic number for DDR speed DaVinci DA8xx: fix set_cpu_clk_info()
arch/arm/cpu/arm926ejs/davinci/cpu.c | 22 ++++++---- arch/arm/include/asm/arch-davinci/hardware.h | 57 +++++++++++++++++++------ 2 files changed, 57 insertions(+), 22 deletions(-)
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Prabhakar Lad prabhakar.csengg@gmail.com --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/include/asm/arch-davinci/hardware.h | 53 +++++++++++++++++++------- 1 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index b145c6e..dac43bb 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -441,21 +441,46 @@ struct davinci_pllc_regs { #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE) #define DAVINCI_PLLC_DIV_MASK 0x1f
-#define ASYNC3 get_async3_src() -#define PLL1_SYSCLK2 ((1 << 16) | 0x2) -#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3) -/* Clock IDs */ +/* + * A clock ID is a 32-bit number where bit 16 represents the PLL controller + * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor, + * counting from 1. Clock IDs may be passed to clk_get(). + */ + +/* flags to select PLL controller */ +#define DAVINCI_PLLC0_FLAG (0) +#define DAVINCI_PLLC1_FLAG (1 << 16) + enum davinci_clk_ids { - DAVINCI_SPI0_CLKID = 2, - DAVINCI_UART2_CLKID = 2, - DAVINCI_MMC_CLKID = 2, - DAVINCI_MDIO_CLKID = 4, - DAVINCI_ARM_CLKID = 6, - DAVINCI_PLLM_CLKID = 0xff, - DAVINCI_PLLC_CLKID = 0x100, - DAVINCI_AUXCLK_CLKID = 0x101 + /* + * Clock IDs for PLL outputs. Each may be switched on/off independently, + * and each may map to one or more peripherals. + */ + DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, + DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, + DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, + DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2, + + /* map peripherals to clock IDs */ + DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, + DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, + DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, + DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, + DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2, + + /* special clock ID - output of PLL multiplier */ + DAVINCI_PLLM_CLKID = 0x0FF, + + /* special clock ID - output of PLL post divisor */ + DAVINCI_PLLC_CLKID = 0x100, + + /* special clock ID - PLL bypass */ + DAVINCI_AUXCLK_CLKID = 0x101, };
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ + : get_async3_src()) + int clk_get(enum davinci_clk_ids id);
/* Boot config */ @@ -570,10 +595,10 @@ static inline int cpu_is_da850(void) return ((part_no == 0xb7d1) ? 1 : 0); }
-static inline int get_async3_src(void) +static inline enum davinci_clk_ids get_async3_src(void) { return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ? - PLL1_SYSCLK2 : 2; + DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2; }
#endif /* CONFIG_SOC_DA8XX */
On Tue, Jul 31, 2012 at 09:30:34AM +0000, Laurence Withers wrote:
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual.
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Prabhakar Lad prabhakar.csengg@gmail.com
I've applied this with a minor change for DAVINCI_MMC0_CLKID having been added here in another series. Thanks!
On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Prabhakar Lad prabhakar.csengg@gmail.com --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/include/asm/arch-davinci/hardware.h | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index dac43bb..0fce940 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -466,7 +466,6 @@ enum davinci_clk_ids { DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2, - DAVINCI_UART2_CLKID = DAVINCI_PLL0_SYSCLK2,
/* special clock ID - output of PLL multiplier */ DAVINCI_PLLM_CLKID = 0x0FF, @@ -478,6 +477,9 @@ enum davinci_clk_ids { DAVINCI_AUXCLK_CLKID = 0x101, };
+#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ + : get_async3_src()) + #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \ : get_async3_src())
On Tue, Jul 31, 2012 at 09:30:35AM +0000, Laurence Withers wrote:
On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match.
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Prabhakar Lad prabhakar.csengg@gmail.com
I've applied this after making it apply cleanly again (DAVINCI_MMC0_CLKID again), thanks!
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller).
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Prabhakar Lad prabhakar.csengg@gmail.com --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 3 ++- arch/arm/include/asm/arch-davinci/hardware.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 6cb857a..41201d0 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -194,7 +194,8 @@ int set_cpu_clk_info(void) #ifdef CONFIG_SOC_DA8XX gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = clk_get(0x10001) / 1000000; + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); #else
unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 0fce940..7f3dcc2 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -459,10 +459,12 @@ enum davinci_clk_ids { DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2, DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4, DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6, + DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1, DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
/* map peripherals to clock IDs */ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6, + DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1, DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4, DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2, DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions.
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Hadli, Manjunath manjunath.hadli@ti.com Cc: Heiko Schocher hs@denx.de --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 23 ++++++++++++++--------- 1 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 41201d0..b31add8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } + +int set_cpu_clk_info(void) +{ + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); + gd->bd->bi_dsp_freq = 0; + return 0; +} + #else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset) @@ -187,17 +198,9 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* !CONFIG_SOC_DA8XX */
int set_cpu_clk_info(void) { -#ifdef CONFIG_SOC_DA8XX - gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; - /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : - (clk_get(DAVINCI_DDR_CLKID) / 1000000); -#else - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; #if defined(CONFIG_SOC_DM365) pllbase = DAVINCI_PLL_CNTRL1_BASE; @@ -216,10 +219,12 @@ int set_cpu_clk_info(void) pllbase = DAVINCI_PLL_CNTRL0_BASE; #endif gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; -#endif + return 0; }
+#endif /* !CONFIG_SOC_DA8XX */ + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()
Hi Laurence,
On Tuesday 31 July 2012 03:00 PM, Laurence Withers wrote:
This small series of patches tidies up the clock IDs that are used to interact with the PLL controllers on the DaVinci DA8xx processors.
It more clearly defines the structure and meaning of the IDs and untangles some model-specific code that can't be shared among the family. This tidying allows three bugs to be identified and resolved:
- on the DA850, UART2's clock may come from ASYNC3, unlike the DA830;
- the DA830 doesn't have a DDR2/mDDR PHY, or a PLL controller for it;
- the DSP speed reported by bdinfo was not being initialised on the DA8xx family.
I have tested the entire patchset on da850, da830, dm355, dm6446 and dm365 evm's.
Tested-by: Prabhakar Lad prabhakar.lad@ti.com
Thx, --Prabhakar Lad
Laurence Withers (4): DaVinci DA8xx: tidy up clock ID definition DaVinci DA850: UART2 clock ID comes from ASYNC3 DaVinci DA8xx: replace magic number for DDR speed DaVinci DA8xx: fix set_cpu_clk_info()
arch/arm/cpu/arm926ejs/davinci/cpu.c | 22 ++++++---- arch/arm/include/asm/arch-davinci/hardware.h | 57 +++++++++++++++++++------ 2 files changed, 57 insertions(+), 22 deletions(-)
On Tue, Jul 31, 2012 at 09:30:33AM +0000, Laurence Withers wrote:
This small series of patches tidies up the clock IDs that are used to interact with the PLL controllers on the DaVinci DA8xx processors.
It more clearly defines the structure and meaning of the IDs and untangles some model-specific code that can't be shared among the family. This tidying allows three bugs to be identified and resolved:
- on the DA850, UART2's clock may come from ASYNC3, unlike the DA830;
- the DA830 doesn't have a DDR2/mDDR PHY, or a PLL controller for it;
- the DSP speed reported by bdinfo was not being initialised on the DA8xx family.
Laurence Withers (4): DaVinci DA8xx: tidy up clock ID definition DaVinci DA850: UART2 clock ID comes from ASYNC3 DaVinci DA8xx: replace magic number for DDR speed DaVinci DA8xx: fix set_cpu_clk_info()
Applied to u-boot-ti/master, thanks!
participants (3)
-
Laurence Withers -
Prabhakar Lad -
Tom Rini