Some cross-platform drivers rely on this header present. Make it so for x86.

It's just a copy'n'paste of arch/arm/include/asm/dma-mapping.h.

Suggested-by: Bin Meng bmeng.cn@gmail.com Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com --- arch/x86/include/asm/dma-mapping.h | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 arch/x86/include/asm/dma-mapping.h

diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h new file mode 100644 index 0000000000..7de4c08e36 --- /dev/null +++ b/arch/x86/include/asm/dma-mapping.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007 + * Stelian Pop stelian@popies.net + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_X86_DMA_MAPPING_H +#define __ASM_X86_DMA_MAPPING_H + +#define dma_mapping_error(x, y) 0 + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +#endif /* __ASM_X86_DMA_MAPPING_H */

From: Felipe Balbi felipe.balbi@linux.intel.com

Add Intel Tangier SoC support.

Intel Tangier SoC is a core part of Intel Merrifield platform. For example, Intel Edison board is based on such platform.

The patch is based on work done by the following people (in alphabetical order): Aiden Park aiden.park@intel.com Dukjoon Jeon dukjoon.jeon@intel.com eric.park eric.park@intel.com Fabien Chereau fabien.chereau@intel.com Scott D Phillips scott.d.phillips@intel.com Sebastien Colleur sebastienx.colleur@intel.com Steve Sakoman steve.sakoman@intel.com Vincent Tinelli vincent.tinelli@intel.com

Reviewed-by: Simon Glass sjg@chromium.org Signed-off-by: Vincent Tinelli vincent.tinelli@intel.com Signed-off-by: Felipe Balbi felipe.balbi@linux.intel.com Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com --- arch/x86/Kconfig | 1 + arch/x86/cpu/Makefile | 1 + arch/x86/cpu/tangier/Kconfig | 20 ++++ arch/x86/cpu/tangier/Makefile | 7 ++ arch/x86/cpu/tangier/car.S | 13 +++ arch/x86/cpu/tangier/sdram.c | 206 +++++++++++++++++++++++++++++++++++++++++ arch/x86/cpu/tangier/tangier.c | 34 +++++++ arch/x86/include/asm/sfi.h | 19 ++++ 8 files changed, 301 insertions(+) create mode 100644 arch/x86/cpu/tangier/Kconfig create mode 100644 arch/x86/cpu/tangier/Makefile create mode 100644 arch/x86/cpu/tangier/car.S create mode 100644 arch/x86/cpu/tangier/sdram.c create mode 100644 arch/x86/cpu/tangier/tangier.c

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0cd981e73e..5c8dc822ef 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -114,6 +114,7 @@ source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" +source "arch/x86/cpu/tangier/Kconfig"

# architecture-specific options below

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e1c84ce097..999429e62b 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ +obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-y += lapic.o ioapic.o obj-y += irq.o ifndef CONFIG_$(SPL_)X86_64 diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig new file mode 100644 index 0000000000..92d3352f3b --- /dev/null +++ b/arch/x86/cpu/tangier/Kconfig @@ -0,0 +1,20 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_TANGIER + bool + depends on INTEL_MID + +config SYS_CAR_ADDR + hex + default 0x19200000 + +config SYS_CAR_SIZE + hex + default 0x4000 + help + Space in bytes in eSRAM used as Cache-As-RAM (CAR). + Note this size must not exceed eSRAM's total size. diff --git a/arch/x86/cpu/tangier/Makefile b/arch/x86/cpu/tangier/Makefile new file mode 100644 index 0000000000..d146b3f5c2 --- /dev/null +++ b/arch/x86/cpu/tangier/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += car.o tangier.o sdram.o diff --git a/arch/x86/cpu/tangier/car.S b/arch/x86/cpu/tangier/car.S new file mode 100644 index 0000000000..6982106c19 --- /dev/null +++ b/arch/x86/cpu/tangier/car.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010-2011 + * Graeme Russ, graeme.russ@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.section .text + +.globl car_init +car_init: + jmp car_init_ret diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c new file mode 100644 index 0000000000..5743077431 --- /dev/null +++ b/arch/x86/cpu/tangier/sdram.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/e820.h> +#include <asm/global_data.h> +#include <asm/sfi.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * SFI tables are part of the first stage bootloader. + * + * U-Boot finds the System Table by searching 16-byte boundaries between + * physical address 0x000E0000 and 0x000FFFFF. U-Boot shall search this region + * starting at the low address and shall stop searching when the 1st valid SFI + * System Table is found. + */ +#define SFI_BASE_ADDR 0x000E0000 +#define SFI_LENGTH 0x00020000 +#define SFI_TABLE_LENGTH 16 + +static int sfi_table_check(struct sfi_table_header *sbh) +{ + char chksum = 0; + char *pos = (char *)sbh; + u32 i; + + if (sbh->len < SFI_TABLE_LENGTH) + return -ENXIO; + + if (sbh->len > SFI_LENGTH) + return -ENXIO; + + for (i = 0; i < sbh->len; i++) + chksum += *pos++; + + if (chksum) + error("sfi: Invalid checksum\n"); + + /* Checksum is OK if zero */ + return chksum ? -EILSEQ : 0; +} + +static int sfi_table_is_type(struct sfi_table_header *sbh, const char *signature) +{ + return !strncmp(sbh->sig, signature, SFI_SIGNATURE_SIZE) && + !sfi_table_check(sbh); +} + +static struct sfi_table_simple *sfi_get_table_by_sig(unsigned long addr, + const char *signature) +{ + struct sfi_table_simple *sb; + u32 i; + + for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) { + sb = (struct sfi_table_simple *)(addr + i); + if (sfi_table_is_type(&sb->header, signature)) + return sb; + } + + return NULL; +} + +static struct sfi_table_simple *sfi_search_mmap(void) +{ + struct sfi_table_header *sbh; + struct sfi_table_simple *sb; + u32 sys_entry_cnt; + u32 i; + + /* Find SYST table */ + sb = sfi_get_table_by_sig(SFI_BASE_ADDR, SFI_SIG_SYST); + if (!sb) { + error("sfi: failed to locate SYST table\n"); + return NULL; + } + + sys_entry_cnt = (sb->header.len - sizeof(*sbh)) / 8; + + /* Search through each SYST entry for MMAP table */ + for (i = 0; i < sys_entry_cnt; i++) { + sbh = (struct sfi_table_header *)(unsigned long)sb->pentry[i]; + + if (sfi_table_is_type(sbh, SFI_SIG_MMAP)) + return (struct sfi_table_simple *)sbh; + } + + error("sfi: failed to locate SFI MMAP table\n"); + return NULL; +} + +#define sfi_for_each_mentry(i, sb, mentry) \ + for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry; \ + i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry); \ + i++, mentry++) \ + +static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + unsigned long long start, end, size; + int type, total = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + start = mentry->phys_start; + size = mentry->pages << 12; + end = start + size; + + if (start > end) + continue; + + /* translate SFI mmap type to E820 map type */ + switch (mentry->type) { + case SFI_MEM_CONV: + type = E820_RAM; + break; + case SFI_MEM_UNUSABLE: + case SFI_RUNTIME_SERVICE_DATA: + continue; + default: + type = E820_RESERVED; + } + + if (total == E820MAX) + break; + entries[total].addr = start; + entries[total].size = size; + entries[total].type = type; + + total++; + } + + return total; +} + +static int sfi_get_bank_size(void) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + int bank = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + if (mentry->type != SFI_MEM_CONV) + continue; + + gd->bd->bi_dram[bank].start = mentry->phys_start; + gd->bd->bi_dram[bank].size = mentry->pages << 12; + bank++; + } + + return bank; +} + +static phys_size_t sfi_get_ram_size(void) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + phys_size_t ram = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + if (mentry->type != SFI_MEM_CONV) + continue; + + ram += mentry->pages << 12; + } + + debug("sfi: RAM size %llu\n", ram); + return ram; +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + return sfi_setup_e820(max_entries, entries); +} + +int dram_init_banksize(void) +{ + sfi_get_bank_size(); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sfi_get_ram_size(); + return 0; +} diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c new file mode 100644 index 0000000000..20d6c6039b --- /dev/null +++ b/arch/x86/cpu/tangier/tangier.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ +int arch_cpu_init(void) +{ + return x86_cpu_init_f(); +} + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + scu_ipc_simple_command(IPCMSG_COLD_RESET, 0); +} diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h index d6c44c978a..6c6ebeade8 100644 --- a/arch/x86/include/asm/sfi.h +++ b/arch/x86/include/asm/sfi.h @@ -60,6 +60,25 @@ struct __packed sfi_mem_entry { u64 attrib; };

+/* Memory type definitions */ +enum sfi_mem_type { + SFI_MEM_RESERVED, + SFI_LOADER_CODE, + SFI_LOADER_DATA, + SFI_BOOT_SERVICE_CODE, + SFI_BOOT_SERVICE_DATA, + SFI_RUNTIME_SERVICE_CODE, + SFI_RUNTIME_SERVICE_DATA, + SFI_MEM_CONV, + SFI_MEM_UNUSABLE, + SFI_ACPI_RECLAIM, + SFI_ACPI_NVS, + SFI_MEM_MMIO, + SFI_MEM_IOPORT, + SFI_PAL_CODE, + SFI_MEM_TYPEMAX, +}; + struct __packed sfi_cpu_table_entry { u32 apic_id; };

Add Intel Edison board which is using U-Boot.

The patch is based on work done by the following people (in alphabetical order): Aiden Park aiden.park@intel.com Dukjoon Jeon dukjoon.jeon@intel.com eric.park eric.park@intel.com Fabien Chereau fabien.chereau@intel.com Felipe Balbi felipe.balbi@linux.intel.com Scott D Phillips scott.d.phillips@intel.com Sebastien Colleur sebastienx.colleur@intel.com Steve Sakoman steve.sakoman@intel.com Vincent Tinelli vincent.tinelli@intel.com

In case we're building for Intel Edison, we must have 4096 bytes of zeroes in the beginning on u-boot.bin. This is done in board/intel/edison/config.mk.

First run sets hardware_id environment variable which is read from System Controller Unit (SCU).

Serial number (serial# environment variable) is generated based on eMMC CID.

MAC address on USB network interface is unique to the board but kept the same all over the time.

Set mac address from U-Boot using following scheme: OUI = 02:00:86 next 3 bytes of MAC address set from eMMC serial number

This allows to have a unique mac address across reboot and flashing.

Signed-off-by: Vincent Tinelli vincent.tinelli@intel.com Signed-off-by: Felipe Balbi felipe.balbi@linux.intel.com Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com --- arch/x86/cpu/tangier/Kconfig | 4 ++ arch/x86/dts/Makefile | 1 + arch/x86/dts/edison.dts | 89 ++++++++++++++++++++++++++++++++ board/intel/Kconfig | 8 +++ board/intel/edison/Kconfig | 26 ++++++++++ board/intel/edison/Makefile | 1 + board/intel/edison/config.mk | 18 +++++++ board/intel/edison/edison.c | 104 ++++++++++++++++++++++++++++++++++++++ board/intel/edison/edison_start.S | 13 +++++ configs/edison_defconfig | 53 +++++++++++++++++++ doc/README.x86 | 39 ++++++++++++++ include/configs/edison.h | 78 ++++++++++++++++++++++++++++ 12 files changed, 434 insertions(+) create mode 100644 arch/x86/dts/edison.dts create mode 100644 board/intel/edison/Kconfig create mode 100644 board/intel/edison/Makefile create mode 100644 board/intel/edison/config.mk create mode 100644 board/intel/edison/edison.c create mode 100644 board/intel/edison/edison_start.S create mode 100644 configs/edison_defconfig create mode 100644 include/configs/edison.h

diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig index 92d3352f3b..b67c6a799e 100644 --- a/arch/x86/cpu/tangier/Kconfig +++ b/arch/x86/cpu/tangier/Kconfig @@ -18,3 +18,7 @@ config SYS_CAR_SIZE help Space in bytes in eSRAM used as Cache-As-RAM (CAR). Note this size must not exceed eSRAM's total size. + +config SYS_USB_OTG_BASE + hex + default 0xf9100000 diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 3f534ad40a..6589495f23 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -10,6 +10,7 @@ dtb-y += bayleybay.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ + edison.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts new file mode 100644 index 0000000000..0b04984c6e --- /dev/null +++ b/arch/x86/dts/edison.dts @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Edison"; + compatible = "intel,edison"; + + aliases { + serial0 = &serial0; + }; + + chosen { + stdout-path = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <2>; + }; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + serial0: serial@ff010180 { + compatible = "intel,mid-uart"; + reg = <0xff010180 0x100>; + reg-shift = <0>; + clock-frequency = <29491200>; + current-speed = <115200>; + }; + + emmc: mmc@ff3fc000 { + compatible = "intel,sdhci-tangier"; + reg = <0xff3fc000 0x1000>; + }; + +/* + * FIXME: For now U-Boot DM model doesn't allow to power up this controller. + * Enabling it will make U-Boot hang. + * + sdcard: mmc@ff3fa000 { + compatible = "intel,sdhci-tangier"; + reg = <0xff3fa000 0x1000>; + }; + */ + + pmu: power@ff00b000 { + compatible = "intel,pmu-mid"; + reg = <0xff00b000 0x1000>; + }; + + scu: ipc@ff009000 { + compatible = "intel,scu-ipc"; + reg = <0xff009000 0x1000>; + }; +}; diff --git a/board/intel/Kconfig b/board/intel/Kconfig index 4d341aa799..d7d950e877 100644 --- a/board/intel/Kconfig +++ b/board/intel/Kconfig @@ -35,6 +35,13 @@ config TARGET_CROWNBAY Intel Platform Controller Hub EG20T, other system components and peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.

+config TARGET_EDISON + bool "Edison" + help + This is the Intel Edison Compute Module. It contains a dual core Intel + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers. + config TARGET_GALILEO bool "Galileo" help @@ -64,6 +71,7 @@ endchoice source "board/intel/bayleybay/Kconfig" source "board/intel/cougarcanyon2/Kconfig" source "board/intel/crownbay/Kconfig" +source "board/intel/edison/Kconfig" source "board/intel/galileo/Kconfig" source "board/intel/minnowmax/Kconfig"

diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig new file mode 100644 index 0000000000..4ff9d5adec --- /dev/null +++ b/board/intel/edison/Kconfig @@ -0,0 +1,26 @@ +if TARGET_EDISON + +config SYS_BOARD + default "edison" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "tangier" + +config SYS_CONFIG_NAME + default "edison" + +config SYS_TEXT_BASE + default 0x01101000 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_LOAD_FROM_32_BIT + select INTEL_MID + select INTEL_TANGIER + select BOARD_LATE_INIT + select MD5 + +endif diff --git a/board/intel/edison/Makefile b/board/intel/edison/Makefile new file mode 100644 index 0000000000..a29f51294b --- /dev/null +++ b/board/intel/edison/Makefile @@ -0,0 +1 @@ +obj-y += edison_start.o edison.o diff --git a/board/intel/edison/config.mk b/board/intel/edison/config.mk new file mode 100644 index 0000000000..465133fd77 --- /dev/null +++ b/board/intel/edison/config.mk @@ -0,0 +1,18 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause +# + +# Add 4096 bytes of zeroes to u-boot.bin +quiet_cmd_mkalign_eds = EDSALGN $@ +cmd_mkalign_eds = \ + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \ + mv $@ $^ + +ALL-y += u-boot-align.bin +u-boot-align.bin: u-boot.bin + $(call if_changed,mkalign_eds) + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c new file mode 100644 index 0000000000..a1a7d4d7c8 --- /dev/null +++ b/board/intel/edison/edison.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <dwc3-uboot.h> +#include <mmc.h> +#include <u-boot/md5.h> +#include <usb.h> +#include <watchdog.h> + +#include <linux/usb/gadget.h> + +#include <asm/cache.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct dwc3_device dwc3_device_data = { + .maximum_speed = USB_SPEED_HIGH, + .base = CONFIG_SYS_USB_OTG_BASE, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, +}; + +int usb_gadget_handle_interrupts(int controller_index) +{ + dwc3_uboot_handle_interrupt(controller_index); + WATCHDOG_RESET(); + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) + return dwc3_uboot_init(&dwc3_device_data); + return -EINVAL; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + return 0; + } + return -EINVAL; +} + +static void assign_serial(void) +{ + struct mmc *mmc = find_mmc_device(0); + unsigned char ssn[16]; + char usb0addr[18]; + char serial[33]; + int i; + + if (!mmc) + return; + + md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn); + + snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x", + ssn[13], ssn[14], ssn[15]); + setenv("usb0addr", usb0addr); + + for (i = 0; i < 16; i++) + snprintf(&serial[2 * i], 3, "%02x", ssn[i]); + setenv("serial#", serial); + +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + saveenv(); +#endif +} + +static void assign_hardware_id(void) +{ + struct ipc_ifwi_version v; + char hardware_id[4]; + int ret; + + ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4); + if (ret < 0) + printf("Can't retrieve hardware revision\n"); + + snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id); + setenv("hardware_id", hardware_id); + +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + saveenv(); +#endif +} + +int board_late_init(void) +{ + if (!getenv("serial#")) + assign_serial(); + + if (!getenv("hardware_id")) + assign_hardware_id(); + + return 0; +} diff --git a/board/intel/edison/edison_start.S b/board/intel/edison/edison_start.S new file mode 100644 index 0000000000..932fe6c24b --- /dev/null +++ b/board/intel/edison/edison_start.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* board early intialization */ +.globl early_board_init +early_board_init: + /* No 32-bit board specific initialisation */ + jmp early_board_init_ret diff --git a/configs/edison_defconfig b/configs/edison_defconfig new file mode 100644 index 0000000000..f33b35c8d2 --- /dev/null +++ b/configs/edison_defconfig @@ -0,0 +1,53 @@ +CONFIG_X86=y +CONFIG_VENDOR_INTEL=y +CONFIG_DEFAULT_DEVICE_TREE="edison" +CONFIG_TARGET_EDISON=y +CONFIG_SMP=y +# CONFIG_ARCH_EARLY_INIT_R is not set +# CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ENV_CALLBACK=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_TIMER=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_CPU=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_TANGIER=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_DM_RTC=y +CONFIG_INTEL_MID_SERIAL=y +CONFIG_TIMER=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Intel" +CONFIG_G_DNL_VENDOR_NUM=0x8087 +CONFIG_G_DNL_PRODUCT_NUM=0x0a99 +CONFIG_TANGIER_WATCHDOG=y +CONFIG_FAT_WRITE=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SHA1=y diff --git a/doc/README.x86 b/doc/README.x86 index c69dc1c511..9eb541d0f8 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -18,6 +18,8 @@ U-Boot supports running as a coreboot [1] payload on x86. So far only Link work with minimal adjustments on other x86 boards since coreboot deals with most of the low-level details.

+U-boot is a main bootloader on Intel Edison board. + U-Boot also supports booting directly from x86 reset vector, without coreboot. In this case, known as bare mode, from the fact that it runs on the 'bare metal', U-Boot acts like a BIOS replacement. The following platforms @@ -61,6 +63,16 @@ Change the 'Board configuration file' and 'Board Device Tree Source (dts) file' to point to a new board. You can also change the Cache-As-RAM (CAR) related settings here if the default values do not fit your new board.

+Build Instructions for U-Boot as main bootloader +------------------------------------------------ + +Intel Edison instructions: + +Simple you can build U-Boot and obtain u-boot.bin + +$ make edison_defconfig +$ make all + Build Instructions for U-Boot as BIOS replacement (bare mode) ------------------------------------------------------------- Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a @@ -455,6 +467,33 @@ Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,

=> zboot 01000000 - 04000000 1b1ab50

+Updating U-Boot on Edison +------------------------- +By default Intel Edison boards are shipped with preinstalled heavily +patched U-Boot v2014.04. Though it supports DFU which we may be able to +use. + +1. Prepare u-boot.bin as described in chapter above. You still need one +more step (if and only if you have original U-Boot), i.e. run the +following command: + +$ truncate -s %4096 u-boot.bin + +2. Run your board and interrupt booting to U-Boot console. In the console +call: + + => run do_force_flash_os + +3. Wait for few seconds, it will prepare environment variable and runs +DFU. Run DFU command from the host system: + +$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin + +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and +reset the board: + + => reset + CPU Microcode ------------- Modern CPUs usually require a special bit stream called microcode [8] to be diff --git a/include/configs/edison.h b/include/configs/edison.h new file mode 100644 index 0000000000..8f28cba200 --- /dev/null +++ b/include/configs/edison.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2017 Intel Corp. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/ibmpc.h> + +/*----------------------------------------------------------------------- + * Boot + */ + +#define CONFIG_CMD_ZBOOT +#define CONFIG_BOOTCOMMAND "run bootcmd" + +/*----------------------------------------------------------------------- + * DISK Partition support + */ + +#define CONFIG_RANDOM_UUID + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 128 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_AUTO_COMPLETE + +/*----------------------------------------------------------------------- + * Memory + */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 +#define CONFIG_PHYSMEM + +#define CONFIG_NR_DRAM_BANKS 3 + +#define CONFIG_SYS_STACK_SIZE (32 * 1024) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) + +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x01000000 + +/*----------------------------------------------------------------------- + * Environment + */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 +#define CONFIG_ENV_SIZE (64 * 1024) +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) +#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) +#define CONFIG_SUPPORT_EMMC_BOOT + +/*----------------------------------------------------------------------- + * PCI + */ + +#define CONFIG_CMD_PCI + +/*----------------------------------------------------------------------- + * RTC + */ + +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 +#define CONFIG_RTC_MC146818 + +#endif