[U-Boot] [PATCH 00/11] x86: Disable DM_PCI_COMPAT
In order to disable DM_PCI_COMPAT for x86, there are some more clean up work to do.
This series is available in pci-working2 branch of u-boot-x86 repo.
Bin Meng (11): net: pch_gbe: Convert to use DM PCI API net: designware: Use dm_pci_mem_to_phys() in the probe routine net: e1000: Convert to use DM PCI API x86: quark: Use Quark's own PCI config APIs efi: app: Clean up defconfig efi: app: Disable CONFIG_USB_EHCI_PCI x86: chromebox_panther: Drop the cache line size hack x86: chromebox_panther: Convert to use driver model ethernet dm: pci: Add missing forward declarations x86: Disable DM_PCI_COMPAT x86: Drop pci_type1.c and DEFINE_PCI_DEVICE_TABLE
arch/x86/Kconfig | 3 -- arch/x86/cpu/quark/mrc_util.c | 5 ++- arch/x86/include/asm/pci.h | 7 ---- arch/x86/lib/Makefile | 3 -- arch/x86/lib/pci_type1.c | 50 ------------------------- configs/chromebox_panther_defconfig | 1 + configs/efi-x86_defconfig | 2 +- drivers/net/designware.c | 4 +- drivers/net/e1000.c | 75 ++++++++++++++++++++++++++++++++++++- drivers/net/e1000.h | 4 ++ drivers/net/pch_gbe.c | 27 ++++++------- drivers/net/pch_gbe.h | 2 +- include/configs/chromebox_panther.h | 2 - include/configs/efi-x86.h | 4 +- include/pci.h | 16 +++----- 15 files changed, 103 insertions(+), 102 deletions(-) delete mode 100644 arch/x86/lib/pci_type1.c
Use native DM PCI APIs instead of legacy compatible ones.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/net/pch_gbe.c | 27 ++++++++++++--------------- drivers/net/pch_gbe.h | 2 +- 2 files changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index 56d29d4..137818b 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -117,15 +117,15 @@ static void pch_gbe_rx_descs_init(struct udevice *dev)
memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM); for (i = 0; i < PCH_GBE_DESC_NUM; i++) - rx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, + rx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)(priv->rx_buff[i]));
- writel(pci_phys_to_mem(priv->bdf, (u32)rx_desc), + writel(dm_pci_phys_to_mem(priv->dev, (u32)rx_desc), &mac_regs->rx_dsc_base); writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->rx_dsc_size);
- writel(pci_phys_to_mem(priv->bdf, (u32)(rx_desc + 1)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_desc + 1)), &mac_regs->rx_dsc_sw_p); }
@@ -137,11 +137,11 @@ static void pch_gbe_tx_descs_init(struct udevice *dev)
memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
- writel(pci_phys_to_mem(priv->bdf, (u32)tx_desc), + writel(dm_pci_phys_to_mem(priv->dev, (u32)tx_desc), &mac_regs->tx_dsc_base); writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1), &mac_regs->tx_dsc_size); - writel(pci_phys_to_mem(priv->bdf, (u32)(tx_desc + 1)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_desc + 1)), &mac_regs->tx_dsc_sw_p); }
@@ -251,7 +251,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (length < 64) frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
- tx_desc->buffer_addr = pci_phys_to_mem(priv->bdf, (u32)packet); + tx_desc->buffer_addr = dm_pci_phys_to_mem(priv->dev, (u32)packet); tx_desc->length = length; tx_desc->tx_words_eob = length + 3; tx_desc->tx_frame_ctrl = frame_ctrl; @@ -262,7 +262,7 @@ static int pch_gbe_send(struct udevice *dev, void *packet, int length) if (++priv->tx_idx >= PCH_GBE_DESC_NUM) priv->tx_idx = 0;
- writel(pci_phys_to_mem(priv->bdf, (u32)(tx_head + priv->tx_idx)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(tx_head + priv->tx_idx)), &mac_regs->tx_dsc_sw_p);
start = get_timer(0); @@ -294,7 +294,7 @@ static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp) if ((u32)rx_desc == hw_desc) return -EAGAIN;
- buffer_addr = pci_mem_to_phys(priv->bdf, rx_desc->buffer_addr); + buffer_addr = dm_pci_mem_to_phys(priv->dev, rx_desc->buffer_addr); *packetp = (uchar *)buffer_addr; length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
@@ -315,7 +315,7 @@ static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length) if (++rx_swp >= PCH_GBE_DESC_NUM) rx_swp = 0;
- writel(pci_phys_to_mem(priv->bdf, (u32)(rx_head + rx_swp)), + writel(dm_pci_phys_to_mem(priv->dev, (u32)(rx_head + rx_swp)), &mac_regs->rx_dsc_sw_p);
return 0; @@ -421,11 +421,8 @@ int pch_gbe_probe(struct udevice *dev) { struct pch_gbe_priv *priv; struct eth_pdata *plat = dev_get_platdata(dev); - pci_dev_t devno; u32 iobase;
- devno = dm_pci_get_bdf(dev); - /* * The priv structure contains the descriptors and frame buffers which * need a strict buswidth alignment (64 bytes). This is guaranteed by @@ -433,11 +430,11 @@ int pch_gbe_probe(struct udevice *dev) */ priv = dev_get_priv(dev);
- priv->bdf = devno; + priv->dev = dev;
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_1, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = pci_mem_to_phys(devno, iobase); + iobase = dm_pci_mem_to_phys(dev, iobase);
plat->iobase = iobase; priv->mac_regs = (struct pch_gbe_regs *)iobase; diff --git a/drivers/net/pch_gbe.h b/drivers/net/pch_gbe.h index afcb03d..0ea0c73 100644 --- a/drivers/net/pch_gbe.h +++ b/drivers/net/pch_gbe.h @@ -290,7 +290,7 @@ struct pch_gbe_priv { struct phy_device *phydev; struct mii_dev *bus; struct pch_gbe_regs *mac_regs; - pci_dev_t bdf; + struct udevice *dev; int rx_idx; int tx_idx; };
On 2 February 2016 at 06:57, Bin Meng bmeng.cn@gmail.com wrote:
Use native DM PCI APIs instead of legacy compatible ones.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/net/pch_gbe.c | 27 ++++++++++++--------------- drivers/net/pch_gbe.h | 2 +- 2 files changed, 13 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:57, Bin Meng bmeng.cn@gmail.com wrote:
Use native DM PCI APIs instead of legacy compatible ones.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/net/pch_gbe.c | 27 ++++++++++++--------------- drivers/net/pch_gbe.h | 2 +- 2 files changed, 13 insertions(+), 16 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
Convert to use native DM PCI API dm_pci_mem_to_phys().
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/net/designware.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 77b98c9..ca58f34 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -591,11 +591,9 @@ static int designware_eth_probe(struct udevice *dev) * or via a PCI bridge, fill in platdata before we probe the hardware. */ if (device_is_on_pci_bus(dev)) { - pci_dev_t bdf = dm_pci_get_bdf(dev); - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); iobase &= PCI_BASE_ADDRESS_MEM_MASK; - iobase = pci_mem_to_phys(bdf, iobase); + iobase = dm_pci_mem_to_phys(dev, iobase);
pdata->iobase = iobase; pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Convert to use native DM PCI API dm_pci_mem_to_phys().
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/net/designware.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Convert to use native DM PCI API dm_pci_mem_to_phys().
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/net/designware.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
Update this driver to use proper DM PCI APIs.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/net/e1000.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/net/e1000.h | 4 +++ 2 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 70fc02e..2f2185d 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -38,8 +38,13 @@ tested on both gig copper and gig fiber boards
#define TOUT_LOOP 100000
+#ifdef CONFIG_DM_ETH +#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v)) +#define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a) +#else #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v)) #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a) +#endif
#define E1000_DEFAULT_PCI_PBA 0x00000030 #define E1000_DEFAULT_PCIE_PBA 0x000a0026 @@ -1395,8 +1400,13 @@ e1000_reset_hw(struct e1000_hw *hw) /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, + hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#endif }
/* Clear interrupt mask to stop board from generating interrupts */ @@ -1469,7 +1479,11 @@ e1000_reset_hw(struct e1000_hw *hw)
/* If MWI was previously enabled, reenable it. */ if (hw->mac_type == e1000_82542_rev2_0) { +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#endif } if (hw->mac_type != e1000_igb) E1000_WRITE_REG(hw, PBA, pba); @@ -1655,9 +1669,15 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ if (hw->mac_type == e1000_82542_rev2_0) { DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, + hw-> + pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw-> pci_cmd_word & ~PCI_COMMAND_INVALIDATE); +#endif E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); E1000_WRITE_FLUSH(hw); mdelay(5); @@ -1673,7 +1693,11 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_FLUSH(hw); mdelay(1); +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#else pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); +#endif }
/* Zero out the Multicast HASH table */ @@ -1696,10 +1720,17 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) default: /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ if (hw->bus_type == e1000_bus_type_pcix) { +#ifdef CONFIG_DM_ETH + dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, + &pcix_cmd_word); + dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, + &pcix_stat_hi_word); +#else pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word); pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); +#endif cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; @@ -1711,8 +1742,13 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) if (cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; +#ifdef CONFIG_DM_ETH + dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, + pcix_cmd_word); +#else pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word); +#endif } } break; @@ -4809,6 +4845,16 @@ e1000_sw_init(struct e1000_hw *hw) int result;
/* PCI config space info */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); + dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); + dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, + &hw->subsystem_vendor_id); + dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); + + dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); + dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); +#else pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, @@ -4817,6 +4863,7 @@ e1000_sw_init(struct e1000_hw *hw)
pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); +#endif
/* identify the MAC */ result = e1000_set_mac_type(hw); @@ -5232,25 +5279,46 @@ void e1000_get_bus_type(struct e1000_hw *hw) static LIST_HEAD(e1000_hw_list); #endif
+#ifdef CONFIG_DM_ETH +static int e1000_init_one(struct e1000_hw *hw, int cardnum, + struct udevice *devno, unsigned char enetaddr[6]) +#else static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, unsigned char enetaddr[6]) +#endif { u32 val;
/* Assign the passed-in values */ +#ifdef CONFIG_DM_ETH hw->pdev = devno; +#else + hw->pdev = devno; +#endif hw->cardnum = cardnum;
/* Print a debug message with the IO base address */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val); +#else pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); +#endif E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
/* Try to enable I/O accesses and bus-mastering */ val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; +#ifdef CONFIG_DM_ETH + dm_pci_write_config32(devno, PCI_COMMAND, val); +#else pci_write_config_dword(devno, PCI_COMMAND, val); +#endif
/* Make sure it worked */ +#ifdef CONFIG_DM_ETH + dm_pci_read_config32(devno, PCI_COMMAND, &val); +#else pci_read_config_dword(devno, PCI_COMMAND, &val); +#endif if (!(val & PCI_COMMAND_MEMORY)) { E1000_ERR(hw, "Can't enable I/O memory\n"); return -ENOSPC; @@ -5269,8 +5337,13 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, #ifndef CONFIG_E1000_NO_NVM hw->eeprom_semaphore_present = true; #endif +#ifdef CONFIG_DM_ETH + hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); +#else hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); +#endif hw->mac_type = e1000_undefined;
/* MAC and Phy settings */ @@ -5554,7 +5627,7 @@ static int e1000_eth_probe(struct udevice *dev)
hw->name = dev->name; ret = e1000_init_one(hw, trailing_strtol(dev->name), - dm_pci_get_bdf(dev), plat->enetaddr); + dev, plat->enetaddr); if (ret < 0) { printf(pr_fmt("failed to initialize card: %d\n"), ret); return ret; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index e46edcd..fcb7df0 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -1084,7 +1084,11 @@ struct e1000_hw { #endif unsigned int cardnum;
+#ifdef CONFIG_DM_ETH + struct udevice *pdev; +#else pci_dev_t pdev; +#endif uint8_t *hw_addr; e1000_mac_type mac_type; e1000_phy_type phy_type;
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Update this driver to use proper DM PCI APIs.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/net/e1000.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/net/e1000.h | 4 +++ 2 files changed, 78 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Update this driver to use proper DM PCI APIs.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/net/e1000.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++- drivers/net/e1000.h | 4 +++ 2 files changed, 78 insertions(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
There are still two places in Quark's MRC codes that use the generic legacy PCI APIs, but as we are phasing out these legacy APIs, switch to use Quark's own PCI config routines.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/cpu/quark/mrc_util.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/quark/mrc_util.c b/arch/x86/cpu/quark/mrc_util.c index 49d803d..fac2d72 100644 --- a/arch/x86/cpu/quark/mrc_util.c +++ b/arch/x86/cpu/quark/mrc_util.c @@ -12,6 +12,7 @@ #include <asm/arch/device.h> #include <asm/arch/mrc.h> #include <asm/arch/msg_port.h> +#include <asm/arch/quark.h> #include "mrc_util.h" #include "hte.h" #include "smc.h" @@ -106,8 +107,8 @@ void select_hte(void) */ void dram_init_command(uint32_t data) { - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); - pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, data); + qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, 0); msg_port_setup(MSG_OP_DRAM_INIT, MEM_CTLR, 0);
DPF(D_REGWR, "WR32 %03X %08X %08X\n", MEM_CTLR, 0, data);
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
There are still two places in Quark's MRC codes that use the generic legacy PCI APIs, but as we are phasing out these legacy APIs, switch to use Quark's own PCI config routines.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/mrc_util.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
There are still two places in Quark's MRC codes that use the generic legacy PCI APIs, but as we are phasing out these legacy APIs, switch to use Quark's own PCI config routines.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/quark/mrc_util.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
Move some #undef from efi-x86.h to efi-x86_defconfig as these are already Kconfig options.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
configs/efi-x86_defconfig | 2 +- include/configs/efi-x86.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig index 943ef07..b4cbd5f 100644 --- a/configs/efi-x86_defconfig +++ b/configs/efi-x86_defconfig @@ -3,6 +3,7 @@ CONFIG_VENDOR_EFI=y CONFIG_DEFAULT_DEVICE_TREE="efi" CONFIG_TARGET_EFI=y # CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_IMLS is not set CONFIG_CMD_GPIO=y # CONFIG_CMD_NET is not set CONFIG_OF_CONTROL=y @@ -13,6 +14,5 @@ CONFIG_DEBUG_EFI_CONSOLE=y CONFIG_DEBUG_UART_BASE=0 CONFIG_DEBUG_UART_CLOCK=0 CONFIG_ICH_SPI=y -# CONFIG_X86_SERIAL is not set CONFIG_TIMER=y CONFIG_EFI=y diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 258a83f..7fb37f0 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -13,9 +13,6 @@
#undef CONFIG_TPM_TIS_BASE_ADDRESS
-#undef CONFIG_CMD_IMLS - -#undef CONFIG_X86_SERIAL #undef CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_NOWHERE #undef CONFIG_VIDEO
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Move some #undef from efi-x86.h to efi-x86_defconfig as these are already Kconfig options.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/efi-x86_defconfig | 2 +- include/configs/efi-x86.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Move some #undef from efi-x86.h to efi-x86_defconfig as these are already Kconfig options.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/efi-x86_defconfig | 2 +- include/configs/efi-x86.h | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
It does not build if without CONFIG_DM_PCI_COMPAT. For now we just disable it, until some day we add USB support to EFI application.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/configs/efi-x86.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/efi-x86.h b/include/configs/efi-x86.h index 7fb37f0..6dd0b32 100644 --- a/include/configs/efi-x86.h +++ b/include/configs/efi-x86.h @@ -20,6 +20,7 @@ #undef CONFIG_SCSI_AHCI #undef CONFIG_CMD_SCSI #undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_USB_EHCI_PCI
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ "stdout=vga,serial\0" \
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
It does not build if without CONFIG_DM_PCI_COMPAT. For now we just disable it, until some day we add USB support to EFI application.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/configs/efi-x86.h | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
It does not build if without CONFIG_DM_PCI_COMPAT. For now we just disable it, until some day we add USB support to EFI application.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/configs/efi-x86.h | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
Now that the RTL8169 driver warning is fixed we can drop this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/configs/chromebox_panther.h | 2 -- 1 file changed, 2 deletions(-)
diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h index 00fe26d..d5b3390 100644 --- a/include/configs/chromebox_panther.h +++ b/include/configs/chromebox_panther.h @@ -11,7 +11,5 @@ #include <configs/x86-chromebook.h>
#define CONFIG_RTL8169 -/* Avoid a warning in the Realtek Ethernet driver */ -#define CONFIG_SYS_CACHELINE_SIZE 16
#endif /* __CONFIG_H */
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Now that the RTL8169 driver warning is fixed we can drop this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/configs/chromebox_panther.h | 2 -- 1 file changed, 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Now that the RTL8169 driver warning is fixed we can drop this.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/configs/chromebox_panther.h | 2 -- 1 file changed, 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
This board uses RTL8169 which is a driver model ethernet driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
configs/chromebox_panther_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig index e4a3821..6e851cc 100644 --- a/configs/chromebox_panther_defconfig +++ b/configs/chromebox_panther_defconfig @@ -25,6 +25,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_SYS_NS16550=y
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
This board uses RTL8169 which is a driver model ethernet driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/chromebox_panther_defconfig | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:27 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
This board uses RTL8169 which is a driver model ethernet driver.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/chromebox_panther_defconfig | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
include/pci.h | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/include/pci.h b/include/pci.h index d0d152c..68548b0 100644 --- a/include/pci.h +++ b/include/pci.h @@ -1050,6 +1050,11 @@ int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); * functions, rather than byte/word/dword. But both are supported. */ int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); +int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); +int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); +int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); +int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); +int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
#ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ @@ -1059,8 +1064,6 @@ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, return pci_write_config32(pcidev, offset, value); }
-int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); - /* Compatibility with old naming */ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, u16 value) @@ -1068,8 +1071,6 @@ static inline int pci_write_config_word(pci_dev_t pcidev, int offset, return pci_write_config16(pcidev, offset, value); }
-int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); - /* Compatibility with old naming */ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, u8 value) @@ -1077,8 +1078,6 @@ static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, return pci_write_config8(pcidev, offset, value); }
-int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, u32 *valuep) @@ -1086,8 +1085,6 @@ static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, return pci_read_config32(pcidev, offset, valuep); }
-int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, u16 *valuep) @@ -1095,15 +1092,12 @@ static inline int pci_read_config_word(pci_dev_t pcidev, int offset, return pci_read_config16(pcidev, offset, valuep); }
-int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); - /* Compatibility with old naming */ static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, u8 *valuep) { return pci_read_config8(pcidev, offset, valuep); } - #endif /* CONFIG_DM_PCI_COMPAT */
/**
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/pci.h | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:28 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
When CONFIG_DM_PCI_COMPAT is not on, there is only a forward declaration for pci_write_config32(). Add other missing ones.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
include/pci.h | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
Now that all x86 codes have been converted to use proper DM PCI APIs, it's time to disable the legacy compatible layer.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
arch/x86/Kconfig | 3 --- 1 file changed, 3 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index a995e32..49e173c 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -93,9 +93,6 @@ config SYS_X86_START16 depends on X86_RESET_VECTOR default 0xfffff800
-config DM_PCI_COMPAT - default y # Until we finish moving over to the new API - config BOARD_ROMSIZE_KB_512 bool config BOARD_ROMSIZE_KB_1024
Hi Bin,
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Now that all x86 codes have been converted to use proper DM PCI APIs, it's time to disable the legacy compatible layer.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/Kconfig | 3 --- 1 file changed, 3 deletions(-)
Wow you were super-fast with this one!
Regards, Simon
On Tue, Feb 2, 2016 at 9:58 PM, Bin Meng bmeng.cn@gmail.com wrote:
Now that all x86 codes have been converted to use proper DM PCI APIs, it's time to disable the legacy compatible layer.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/Kconfig | 3 --- 1 file changed, 3 deletions(-)
applied to u-boot-x86/master, thanks!
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c which is only built for legacy PCI. Also per checkpatch.pl warning, DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
arch/x86/include/asm/pci.h | 7 ------- arch/x86/lib/Makefile | 3 --- arch/x86/lib/pci_type1.c | 50 ---------------------------------------------- 3 files changed, 60 deletions(-) delete mode 100644 arch/x86/lib/pci_type1.c
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 46b992e..f93c840 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -18,13 +18,6 @@
#ifndef __ASSEMBLY__
-#define DEFINE_PCI_DEVICE_TABLE(_table) \ - const struct pci_device_id _table[] - -struct pci_controller; - -void pci_setup_type1(struct pci_controller *hose); - int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size);
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 50bc69a..4fc1936 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -22,9 +22,6 @@ obj-y += cmd_mtrr.o obj-y += northbridge-uclass.o obj-$(CONFIG_I8259_PIC) += i8259.o obj-$(CONFIG_I8254_TIMER) += i8254.o -ifndef CONFIG_DM_PCI -obj-$(CONFIG_PCI) += pci_type1.o -endif obj-y += pirq_routing.o obj-y += relocate.o obj-y += physmem.o diff --git a/arch/x86/lib/pci_type1.c b/arch/x86/lib/pci_type1.c deleted file mode 100644 index a251adc..0000000 --- a/arch/x86/lib/pci_type1.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Support for type PCI configuration cycles. - * based on pci_indirect.c - */ -#include <common.h> -#include <asm/io.h> -#include <pci.h> -#include <asm/pci.h> - -#define cfg_read(val, addr, op) (*val = op((int)(addr))) -#define cfg_write(val, addr, op) op((val), (int)(addr)) - -#define TYPE1_PCI_OP(rw, size, type, op, mask) \ -static int \ -type1_##rw##_config_##size(struct pci_controller *hose, \ - pci_dev_t dev, int offset, type val) \ -{ \ - outl(dev | (offset & 0xfc) | PCI_CFG_EN, (int)hose->cfg_addr); \ - cfg_##rw(val, hose->cfg_data + (offset & mask), op); \ - return 0; \ -} - -TYPE1_PCI_OP(read, byte, u8 *, inb, 3) -TYPE1_PCI_OP(read, word, u16 *, inw, 2) -TYPE1_PCI_OP(read, dword, u32 *, inl, 0) - -TYPE1_PCI_OP(write, byte, u8, outb, 3) -TYPE1_PCI_OP(write, word, u16, outw, 2) -TYPE1_PCI_OP(write, dword, u32, outl, 0) - -void pci_setup_type1(struct pci_controller *hose) -{ - pci_set_ops(hose, - type1_read_config_byte, - type1_read_config_word, - type1_read_config_dword, - type1_write_config_byte, - type1_write_config_word, - type1_write_config_dword); - - hose->cfg_addr = (unsigned int *)PCI_REG_ADDR; - hose->cfg_data = (unsigned char *)PCI_REG_DATA; -}
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c which is only built for legacy PCI. Also per checkpatch.pl warning, DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/include/asm/pci.h | 7 ------- arch/x86/lib/Makefile | 3 --- arch/x86/lib/pci_type1.c | 50 ---------------------------------------------- 3 files changed, 60 deletions(-) delete mode 100644 arch/x86/lib/pci_type1.c
Reviewed-by: Simon Glass sjg@chromium.org
On Wed, Feb 3, 2016 at 11:28 AM, Simon Glass sjg@chromium.org wrote:
On 2 February 2016 at 06:58, Bin Meng bmeng.cn@gmail.com wrote:
Now that we have converted all x86 codes to DM PCI, drop pci_type1.c which is only built for legacy PCI. Also per checkpatch.pl warning, DEFINE_PCI_DEVICE_TABLE is now deprecated so drop that too.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/include/asm/pci.h | 7 ------- arch/x86/lib/Makefile | 3 --- arch/x86/lib/pci_type1.c | 50 ---------------------------------------------- 3 files changed, 60 deletions(-) delete mode 100644 arch/x86/lib/pci_type1.c
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86/master, thanks!
participants (2)
-
Bin Meng -
Simon Glass