[U-Boot] [PATCH v6 0/3] Adds support for Exynos5422 odroid xu3 board
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ v5: https://patchwork.ozlabs.org/patch/407941/
This patchset fixes GPIO information of Exynos5420 which is needed to support Exynos5422 Odroid XU3 board. On the base of the fixes, this patchset adds support for Exynos5422 Odroid XU3 board. I have done this work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1: 26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat.
link: https://patchwork.ozlabs.org/patch/405246/ (updated)
How to test this patch: 1. git clone http://git.denx.de/u-boot-samsung.git 2. git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370 3. Get and apply the patchset of Akshay Saraswat https://patchwork.ozlabs.org/patch/405246/ https://patchwork.ozlabs.org/patch/405247/ https://patchwork.ozlabs.org/patch/405248/ https://patchwork.ozlabs.org/patch/405249/ https://patchwork.ozlabs.org/patch/405250/ https://patchwork.ozlabs.org/patch/405251/ https://patchwork.ozlabs.org/patch/405252/ 4. Apply this patchset 5. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config 6. make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8 7. Now you can use u-boot-dtb.bin for your downloading
Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id.
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SECURE_BL1_ONLY
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \ - "if test -e mmc 0 Image.itb; then; " \ + "if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ + "elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ + "elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ + "mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
Changes for v2: - Add a patch to add new common setup header file for Odroid X2/U3 and Odroid XU3
Changes for v3: - Remove the patch which adds new common setup header file from v2 - Remove the wrong patch to fix GPIO information of Exynos 5800 - Remove unnecessary node from DT file - Remove unnecessary features from config file - Fix some trivial typos in comments
Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file
Changes for v5: - Add the specific build instruction - Update the information of patchset by Akshay Saraswat - Convert /include/ to #include in DT file
Chagnes for v6: - Separate out the documentation to new commit - Remove unnecessary header file inclusuib from the board-specific setup file - Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
Hyungwon Hwang (3): exynos5: fix GPIO information of exynos5420 Odroid-XU3: Add support for Odroid-XU3 Odroid-XU3: Add documentation for Odroid-XU3
arch/arm/cpu/armv7/exynos/Kconfig | 5 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 60 +++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- board/samsung/odroid-xu3/Kconfig | 12 ++ board/samsung/odroid-xu3/MAINTAINERS | 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 122 +++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 +++++++++++++ configs/odroid-xu3_defconfig | 4 + doc/README.odroid-xu3 | 134 ++++++++++++++++++ include/configs/odroid_xu3.h | 144 ++++++++++++++++++++ 13 files changed, 708 insertions(+), 127 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 doc/README.odroid-xu3 create mode 100644 include/configs/odroid_xu3.h
This patch fixes wrong GPIO information such as GPIO bank, table which is used to convert GPIO name to index, bank base address, and etc.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com --- Changes for v4: - None
Changes for v5: - None
Changes for v6: - None
arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- 2 files changed, 117 insertions(+), 126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 29674ad..48936de 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -148,7 +148,7 @@
/* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 #define EXYNOS5420_PRO_ID 0x10000000 #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 @@ -170,11 +170,10 @@ #define EXYNOS5420_I2S_BASE 0x12D60000 #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 -#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 -#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 +#define EXYNOS5420_GPIO_PART1_BASE 0x13400000 +#define EXYNOS5420_GPIO_PART2_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART3_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART4_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 9699954..aef897d 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1042,83 +1042,7 @@ enum exynos5_gpio_pin { };
enum exynos5420_gpio_pin { - /* GPIO_PART1_STARTS */ - EXYNOS5420_GPIO_A00, /* 0 */ - EXYNOS5420_GPIO_A01, - EXYNOS5420_GPIO_A02, - EXYNOS5420_GPIO_A03, - EXYNOS5420_GPIO_A04, - EXYNOS5420_GPIO_A05, - EXYNOS5420_GPIO_A06, - EXYNOS5420_GPIO_A07, - EXYNOS5420_GPIO_A10, /* 8 */ - EXYNOS5420_GPIO_A11, - EXYNOS5420_GPIO_A12, - EXYNOS5420_GPIO_A13, - EXYNOS5420_GPIO_A14, - EXYNOS5420_GPIO_A15, - EXYNOS5420_GPIO_A16, - EXYNOS5420_GPIO_A17, - EXYNOS5420_GPIO_A20, /* 16 0x10 */ - EXYNOS5420_GPIO_A21, - EXYNOS5420_GPIO_A22, - EXYNOS5420_GPIO_A23, - EXYNOS5420_GPIO_A24, - EXYNOS5420_GPIO_A25, - EXYNOS5420_GPIO_A26, - EXYNOS5420_GPIO_A27, - EXYNOS5420_GPIO_B00, /* 24 0x18 */ - EXYNOS5420_GPIO_B01, - EXYNOS5420_GPIO_B02, - EXYNOS5420_GPIO_B03, - EXYNOS5420_GPIO_B04, - EXYNOS5420_GPIO_B05, - EXYNOS5420_GPIO_B06, - EXYNOS5420_GPIO_B07, - EXYNOS5420_GPIO_B10, /* 32 0x20 */ - EXYNOS5420_GPIO_B11, - EXYNOS5420_GPIO_B12, - EXYNOS5420_GPIO_B13, - EXYNOS5420_GPIO_B14, - EXYNOS5420_GPIO_B15, - EXYNOS5420_GPIO_B16, - EXYNOS5420_GPIO_B17, - EXYNOS5420_GPIO_B20, /* 40 0x28 */ - EXYNOS5420_GPIO_B21, - EXYNOS5420_GPIO_B22, - EXYNOS5420_GPIO_B23, - EXYNOS5420_GPIO_B24, - EXYNOS5420_GPIO_B25, - EXYNOS5420_GPIO_B26, - EXYNOS5420_GPIO_B27, - EXYNOS5420_GPIO_B30, /* 48 0x30 */ - EXYNOS5420_GPIO_B31, - EXYNOS5420_GPIO_B32, - EXYNOS5420_GPIO_B33, - EXYNOS5420_GPIO_B34, - EXYNOS5420_GPIO_B35, - EXYNOS5420_GPIO_B36, - EXYNOS5420_GPIO_B37, - EXYNOS5420_GPIO_B40, /* 56 0x38 */ - EXYNOS5420_GPIO_B41, - EXYNOS5420_GPIO_B42, - EXYNOS5420_GPIO_B43, - EXYNOS5420_GPIO_B44, - EXYNOS5420_GPIO_B45, - EXYNOS5420_GPIO_B46, - EXYNOS5420_GPIO_B47, - EXYNOS5420_GPIO_H00, /* 64 0x40 */ - EXYNOS5420_GPIO_H01, - EXYNOS5420_GPIO_H02, - EXYNOS5420_GPIO_H03, - EXYNOS5420_GPIO_H04, - EXYNOS5420_GPIO_H05, - EXYNOS5420_GPIO_H06, - EXYNOS5420_GPIO_H07, - - /* GPIO PART 2 STARTS*/ - EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */ - EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_Y70, EXYNOS5420_GPIO_Y71, EXYNOS5420_GPIO_Y72, EXYNOS5420_GPIO_Y73, @@ -1126,10 +1050,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y75, EXYNOS5420_GPIO_Y76, EXYNOS5420_GPIO_Y77, - - /* GPIO PART 3 STARTS*/ - EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */ - EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_X01, EXYNOS5420_GPIO_X02, EXYNOS5420_GPIO_X03, @@ -1137,7 +1058,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X05, EXYNOS5420_GPIO_X06, EXYNOS5420_GPIO_X07, - EXYNOS5420_GPIO_X10, /* 88 0x58 */ + EXYNOS5420_GPIO_X10, EXYNOS5420_GPIO_X11, EXYNOS5420_GPIO_X12, EXYNOS5420_GPIO_X13, @@ -1145,7 +1066,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X15, EXYNOS5420_GPIO_X16, EXYNOS5420_GPIO_X17, - EXYNOS5420_GPIO_X20, /* 96 0x60 */ + EXYNOS5420_GPIO_X20, EXYNOS5420_GPIO_X21, EXYNOS5420_GPIO_X22, EXYNOS5420_GPIO_X23, @@ -1153,7 +1074,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X25, EXYNOS5420_GPIO_X26, EXYNOS5420_GPIO_X27, - EXYNOS5420_GPIO_X30, /* 104 0x68 */ + EXYNOS5420_GPIO_X30, EXYNOS5420_GPIO_X31, EXYNOS5420_GPIO_X32, EXYNOS5420_GPIO_X33, @@ -1162,9 +1083,8 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X36, EXYNOS5420_GPIO_X37,
- /* GPIO PART 4 STARTS*/ - EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */ - EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_MAX_PORT_PART_1, + EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_1, EXYNOS5420_GPIO_C01, EXYNOS5420_GPIO_C02, EXYNOS5420_GPIO_C03, @@ -1172,7 +1092,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C05, EXYNOS5420_GPIO_C06, EXYNOS5420_GPIO_C07, - EXYNOS5420_GPIO_C10, /* 120 0x78 */ + EXYNOS5420_GPIO_C10, EXYNOS5420_GPIO_C11, EXYNOS5420_GPIO_C12, EXYNOS5420_GPIO_C13, @@ -1180,7 +1100,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C15, EXYNOS5420_GPIO_C16, EXYNOS5420_GPIO_C17, - EXYNOS5420_GPIO_C20, /* 128 0x80 */ + EXYNOS5420_GPIO_C20, EXYNOS5420_GPIO_C21, EXYNOS5420_GPIO_C22, EXYNOS5420_GPIO_C23, @@ -1188,7 +1108,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C25, EXYNOS5420_GPIO_C26, EXYNOS5420_GPIO_C27, - EXYNOS5420_GPIO_C30, /* 136 0x88 */ + EXYNOS5420_GPIO_C30, EXYNOS5420_GPIO_C31, EXYNOS5420_GPIO_C32, EXYNOS5420_GPIO_C33, @@ -1196,7 +1116,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C35, EXYNOS5420_GPIO_C36, EXYNOS5420_GPIO_C37, - EXYNOS5420_GPIO_C40, /* 144 0x90 */ + EXYNOS5420_GPIO_C40, EXYNOS5420_GPIO_C41, EXYNOS5420_GPIO_C42, EXYNOS5420_GPIO_C43, @@ -1204,7 +1124,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C45, EXYNOS5420_GPIO_C46, EXYNOS5420_GPIO_C47, - EXYNOS5420_GPIO_D10, /* 152 0x98 */ + EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_D11, EXYNOS5420_GPIO_D12, EXYNOS5420_GPIO_D13, @@ -1212,7 +1132,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_D15, EXYNOS5420_GPIO_D16, EXYNOS5420_GPIO_D17, - EXYNOS5420_GPIO_Y00, /* 160 0xa0 */ + EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_Y01, EXYNOS5420_GPIO_Y02, EXYNOS5420_GPIO_Y03, @@ -1220,7 +1140,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y05, EXYNOS5420_GPIO_Y06, EXYNOS5420_GPIO_Y07, - EXYNOS5420_GPIO_Y10, /* 168 0xa8 */ + EXYNOS5420_GPIO_Y10, EXYNOS5420_GPIO_Y11, EXYNOS5420_GPIO_Y12, EXYNOS5420_GPIO_Y13, @@ -1228,7 +1148,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y15, EXYNOS5420_GPIO_Y16, EXYNOS5420_GPIO_Y17, - EXYNOS5420_GPIO_Y20, /* 176 0xb0 */ + EXYNOS5420_GPIO_Y20, EXYNOS5420_GPIO_Y21, EXYNOS5420_GPIO_Y22, EXYNOS5420_GPIO_Y23, @@ -1236,7 +1156,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y25, EXYNOS5420_GPIO_Y26, EXYNOS5420_GPIO_Y27, - EXYNOS5420_GPIO_Y30, /* 184 0xb8 */ + EXYNOS5420_GPIO_Y30, EXYNOS5420_GPIO_Y31, EXYNOS5420_GPIO_Y32, EXYNOS5420_GPIO_Y33, @@ -1244,7 +1164,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y35, EXYNOS5420_GPIO_Y36, EXYNOS5420_GPIO_Y37, - EXYNOS5420_GPIO_Y40, /* 192 0xc0 */ + EXYNOS5420_GPIO_Y40, EXYNOS5420_GPIO_Y41, EXYNOS5420_GPIO_Y42, EXYNOS5420_GPIO_Y43, @@ -1252,7 +1172,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y45, EXYNOS5420_GPIO_Y46, EXYNOS5420_GPIO_Y47, - EXYNOS5420_GPIO_Y50, /* 200 0xc8 */ + EXYNOS5420_GPIO_Y50, EXYNOS5420_GPIO_Y51, EXYNOS5420_GPIO_Y52, EXYNOS5420_GPIO_Y53, @@ -1260,7 +1180,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y55, EXYNOS5420_GPIO_Y56, EXYNOS5420_GPIO_Y57, - EXYNOS5420_GPIO_Y60, /* 208 0xd0 */ + EXYNOS5420_GPIO_Y60, EXYNOS5420_GPIO_Y61, EXYNOS5420_GPIO_Y62, EXYNOS5420_GPIO_Y63, @@ -1269,9 +1189,8 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y66, EXYNOS5420_GPIO_Y67,
- /* GPIO_PART5_STARTS */ - EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */ - EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_MAX_PORT_PART_2, + EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, EXYNOS5420_GPIO_E01, EXYNOS5420_GPIO_E02, EXYNOS5420_GPIO_E03, @@ -1279,7 +1198,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_E05, EXYNOS5420_GPIO_E06, EXYNOS5420_GPIO_E07, - EXYNOS5420_GPIO_E10, /* 224 0xe0 */ + EXYNOS5420_GPIO_E10, EXYNOS5420_GPIO_E11, EXYNOS5420_GPIO_E12, EXYNOS5420_GPIO_E13, @@ -1287,7 +1206,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_E15, EXYNOS5420_GPIO_E16, EXYNOS5420_GPIO_E17, - EXYNOS5420_GPIO_F00, /* 232 0xe8 */ + EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_F01, EXYNOS5420_GPIO_F02, EXYNOS5420_GPIO_F03, @@ -1295,7 +1214,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_F05, EXYNOS5420_GPIO_F06, EXYNOS5420_GPIO_F07, - EXYNOS5420_GPIO_F10, /* 240 0xf0 */ + EXYNOS5420_GPIO_F10, EXYNOS5420_GPIO_F11, EXYNOS5420_GPIO_F12, EXYNOS5420_GPIO_F13, @@ -1303,7 +1222,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_F15, EXYNOS5420_GPIO_F16, EXYNOS5420_GPIO_F17, - EXYNOS5420_GPIO_G00, /* 248 0xf8 */ + EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_G01, EXYNOS5420_GPIO_G02, EXYNOS5420_GPIO_G03, @@ -1311,7 +1230,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G05, EXYNOS5420_GPIO_G06, EXYNOS5420_GPIO_G07, - EXYNOS5420_GPIO_G10, /* 256 0x100 */ + EXYNOS5420_GPIO_G10, EXYNOS5420_GPIO_G11, EXYNOS5420_GPIO_G12, EXYNOS5420_GPIO_G13, @@ -1319,7 +1238,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G15, EXYNOS5420_GPIO_G16, EXYNOS5420_GPIO_G17, - EXYNOS5420_GPIO_G20, /* 264 0x108 */ + EXYNOS5420_GPIO_G20, EXYNOS5420_GPIO_G21, EXYNOS5420_GPIO_G22, EXYNOS5420_GPIO_G23, @@ -1327,7 +1246,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G25, EXYNOS5420_GPIO_G26, EXYNOS5420_GPIO_G27, - EXYNOS5420_GPIO_J40, /* 272 0x110 */ + EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_J41, EXYNOS5420_GPIO_J42, EXYNOS5420_GPIO_J43, @@ -1336,15 +1255,89 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_J46, EXYNOS5420_GPIO_J47,
- /* GPIO_PART6_STARTS */ - EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */ - EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5, + EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_A00 = EXYNOS5420_GPIO_MAX_PORT_PART_3, + EXYNOS5420_GPIO_A01, + EXYNOS5420_GPIO_A02, + EXYNOS5420_GPIO_A03, + EXYNOS5420_GPIO_A04, + EXYNOS5420_GPIO_A05, + EXYNOS5420_GPIO_A06, + EXYNOS5420_GPIO_A07, + EXYNOS5420_GPIO_A10, + EXYNOS5420_GPIO_A11, + EXYNOS5420_GPIO_A12, + EXYNOS5420_GPIO_A13, + EXYNOS5420_GPIO_A14, + EXYNOS5420_GPIO_A15, + EXYNOS5420_GPIO_A16, + EXYNOS5420_GPIO_A17, + EXYNOS5420_GPIO_A20, + EXYNOS5420_GPIO_A21, + EXYNOS5420_GPIO_A22, + EXYNOS5420_GPIO_A23, + EXYNOS5420_GPIO_A24, + EXYNOS5420_GPIO_A25, + EXYNOS5420_GPIO_A26, + EXYNOS5420_GPIO_A27, + EXYNOS5420_GPIO_B00, + EXYNOS5420_GPIO_B01, + EXYNOS5420_GPIO_B02, + EXYNOS5420_GPIO_B03, + EXYNOS5420_GPIO_B04, + EXYNOS5420_GPIO_B05, + EXYNOS5420_GPIO_B06, + EXYNOS5420_GPIO_B07, + EXYNOS5420_GPIO_B10, + EXYNOS5420_GPIO_B11, + EXYNOS5420_GPIO_B12, + EXYNOS5420_GPIO_B13, + EXYNOS5420_GPIO_B14, + EXYNOS5420_GPIO_B15, + EXYNOS5420_GPIO_B16, + EXYNOS5420_GPIO_B17, + EXYNOS5420_GPIO_B20, + EXYNOS5420_GPIO_B21, + EXYNOS5420_GPIO_B22, + EXYNOS5420_GPIO_B23, + EXYNOS5420_GPIO_B24, + EXYNOS5420_GPIO_B25, + EXYNOS5420_GPIO_B26, + EXYNOS5420_GPIO_B27, + EXYNOS5420_GPIO_B30, + EXYNOS5420_GPIO_B31, + EXYNOS5420_GPIO_B32, + EXYNOS5420_GPIO_B33, + EXYNOS5420_GPIO_B34, + EXYNOS5420_GPIO_B35, + EXYNOS5420_GPIO_B36, + EXYNOS5420_GPIO_B37, + EXYNOS5420_GPIO_B40, + EXYNOS5420_GPIO_B41, + EXYNOS5420_GPIO_B42, + EXYNOS5420_GPIO_B43, + EXYNOS5420_GPIO_B44, + EXYNOS5420_GPIO_B45, + EXYNOS5420_GPIO_B46, + EXYNOS5420_GPIO_B47, + EXYNOS5420_GPIO_H00, + EXYNOS5420_GPIO_H01, + EXYNOS5420_GPIO_H02, + EXYNOS5420_GPIO_H03, + EXYNOS5420_GPIO_H04, + EXYNOS5420_GPIO_H05, + EXYNOS5420_GPIO_H06, + EXYNOS5420_GPIO_H07, + + EXYNOS5420_GPIO_MAX_PORT_PART_4, + EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_4, EXYNOS5420_GPIO_Z1, EXYNOS5420_GPIO_Z2, EXYNOS5420_GPIO_Z3, EXYNOS5420_GPIO_Z4, EXYNOS5420_GPIO_Z5, EXYNOS5420_GPIO_Z6, + EXYNOS5420_GPIO_MAX_PORT };
@@ -1385,14 +1378,13 @@ static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, };
-#define EXYNOS5420_GPIO_NUM_PARTS 6 +#define EXYNOS5420_GPIO_NUM_PARTS 5 static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 }, - { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 }, - { EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT }, + { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, };
static inline struct gpio_info *get_gpio_data(void) @@ -1505,17 +1497,17 @@ static const struct gpio_name_num_table exynos5_gpio_table[] = { };
static const struct gpio_name_num_table exynos5420_gpio_table[] = { - GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), - GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), - GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0), - GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010), + GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0), GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0), - GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040), + GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0), + GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0), + GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0), + GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0), GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0), { 0 } };
Hi Hyungwon,
This patch fixes wrong GPIO information such as GPIO bank, table which is used to convert GPIO name to index, bank base address, and etc.
Please check if you sent your patches as a plain text.
To apply your patches without problems I had to use "mbox" from patchwork. (e.g. http://patchwork.ozlabs.org/patch/408649/)
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v4:
- None
Changes for v5:
- None
Changes for v6:
- None
arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 232 +++++++++++++++----------------- 2 files changed, 117 insertions(+), 126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 29674ad..48936de 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -148,7 +148,7 @@
/* EXYNOS5420 */ #define EXYNOS5420_AUDIOSS_BASE 0x03810000 -#define EXYNOS5420_GPIO_PART6_BASE 0x03860000 +#define EXYNOS5420_GPIO_PART5_BASE 0x03860000 #define EXYNOS5420_PRO_ID 0x10000000 #define EXYNOS5420_CLOCK_BASE 0x10010000 #define EXYNOS5420_POWER_BASE 0x10040000 @@ -170,11 +170,10 @@ #define EXYNOS5420_I2S_BASE 0x12D60000 #define EXYNOS5420_PWMTIMER_BASE 0x12DD0000 #define EXYNOS5420_SPI_ISP_BASE 0x131A0000 -#define EXYNOS5420_GPIO_PART2_BASE 0x13400000 -#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00 -#define EXYNOS5420_GPIO_PART4_BASE 0x13410000 -#define EXYNOS5420_GPIO_PART5_BASE 0x14000000 -#define EXYNOS5420_GPIO_PART1_BASE 0x14010000 +#define EXYNOS5420_GPIO_PART1_BASE 0x13400000 +#define EXYNOS5420_GPIO_PART2_BASE 0x13410000 +#define EXYNOS5420_GPIO_PART3_BASE 0x14000000 +#define EXYNOS5420_GPIO_PART4_BASE 0x14010000 #define EXYNOS5420_MIPI_DSIM_BASE 0x14500000 #define EXYNOS5420_DP_BASE 0x145B0000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 9699954..aef897d 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -1042,83 +1042,7 @@ enum exynos5_gpio_pin { };
enum exynos5420_gpio_pin {
/* GPIO_PART1_STARTS */EXYNOS5420_GPIO_A00, /* 0 */EXYNOS5420_GPIO_A01,EXYNOS5420_GPIO_A02,EXYNOS5420_GPIO_A03,EXYNOS5420_GPIO_A04,EXYNOS5420_GPIO_A05,EXYNOS5420_GPIO_A06,EXYNOS5420_GPIO_A07,EXYNOS5420_GPIO_A10, /* 8 */EXYNOS5420_GPIO_A11,EXYNOS5420_GPIO_A12,EXYNOS5420_GPIO_A13,EXYNOS5420_GPIO_A14,EXYNOS5420_GPIO_A15,EXYNOS5420_GPIO_A16,EXYNOS5420_GPIO_A17,EXYNOS5420_GPIO_A20, /* 16 0x10 */EXYNOS5420_GPIO_A21,EXYNOS5420_GPIO_A22,EXYNOS5420_GPIO_A23,EXYNOS5420_GPIO_A24,EXYNOS5420_GPIO_A25,EXYNOS5420_GPIO_A26,EXYNOS5420_GPIO_A27,EXYNOS5420_GPIO_B00, /* 24 0x18 */EXYNOS5420_GPIO_B01,EXYNOS5420_GPIO_B02,EXYNOS5420_GPIO_B03,EXYNOS5420_GPIO_B04,EXYNOS5420_GPIO_B05,EXYNOS5420_GPIO_B06,EXYNOS5420_GPIO_B07,EXYNOS5420_GPIO_B10, /* 32 0x20 */EXYNOS5420_GPIO_B11,EXYNOS5420_GPIO_B12,EXYNOS5420_GPIO_B13,EXYNOS5420_GPIO_B14,EXYNOS5420_GPIO_B15,EXYNOS5420_GPIO_B16,EXYNOS5420_GPIO_B17,EXYNOS5420_GPIO_B20, /* 40 0x28 */EXYNOS5420_GPIO_B21,EXYNOS5420_GPIO_B22,EXYNOS5420_GPIO_B23,EXYNOS5420_GPIO_B24,EXYNOS5420_GPIO_B25,EXYNOS5420_GPIO_B26,EXYNOS5420_GPIO_B27,EXYNOS5420_GPIO_B30, /* 48 0x30 */EXYNOS5420_GPIO_B31,EXYNOS5420_GPIO_B32,EXYNOS5420_GPIO_B33,EXYNOS5420_GPIO_B34,EXYNOS5420_GPIO_B35,EXYNOS5420_GPIO_B36,EXYNOS5420_GPIO_B37,EXYNOS5420_GPIO_B40, /* 56 0x38 */EXYNOS5420_GPIO_B41,EXYNOS5420_GPIO_B42,EXYNOS5420_GPIO_B43,EXYNOS5420_GPIO_B44,EXYNOS5420_GPIO_B45,EXYNOS5420_GPIO_B46,EXYNOS5420_GPIO_B47,EXYNOS5420_GPIO_H00, /* 64 0x40 */EXYNOS5420_GPIO_H01,EXYNOS5420_GPIO_H02,EXYNOS5420_GPIO_H03,EXYNOS5420_GPIO_H04,EXYNOS5420_GPIO_H05,EXYNOS5420_GPIO_H06,EXYNOS5420_GPIO_H07,/* GPIO PART 2 STARTS*/EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
EXYNOS5420_GPIO_Y70, EXYNOS5420_GPIO_Y71, EXYNOS5420_GPIO_Y72, EXYNOS5420_GPIO_Y73,@@ -1126,10 +1050,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y75, EXYNOS5420_GPIO_Y76, EXYNOS5420_GPIO_Y77,
/* GPIO PART 3 STARTS*/EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_X01, EXYNOS5420_GPIO_X02, EXYNOS5420_GPIO_X03,@@ -1137,7 +1058,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X05, EXYNOS5420_GPIO_X06, EXYNOS5420_GPIO_X07,
EXYNOS5420_GPIO_X10, /* 88 0x58 */
EXYNOS5420_GPIO_X10, EXYNOS5420_GPIO_X11, EXYNOS5420_GPIO_X12, EXYNOS5420_GPIO_X13,@@ -1145,7 +1066,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X15, EXYNOS5420_GPIO_X16, EXYNOS5420_GPIO_X17,
EXYNOS5420_GPIO_X20, /* 96 0x60 */
EXYNOS5420_GPIO_X20, EXYNOS5420_GPIO_X21, EXYNOS5420_GPIO_X22, EXYNOS5420_GPIO_X23,@@ -1153,7 +1074,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X25, EXYNOS5420_GPIO_X26, EXYNOS5420_GPIO_X27,
EXYNOS5420_GPIO_X30, /* 104 0x68 */
EXYNOS5420_GPIO_X30, EXYNOS5420_GPIO_X31, EXYNOS5420_GPIO_X32, EXYNOS5420_GPIO_X33,@@ -1162,9 +1083,8 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_X36, EXYNOS5420_GPIO_X37,
/* GPIO PART 4 STARTS*/EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
EXYNOS5420_GPIO_MAX_PORT_PART_1,EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_1, EXYNOS5420_GPIO_C01, EXYNOS5420_GPIO_C02, EXYNOS5420_GPIO_C03,@@ -1172,7 +1092,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C05, EXYNOS5420_GPIO_C06, EXYNOS5420_GPIO_C07,
EXYNOS5420_GPIO_C10, /* 120 0x78 */
EXYNOS5420_GPIO_C10, EXYNOS5420_GPIO_C11, EXYNOS5420_GPIO_C12, EXYNOS5420_GPIO_C13,@@ -1180,7 +1100,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C15, EXYNOS5420_GPIO_C16, EXYNOS5420_GPIO_C17,
EXYNOS5420_GPIO_C20, /* 128 0x80 */
EXYNOS5420_GPIO_C20, EXYNOS5420_GPIO_C21, EXYNOS5420_GPIO_C22, EXYNOS5420_GPIO_C23,@@ -1188,7 +1108,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C25, EXYNOS5420_GPIO_C26, EXYNOS5420_GPIO_C27,
EXYNOS5420_GPIO_C30, /* 136 0x88 */
EXYNOS5420_GPIO_C30, EXYNOS5420_GPIO_C31, EXYNOS5420_GPIO_C32, EXYNOS5420_GPIO_C33,@@ -1196,7 +1116,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C35, EXYNOS5420_GPIO_C36, EXYNOS5420_GPIO_C37,
EXYNOS5420_GPIO_C40, /* 144 0x90 */
EXYNOS5420_GPIO_C40, EXYNOS5420_GPIO_C41, EXYNOS5420_GPIO_C42, EXYNOS5420_GPIO_C43,@@ -1204,7 +1124,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_C45, EXYNOS5420_GPIO_C46, EXYNOS5420_GPIO_C47,
EXYNOS5420_GPIO_D10, /* 152 0x98 */
EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_D11, EXYNOS5420_GPIO_D12, EXYNOS5420_GPIO_D13,@@ -1212,7 +1132,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_D15, EXYNOS5420_GPIO_D16, EXYNOS5420_GPIO_D17,
EXYNOS5420_GPIO_Y00, /* 160 0xa0 */
EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_Y01, EXYNOS5420_GPIO_Y02, EXYNOS5420_GPIO_Y03,@@ -1220,7 +1140,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y05, EXYNOS5420_GPIO_Y06, EXYNOS5420_GPIO_Y07,
EXYNOS5420_GPIO_Y10, /* 168 0xa8 */
EXYNOS5420_GPIO_Y10, EXYNOS5420_GPIO_Y11, EXYNOS5420_GPIO_Y12, EXYNOS5420_GPIO_Y13,@@ -1228,7 +1148,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y15, EXYNOS5420_GPIO_Y16, EXYNOS5420_GPIO_Y17,
EXYNOS5420_GPIO_Y20, /* 176 0xb0 */
EXYNOS5420_GPIO_Y20, EXYNOS5420_GPIO_Y21, EXYNOS5420_GPIO_Y22, EXYNOS5420_GPIO_Y23,@@ -1236,7 +1156,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y25, EXYNOS5420_GPIO_Y26, EXYNOS5420_GPIO_Y27,
EXYNOS5420_GPIO_Y30, /* 184 0xb8 */
EXYNOS5420_GPIO_Y30, EXYNOS5420_GPIO_Y31, EXYNOS5420_GPIO_Y32, EXYNOS5420_GPIO_Y33,@@ -1244,7 +1164,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y35, EXYNOS5420_GPIO_Y36, EXYNOS5420_GPIO_Y37,
EXYNOS5420_GPIO_Y40, /* 192 0xc0 */
EXYNOS5420_GPIO_Y40, EXYNOS5420_GPIO_Y41, EXYNOS5420_GPIO_Y42, EXYNOS5420_GPIO_Y43,@@ -1252,7 +1172,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y45, EXYNOS5420_GPIO_Y46, EXYNOS5420_GPIO_Y47,
EXYNOS5420_GPIO_Y50, /* 200 0xc8 */
EXYNOS5420_GPIO_Y50, EXYNOS5420_GPIO_Y51, EXYNOS5420_GPIO_Y52, EXYNOS5420_GPIO_Y53,@@ -1260,7 +1180,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y55, EXYNOS5420_GPIO_Y56, EXYNOS5420_GPIO_Y57,
EXYNOS5420_GPIO_Y60, /* 208 0xd0 */
EXYNOS5420_GPIO_Y60, EXYNOS5420_GPIO_Y61, EXYNOS5420_GPIO_Y62, EXYNOS5420_GPIO_Y63,@@ -1269,9 +1189,8 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_Y66, EXYNOS5420_GPIO_Y67,
/* GPIO_PART5_STARTS */EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
EXYNOS5420_GPIO_MAX_PORT_PART_2,EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_2, EXYNOS5420_GPIO_E01, EXYNOS5420_GPIO_E02, EXYNOS5420_GPIO_E03,@@ -1279,7 +1198,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_E05, EXYNOS5420_GPIO_E06, EXYNOS5420_GPIO_E07,
EXYNOS5420_GPIO_E10, /* 224 0xe0 */
EXYNOS5420_GPIO_E10, EXYNOS5420_GPIO_E11, EXYNOS5420_GPIO_E12, EXYNOS5420_GPIO_E13,@@ -1287,7 +1206,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_E15, EXYNOS5420_GPIO_E16, EXYNOS5420_GPIO_E17,
EXYNOS5420_GPIO_F00, /* 232 0xe8 */
EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_F01, EXYNOS5420_GPIO_F02, EXYNOS5420_GPIO_F03,@@ -1295,7 +1214,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_F05, EXYNOS5420_GPIO_F06, EXYNOS5420_GPIO_F07,
EXYNOS5420_GPIO_F10, /* 240 0xf0 */
EXYNOS5420_GPIO_F10, EXYNOS5420_GPIO_F11, EXYNOS5420_GPIO_F12, EXYNOS5420_GPIO_F13,@@ -1303,7 +1222,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_F15, EXYNOS5420_GPIO_F16, EXYNOS5420_GPIO_F17,
EXYNOS5420_GPIO_G00, /* 248 0xf8 */
EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_G01, EXYNOS5420_GPIO_G02, EXYNOS5420_GPIO_G03,@@ -1311,7 +1230,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G05, EXYNOS5420_GPIO_G06, EXYNOS5420_GPIO_G07,
EXYNOS5420_GPIO_G10, /* 256 0x100 */
EXYNOS5420_GPIO_G10, EXYNOS5420_GPIO_G11, EXYNOS5420_GPIO_G12, EXYNOS5420_GPIO_G13,@@ -1319,7 +1238,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G15, EXYNOS5420_GPIO_G16, EXYNOS5420_GPIO_G17,
EXYNOS5420_GPIO_G20, /* 264 0x108 */
EXYNOS5420_GPIO_G20, EXYNOS5420_GPIO_G21, EXYNOS5420_GPIO_G22, EXYNOS5420_GPIO_G23,@@ -1327,7 +1246,7 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_G25, EXYNOS5420_GPIO_G26, EXYNOS5420_GPIO_G27,
EXYNOS5420_GPIO_J40, /* 272 0x110 */
EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_J41, EXYNOS5420_GPIO_J42, EXYNOS5420_GPIO_J43,@@ -1336,15 +1255,89 @@ enum exynos5420_gpio_pin { EXYNOS5420_GPIO_J46, EXYNOS5420_GPIO_J47,
/* GPIO_PART6_STARTS */EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
EXYNOS5420_GPIO_MAX_PORT_PART_3,EXYNOS5420_GPIO_A00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,EXYNOS5420_GPIO_A01,EXYNOS5420_GPIO_A02,EXYNOS5420_GPIO_A03,EXYNOS5420_GPIO_A04,EXYNOS5420_GPIO_A05,EXYNOS5420_GPIO_A06,EXYNOS5420_GPIO_A07,EXYNOS5420_GPIO_A10,EXYNOS5420_GPIO_A11,EXYNOS5420_GPIO_A12,EXYNOS5420_GPIO_A13,EXYNOS5420_GPIO_A14,EXYNOS5420_GPIO_A15,EXYNOS5420_GPIO_A16,EXYNOS5420_GPIO_A17,EXYNOS5420_GPIO_A20,EXYNOS5420_GPIO_A21,EXYNOS5420_GPIO_A22,EXYNOS5420_GPIO_A23,EXYNOS5420_GPIO_A24,EXYNOS5420_GPIO_A25,EXYNOS5420_GPIO_A26,EXYNOS5420_GPIO_A27,EXYNOS5420_GPIO_B00,EXYNOS5420_GPIO_B01,EXYNOS5420_GPIO_B02,EXYNOS5420_GPIO_B03,EXYNOS5420_GPIO_B04,EXYNOS5420_GPIO_B05,EXYNOS5420_GPIO_B06,EXYNOS5420_GPIO_B07,EXYNOS5420_GPIO_B10,EXYNOS5420_GPIO_B11,EXYNOS5420_GPIO_B12,EXYNOS5420_GPIO_B13,EXYNOS5420_GPIO_B14,EXYNOS5420_GPIO_B15,EXYNOS5420_GPIO_B16,EXYNOS5420_GPIO_B17,EXYNOS5420_GPIO_B20,EXYNOS5420_GPIO_B21,EXYNOS5420_GPIO_B22,EXYNOS5420_GPIO_B23,EXYNOS5420_GPIO_B24,EXYNOS5420_GPIO_B25,EXYNOS5420_GPIO_B26,EXYNOS5420_GPIO_B27,EXYNOS5420_GPIO_B30,EXYNOS5420_GPIO_B31,EXYNOS5420_GPIO_B32,EXYNOS5420_GPIO_B33,EXYNOS5420_GPIO_B34,EXYNOS5420_GPIO_B35,EXYNOS5420_GPIO_B36,EXYNOS5420_GPIO_B37,EXYNOS5420_GPIO_B40,EXYNOS5420_GPIO_B41,EXYNOS5420_GPIO_B42,EXYNOS5420_GPIO_B43,EXYNOS5420_GPIO_B44,EXYNOS5420_GPIO_B45,EXYNOS5420_GPIO_B46,EXYNOS5420_GPIO_B47,EXYNOS5420_GPIO_H00,EXYNOS5420_GPIO_H01,EXYNOS5420_GPIO_H02,EXYNOS5420_GPIO_H03,EXYNOS5420_GPIO_H04,EXYNOS5420_GPIO_H05,EXYNOS5420_GPIO_H06,EXYNOS5420_GPIO_H07,EXYNOS5420_GPIO_MAX_PORT_PART_4,EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_4, EXYNOS5420_GPIO_Z1, EXYNOS5420_GPIO_Z2, EXYNOS5420_GPIO_Z3, EXYNOS5420_GPIO_Z4, EXYNOS5420_GPIO_Z5, EXYNOS5420_GPIO_Z6,EXYNOS5420_GPIO_MAX_PORT};
@@ -1385,14 +1378,13 @@ static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = { { EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT }, };
-#define EXYNOS5420_GPIO_NUM_PARTS 6 +#define EXYNOS5420_GPIO_NUM_PARTS 5 static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = { { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 }, { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 }, { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 }, { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
{ EXYNOS5420_GPIO_PART5_BASE,EXYNOS5420_GPIO_MAX_PORT_PART_5 },
{ EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
{ EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT },};
static inline struct gpio_info *get_gpio_data(void) @@ -1505,17 +1497,17 @@ static const struct gpio_name_num_table exynos5_gpio_table[] = { };
static const struct gpio_name_num_table exynos5420_gpio_table[] = {
GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0), GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0), GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00,010),
GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0), GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0), GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0), GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0), GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0),GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0), GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT,0), { 0 } }; -- 1.8.3.2
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com --- Changes for v3: - Remove unnecessary node from DT file - Remove unnecessary features from config file - Remove unnecessary macros from board-specific header file - Fix some trivial typos in comments
Changes for v4: - Add MMC FIFO buffer's configuration to DT file - Make CONFIG_OF_CONTROL be set by the target information - Add basic document to doc/README.odroid-xu3 - Add CONFIG_CMD_EXT4 to config file - Add environment size and offset to config file - Add extra default environment to make bootable without modification - Remove unnecessary features from config file
Changes for v5: - Convert /include/ to #include in DT file
Changes for v6: - Separate out the documentation to new commit - Remove unnecessary header file inclusions from the board-specific setup file - Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 60 ++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 ++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid_xu3.h | 144 ++++++++++++++++++++++++++++++++++ 10 files changed, 457 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..8fe530c 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3 + bool "Exynos5422 Odroid board" + select OF_CONTROL if !SPL_BUILD + config TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2b9bd93..d984f34 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ - exynos5800-peach-pi.dtb + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..52199d9 --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,60 @@ +/* + * Odroid XU3 device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "exynos54xx.dtsi" + +/ { + model = "Odroid XU3 based on EXYNOS5422"; + compatible = "samsung,odroidxu3", "samsung,exynos5"; + + aliases { + serial0 = "/serial@12C00000"; + console = "/serial@12C20000"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000 + 0x80000000 0x10000000 + 0x90000000 0x10000000 + 0xa0000000 0x10000000 + 0xb0000000 0xea00000>; + }; + + serial@12C20000 { + status="okay"; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + fifoth_val = <0x200f0020>; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + fifoth_val = <0x200f0020>; + }; + + mmc@12230000 { + status = "disabled"; + }; +}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "odroid-xu3" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int get_board_rev(void) +{ + return 0; +} + +int exynos_init(void) +{ + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{ + unsigned int set, clr, clr_src_cpu, clr_pll_con0; + struct exynos5420_clock *clk = (struct exynos5420_clock *) + samsung_get_base_clock(); + /* + * CMU_CPU clocks src to MPLL + * Bit values: 0 ; 1 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL + */ + + /* Set CMU_CPU clocks src to OSCCLK */ + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1); + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1); + + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + /* Set APLL to 1200MHz */ + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | + PLL_ENABLE(1); + set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); + + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CMU_CPU clocks src to APLL */ + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0); + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) | + PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7); + set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) | + PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0); + + clrsetbits_le32(&clk->div_cpu0, clr, set); + + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) + continue; + + /* Set MPLL to 800MHz */ + set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); + + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CLKMUX_UART src to MPLL */ + clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7); + set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3); + + clrsetbits_le32(&clk->src_peric0, clr, set); + + /* Set SCLK_UART to 400 MHz (MPLL / 2) */ + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | + UART3_RATIO(15); + set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) | + UART3_RATIO(1); + + clrsetbits_le32(&clk->div_peric0, clr, set); + + while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING) + continue; + + /* Set CLKMUX_MMC src to MPLL */ + clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7); + set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3); + + clrsetbits_le32(&clk->src_fsys, clr, set); + + clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff); + set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0); + + clrsetbits_le32(&clk->div_fsys1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) + continue; + + return 0; +} + +int exynos_early_init_f(void) +{ + return board_clock_init(); +} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2014 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__ + +#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31) + +/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) + +/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \ + (x) & APLL_SEL(1) || \ + (x) & CORE_SEL(0) || \ + (x) & CORE_SEL(1)) + +/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28) + +/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28) + +#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \ + DIV_ATB(DIV_STAT_CHANGING) | \ + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ + DIV_APLL(DIV_STAT_CHANGING) | \ + DIV_ARM2(DIV_STAT_CHANGING)) + +/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16) + +/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20) + +/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16) + +#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ + DIV_UART3(DIV_STAT_CHANGING) | \ + DIV_UART2(DIV_STAT_CHANGING) | \ + DIV_UART1(DIV_STAT_CHANGING) | \ + DIV_UART0(DIV_STAT_CHANGING)) + +/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16) + +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20) + +#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28) + +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ + DIV_MMC1(DIV_STAT_CHANGING) | \ + DIV_MMC2(DIV_STAT_CHANGING)) + +#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..cda4f26 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include "exynos5-common.h" + +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 + +/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */ + +#define TZPC_BASE_OFFSET 0x10000 + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT + +/* + * FIXME: The number of bank is actually 8. But there is no way to reserver the + * last 16 Mib in the last bank now. So I just excluded the last bank + * temporally. + */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_ENV_IS_IN_MMC + +#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" + +/* + * Bootable media layout: + * dev: SD eMMC(part boot) + * BL1 1 0 + * BL2 31 30 + * UBOOT 63 62 + * TZSW 2111 2110 + * ENV 2560 2560(part user) + * + * MBR Primary partiions: + * Num Name Size Offset + * 1. BOOT: 100MiB 2MiB + * 2. ROOT: - +*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ + "${initrdname}\0" \ + "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ + "${fdtfile}\0" \ + "check_ramdisk=" \ + "if run loadinitrd; then " \ + "setenv initrd_addr ${initrdaddr};" \ + "else " \ + "setenv initrd_addr -;" \ + "fi;\0" \ + "check_dtb=" \ + "if run loaddtb; then " \ + "setenv fdt_addr ${fdtaddr};" \ + "else " \ + "setenv fdt_addr;" \ + "fi;\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ + " rootwait ${console} ${opts}\0" \ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${boardname}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run check_dtb;" \ + "run check_ramdisk;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ + "autoboot=" \ + "if test -e mmc 0 Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc 0 zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc 0 uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "mmcbootdev=0\0" \ + "mmcbootpart=1\0" \ + "mmcrootdev=0\0" \ + "mmcrootpart=2\0" \ + "bootdelay=0\0" \ + "dfu_alt_info=Please reset the board\0" \ + "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "initrdname=uInitrd\0" \ + "initrdaddr=42000000\0" \ + "fdtaddr=40800000\0" + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT + +#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif + +#endif /* __CONFIG_H */
Hi Hyungwon,
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
- Fix some trivial typos in comments
Changes for v4:
- Add MMC FIFO buffer's configuration to DT file
- Make CONFIG_OF_CONTROL be set by the target information
- Add basic document to doc/README.odroid-xu3
- Add CONFIG_CMD_EXT4 to config file
- Add environment size and offset to config file
- Add extra default environment to make bootable without modification
- Remove unnecessary features from config file
Changes for v5:
- Convert /include/ to #include in DT file
Changes for v6:
- Separate out the documentation to new commit
- Remove unnecessary header file inclusions from the board-specific
setup file
- Make the function board_clock_init be declared, only when CONFIG_BOARD_EARLY_INIT_F is defined
arch/arm/cpu/armv7/exynos/Kconfig | 5 ++ arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 60 ++++++++++++++ board/samsung/odroid-xu3/Kconfig | 12 +++ board/samsung/odroid-xu3/MAINTAINERS | 6 ++ board/samsung/odroid-xu3/Makefile | 7 ++ board/samsung/odroid-xu3/odroid-xu3.c | 122 ++++++++++++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 95 ++++++++++++++++++++++ configs/odroid-xu3_defconfig | 4
- include/configs/odroid_xu3.h | 144
++++++++++++++++++++++++++++++++++ 10 files changed, 457 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 13dbd95..8fe530c 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -24,6 +24,10 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"
+config TARGET_ODROID_XU3
bool "Exynos5422 Odroid board"select OF_CONTROL if !SPL_BUILD
Why such dependency is needed? Odroid U3 doesn't need such select (and it doesn't use SPL).
config TARGET_ARNDALE bool "Exynos5250 Arndale board" select SUPPORT_SPL @@ -65,6 +69,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2b9bd93..d984f34 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb
exynos5800-peach-pi.dtb \exynos5422-odroidxu3.dtbdtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..52199d9 --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,60 @@ +/*
- Odroid XU3 device tree source
- Copyright (c) 2014 Samsung Electronics Co., Ltd.
http://www.samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+/dts-v1/; +#include "exynos54xx.dtsi"
+/ {
model = "Odroid XU3 based on EXYNOS5422";compatible = "samsung,odroidxu3", "samsung,exynos5";aliases {serial0 = "/serial@12C00000";console = "/serial@12C20000";};memory {device_type = "memory";reg = <0x40000000 0x100000000x50000000 0x100000000x60000000 0x100000000x70000000 0x100000000x80000000 0x100000000x90000000 0x100000000xa0000000 0x100000000xb0000000 0xea00000>;};serial@12C20000 {status="okay";};mmc@12200000 {samsung,bus-width = <8>;samsung,timing = <1 3 3>;samsung,removable = <0>;samsung,pre-init;fifoth_val = <0x200f0020>;};mmc@12210000 {status = "disabled";};mmc@12220000 {samsung,bus-width = <4>;samsung,timing = <1 2 3>;samsung,removable = <1>;fifoth_val = <0x200f0020>;};mmc@12230000 {status = "disabled";};+}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3
+config SYS_BOARD
default "odroid-xu3"+config SYS_VENDOR
default "samsung"+config SYS_CONFIG_NAME
default "odroid_xu3"+endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..8c54842 --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,122 @@ +/*
- Copyright (C) 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/clock.h> +#include "setup.h"
+DECLARE_GLOBAL_DATA_PTR;
+unsigned int get_board_rev(void) +{
return 0;+}
+int exynos_init(void) +{
return 0;+}
+#ifdef CONFIG_BOARD_EARLY_INIT_F +static int board_clock_init(void) +{
unsigned int set, clr, clr_src_cpu, clr_pll_con0;struct exynos5420_clock *clk = (struct exynos5420_clock *)samsung_get_base_clock();
/** CMU_CPU clocks src to MPLL* Bit values: 0 ; 1* MUX_APLL_SEL: FIN_PLL ; FOUT_APLL* MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL* MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C* MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL*//* Set CMU_CPU clocks src to OSCCLK */clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1);set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1);clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))continue;/* Set APLL to 1200MHz */clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) |PLL_ENABLE(1);set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1);clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))continue;/* Set CMU_CPU clocks src to APLL */set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0);clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu)))continue;clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) |PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7);set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) |PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0);clrsetbits_le32(&clk->div_cpu0, clr, set);while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)continue;/* Set MPLL to 800MHz */set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1);clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))continue;/* Set CLKMUX_UART src to MPLL */clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) |UART3_SEL(7);
set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) |UART3_SEL(3); +
clrsetbits_le32(&clk->src_peric0, clr, set);/* Set SCLK_UART to 400 MHz (MPLL / 2) */clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |UART3_RATIO(15);set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) |UART3_RATIO(1);clrsetbits_le32(&clk->div_peric0, clr, set);while (readl(&clk->div_stat_peric0) &DIV_STAT_PERIC0_CHANGING)
continue;/* Set CLKMUX_MMC src to MPLL */clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7);set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3);clrsetbits_le32(&clk->src_fsys, clr, set);clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) |MMC2_RATIO(0x3ff);
set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0);clrsetbits_le32(&clk->div_fsys1, clr, set);/* Wait for divider ready status */while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)continue;return 0;+}
+int exynos_early_init_f(void) +{
return board_clock_init();+} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..143c189 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,95 @@ +/*
- (C) Copyright 2014 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__
+#define SDIV(x) ((x) & 0x7) +#define PDIV(x) (((x) & 0x3f) << 8) +#define MDIV(x) (((x) & 0x3ff) << 16) +#define FSEL(x) (((x) & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) (((x) & 0x1) << 31)
+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16)
+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \
(x) & APLL_SEL(1)|| \
(x) & CORE_SEL(0)|| \
(x) & CORE_SEL(1))+/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28)
+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28)
+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \
DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_ARM2(DIV_STAT_CHANGING))+/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16)
+/* Set CLK_DIV_PERIC0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20)
+/* Set CLK_DIV_STAT_PERIC0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16)
+#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \
DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))+/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16)
+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20)
+#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28)
+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \
DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC2(DIV_STAT_CHANGING))+#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..cda4f26 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,144 @@ +/*
- Copyright (C) 2013 Samsung Electronics
- Hyungwon Hwang human.hwang@samsung.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H
+#include "exynos5-common.h"
+#define CONFIG_SYS_PROMPT "ODROID-XU3 # " +#define CONFIG_IDENT_STRING " for ODROID-XU3"
+#define CONFIG_BOARD_COMMON
+#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
+/* select serial console configuration */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */
+#define TZPC_BASE_OFFSET 0x10000
+#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FAT
+/*
- FIXME: The number of bank is actually 8. But there is no way to
reserver the
- last 16 Mib in the last bank now. So I just excluded the last bank
- temporally.
- */
+#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
+#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_SIZE +#undef CONFIG_ENV_OFFSET +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
+/*
- Bootable media layout:
- dev: SD eMMC(part boot)
- BL1 1 0
- BL2 31 30
- UBOOT 63 62
- TZSW 2111 2110
- ENV 2560 2560(part user)
- MBR Primary partiions:
- Num Name Size Offset
- BOOT: 100MiB 2MiB
- ROOT: -
+*/ +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS \
"loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart}${kerneladdr} " \
"${kernelname}\0" \"loadinitrd=fatload mmc ${mmcbootdev}:${mmcbootpart}${initrdaddr} " \
"${initrdname}\0" \"loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr}" \
"${fdtfile}\0" \"check_ramdisk=" \"if run loadinitrd; then " \"setenv initrd_addr ${initrdaddr};" \"else " \"setenv initrd_addr -;" \"fi;\0" \"check_dtb=" \"if run loaddtb; then " \"setenv fdt_addr ${fdtaddr};" \"else " \"setenv fdt_addr;" \"fi;\0" \"kernel_args=" \"setenv bootargsroot=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \
" rootwait ${console} ${opts}\0" \"boot_fit=" \"setenv kerneladdr 0x42000000;" \"setenv kernelname Image.itb;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr}#${boardname}\0" \"boot_uimg=" \"setenv kerneladdr 0x40007FC0;" \"setenv kernelname uImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \"boot_zimg=" \"setenv kerneladdr 0x40007FC0;" \"setenv kernelname zImage;" \"run check_dtb;" \"run check_ramdisk;" \"run loadkernel;" \"run kernel_args;" \"bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \"autoboot=" \"if test -e mmc 0 Image.itb; then; " \"run boot_fit;" \"elif test -e mmc 0 zImage; then; " \"run boot_zimg;" \"elif test -e mmc 0 uImage; then; " \"run boot_uimg;" \"fi;\0" \"console=" CONFIG_DEFAULT_CONSOLE \"mmcbootdev=0\0" \"mmcbootpart=1\0" \"mmcrootdev=0\0" \"mmcrootpart=2\0" \"bootdelay=0\0" \"dfu_alt_info=Please reset the board\0" \"consoleon=set console console=ttySAC2,115200n8; save;reset\0" \
"consoleoff=set console console=ram; save; reset\0" \"initrdname=uInitrd\0" \"initrdaddr=42000000\0" \"fdtaddr=40800000\0"+/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT
+#ifdef CONFIG_CMD_NET +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#endif
+#endif /* __CONFIG_H */
1.8.3.2
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com --- Changes for v6: - Newly added
doc/README.odroid-xu3 | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 doc/README.odroid-xu3
diff --git a/doc/README.odroid-xu3 b/doc/README.odroid-xu3 new file mode 100644 index 0000000..8e1f333 --- /dev/null +++ b/doc/README.odroid-xu3 @@ -0,0 +1,134 @@ + U-boot for Odroid XU3 +======================== + +1. Summary +========== +This is a quick instruction for setup Odroid boards based on Exynos5422. +Exynos5422 is almost same with Exynos5800 which is a variant of Exynos5422 for +Chromebook. + +Board config: odroid-xu3_config + +2. Supported devices +==================== +This U-BOOT config can be used on the board: +- Odroid XU3 +with CPU Exynos 5422 and 2GB of RAM + +3. Boot sequence +================ +iROM->BL1->(BL2 + TrustZone)->U-BOOT + +To boot up, this version of U-BOOT needs BL1, BL2, and TrustZone binary. +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardker... + +4. Boot media layout +==================== +The table below shows SD/eMMC cards layout for U-boot. +The block offset is starting from 0 and the block size is 512B. + ------------------------------------- +| Binary | Block offset| part type | +| name | SD | eMMC |(eMMC only)| + ------------------------------------- +| Bl1 | 1 | 0 | 1 (boot) | +| Bl2 | 31 | 30 | 1 (boot) | +| U-boot | 63 | 62 | 1 (boot) | +| Tzsw | 2111 | 2110 | 1 (boot) | +| Uboot Env | 2500 | 2500 | 0 (user) | + ------------------------------------- + +5. Prepare the SD boot card - with SD card reader +================================================= +To prepare bootable media you need boot binaries provided by hardkernel. +The files from the link in point 3. +- bl1.bin.hardkernel +- bl2.bin.hardkernel +- tzsw.bin.hardkernel +- u-boot.bin.hardkernel + +This is all you need to boot this board. You can write the binaries to SD card +just by executiog sd_fusing.sh. You cannot use this script to write binaries to +eMMC card.It is valid only for SD card. + +*note +You cannot access the eMMC protected part (the first 8MB roughly) using an +ordinary eMMC reader. + +*note: +If you build u-boot by yourself, you will find u-boot.bin and u-boot-dtb.bin +as the build result. You have to use u-boot-dtb.bin instead of u-boot.bin. + +quick steps for Linux: +- Download all files from the link at point 3. +- put any SD card into the SD reader +- check the device with "dmesg" +- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) +Check if Hardkernel U-boot is booting, and next do the same with your U-boot. + +6. Prepare the eMMC boot card + with a eMMC card reader (boot from eMMC card slot) +===================================================== +To boot the device from the eMMC slot you should use a special card reader +which supports eMMC partition switch. All of the boot binaries are stored +on the eMMC boot partition which is normally hidden. + +The "sd_fusing.sh" script can be used after updating offsets of binaries +according to the table from point 4. Be sure that you are working on the right +eMMC partition - its size is usually very small, about 1-4 MiB. + +7. Prepare the eMMC boot card + with a SD card reader (boot from SD card slot) +================================================= +If you have an eMMC->microSD adapter you can prepare the card as in point 5. +But then the device can boot only from the SD card slot. + +8. Prepare the boot media using Hardkernel U-boot +================================================= +You can update the U-boot to the custom one if you have an working bootloader +delivered with the board on a eMMC/SD card. Then follow the steps: +- install the android fastboot tool +- connect a micro usb cable to the board +- on the U-boot prompt, run command: fastboot (as a root) +- on the host, run command: "fastboot flash bootloader u-boot-dtb.bin" +- the custom U-boot should start after the board resets. + +9. Partition layout +==================== +Default U-boot environment is setup for fixed partition layout. + +Partition table: MSDOS. Disk layout and files as listed in the table below. + ----- ------ ------ ------ -------- --------------------------------- +| Num | Name | FS | Size | Offset | Reguired files | +| | | Type | MiB | MiB | | + ----- ------ ------ ------ -------- --------------------------------- +| 1 | BOOT | fat | 100 | 2 | kernel, fdt** | +| 2 | ROOT | ext4 | - | | any Linux system | + ----- ------ ------ ------ -------- --------------------------------- + +**note: +Supported fdt files are: +- exynos5422-odroidxu3.dtb + +Supported kernel files are: +- Image.itb +- zImage +- uImage + +10. The environment and booting the kernel +========================================== +There are three macros defined in config for various boot options: +Two for both, kernel with device tree support and also without it: +- boot_uimg - load uImage +- boot_zimg - load zImage +If proper fdt file exists then it will be automatically loaded, +so for old kernel types, please remove fdt file from boot partition. + +The third boot option for multi image support (more info: doc/uImage.FIT/) +- boot_fit - for binary file: "Image.itb" + +Default boot command: "autoboot" +And the boot sequence is: +- boot_fit - if "Image.itb" exists +- boot_zimg - if "zImage" exists +- boot_uimg - if "uImage" exists
Hi Hyungwon,
This patch adds documentation for Odroid-XU3. This documentation is based on that of Odroid (doc/README-odroid) made by Przemyslaw Marczak. The documentation includes basic information about boot media layout, environment, partition layout, and the instruction to burn the u-boot image to boot media.
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Lukasz Majewski l.majewski@samsung.com
Changes for v6:
- Newly added
doc/README.odroid-xu3 | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 doc/README.odroid-xu3
diff --git a/doc/README.odroid-xu3 b/doc/README.odroid-xu3 new file mode 100644 index 0000000..8e1f333 --- /dev/null +++ b/doc/README.odroid-xu3 @@ -0,0 +1,134 @@
- U-boot for Odroid XU3
+========================
+1. Summary +========== +This is a quick instruction for setup Odroid boards based on Exynos5422. +Exynos5422 is almost same with Exynos5800 which is a
almost the same
variant of Exynos5422 for +Chromebook.
+Board config: odroid-xu3_config
+2. Supported devices +==================== +This U-BOOT config can be used on the board: +- Odroid XU3 +with CPU Exynos 5422 and 2GB of RAM
+3. Boot sequence +================ +iROM->BL1->(BL2 + TrustZone)->U-BOOT
+To boot up, this version of U-BOOT needs BL1, BL2, and TrustZone binary. +It can be downloaded from: +https://github.com/hardkernel/u-boot/tree/odroidxu3-v2012.07/sd_fuse/hardker...
+4. Boot media layout +==================== +The table below shows SD/eMMC cards layout for U-boot. +The block offset is starting from 0 and the block size is 512B.
+| Binary | Block offset| part type | +| name | SD | eMMC |(eMMC only)|
+| Bl1 | 1 | 0 | 1 (boot) | +| Bl2 | 31 | 30 | 1 (boot) | +| U-boot | 63 | 62 | 1 (boot) | +| Tzsw | 2111 | 2110 | 1 (boot) | +| Uboot Env | 2500 | 2500 | 0 (user) |
+5. Prepare the SD boot card - with SD card reader +================================================= +To prepare bootable media you need boot binaries provided by hardkernel. +The files from the link in point 3. +- bl1.bin.hardkernel +- bl2.bin.hardkernel +- tzsw.bin.hardkernel +- u-boot.bin.hardkernel
+This is all you need to boot this board. You can write the binaries to SD card +just by executiog sd_fusing.sh. You cannot use this
^^^^^^^^^ executing
script to write binaries to +eMMC card.It is valid only for SD card.
+*note +You cannot access the eMMC protected part (the first 8MB roughly) using an +ordinary eMMC reader.
+*note: +If you build u-boot by yourself, you will find u-boot.bin and u-boot-dtb.bin +as the build result. You have to use u-boot-dtb.bin instead of u-boot.bin. + +quick steps for Linux: +- Download all files from the link at point 3. +- put any SD card into the SD reader +- check the device with "dmesg" +- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) +Check if Hardkernel U-boot is booting, and next do the same with your U-boot. + +6. Prepare the eMMC boot card
- with a eMMC card reader (boot from eMMC card slot)
+===================================================== +To boot the device from the eMMC slot you should use a special card reader +which supports eMMC partition switch. All of the boot binaries are stored +on the eMMC boot partition which is normally hidden. + +The "sd_fusing.sh" script can be used after updating offsets of binaries +according to the table from point 4. Be sure that you are working on the right +eMMC partition - its size is usually very small, about 1-4 MiB. + +7. Prepare the eMMC boot card
- with a SD card reader (boot from SD card slot)
+================================================= +If you have an eMMC->microSD adapter you can prepare the card as in point 5. +But then the device can boot only from the SD card slot.
+8. Prepare the boot media using Hardkernel U-boot +================================================= +You can update the U-boot to the custom one if you have an working
^^^ a
bootloader +delivered with the board on a eMMC/SD card. Then follow
^^^ the
the steps: +- install the android fastboot tool +- connect a micro usb cable to the board +- on the U-boot prompt, run command: fastboot (as a root) +- on the host, run command: "fastboot flash bootloader u-boot-dtb.bin" +- the custom U-boot should start after the board resets. + +9. Partition layout +==================== +Default U-boot environment is setup for fixed partition layout.
+Partition table: MSDOS. Disk layout and files as listed in the table below.
--------------------------------- +| Num | Name | FS | Size | Offset | Reguired files | +| | | Type | MiB | MiB | |
--------------------------------- +| 1 | BOOT | fat | 100 | 2 | kernel, fdt** | +| 2 | ROOT | ext4 | - | | any Linux system |
--------------------------------- + +**note: +Supported fdt files are: +- exynos5422-odroidxu3.dtb
+Supported kernel files are: +- Image.itb +- zImage +- uImage
+10. The environment and booting the kernel +========================================== +There are three macros defined in config for various boot options: +Two for both, kernel with device tree support and also without it: +- boot_uimg - load uImage +- boot_zimg - load zImage +If proper fdt file exists then it will be automatically loaded, +so for old kernel types, please remove fdt file from boot partition.
+The third boot option for multi image support (more info: doc/uImage.FIT/) +- boot_fit - for binary file: "Image.itb"
+Default boot command: "autoboot" +And the boot sequence is: +- boot_fit - if "Image.itb" exists +- boot_zimg - if "zImage" exists +- boot_uimg - if "uImage" exists
Please correct those spelling errors at next patch version (I hope final).
I've managed to cross compile u-boot-dtb.bin for XU3 (according to guideline from a cover letter. I can confirm that it boots up till u-boot prompt, so
Tested-by: Lukasz Majewski l.majewski@samsung.com Acked-by: Lukasz Majewski l.majewski@samsung.com
On 10 November 2014 10:41, Hyungwon Hwang human.hwang@samsung.com wrote:
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ v5: https://patchwork.ozlabs.org/patch/407941/
This patchset fixes GPIO information of Exynos5420 which is needed to support Exynos5422 Odroid XU3 board. On the base of the fixes, this patchset adds support for Exynos5422 Odroid XU3 board. I have done this work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1: 26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat.
link: https://patchwork.ozlabs.org/patch/405246/ (updated)
How to test this patch:
- git clone http://git.denx.de/u-boot-samsung.git
- git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370
- Get and apply the patchset of Akshay Saraswat https://patchwork.ozlabs.org/patch/405246/ https://patchwork.ozlabs.org/patch/405247/ https://patchwork.ozlabs.org/patch/405248/ https://patchwork.ozlabs.org/patch/405249/ https://patchwork.ozlabs.org/patch/405250/ https://patchwork.ozlabs.org/patch/405251/ https://patchwork.ozlabs.org/patch/405252/
- Apply this patchset
- make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config
- make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8
- Now you can use u-boot-dtb.bin for your downloading
Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id.
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SECURE_BL1_ONLY
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \
"if test -e mmc 0 Image.itb; then; " \
"if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \
"elif test -e mmc 0 zImage; then; " \
"elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \
"elif test -e mmc 0 uImage; then; " \
"elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \
"mmcbootdev=0\0" \
"mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \
I think you can make it selectable as env value. How you think?
Thanks, Minkyu Kang.
Dear Minkyu Kang,
On Tue, 11 Nov 2014 21:53:35 +0900 Minkyu Kang promsoft@gmail.com wrote:
On 10 November 2014 10:41, Hyungwon Hwang human.hwang@samsung.com wrote:
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version: v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html v4: https://patchwork.ozlabs.org/patch/407411/ v5: https://patchwork.ozlabs.org/patch/407941/
This patchset fixes GPIO information of Exynos5420 which is needed to support Exynos5422 Odroid XU3 board. On the base of the fixes, this patchset adds support for Exynos5422 Odroid XU3 board. I have done this work on the master branch in http://git.denx.de/u-boot-samsung.git (sha1: 26f195c71252e98aebfffd5cfa994a4475559370) with patches by Akshay Saraswat.
link: https://patchwork.ozlabs.org/patch/405246/ (updated)
How to test this patch:
- git clone http://git.denx.de/u-boot-samsung.git
- git reset --hard 26f195c71252e98aebfffd5cfa994a4475559370
- Get and apply the patchset of Akshay Saraswat https://patchwork.ozlabs.org/patch/405246/ https://patchwork.ozlabs.org/patch/405247/ https://patchwork.ozlabs.org/patch/405248/ https://patchwork.ozlabs.org/patch/405249/ https://patchwork.ozlabs.org/patch/405250/ https://patchwork.ozlabs.org/patch/405251/ https://patchwork.ozlabs.org/patch/405252/
- Apply this patchset
- make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- odroid-xu3_config
- make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j8
- Now you can use u-boot-dtb.bin for your downloading
Note: If you use micro SD card for your test you have to apply the below patch additionally. This patch is needed, because micro sd card is recognized as MMC1 instead of MMC0. Additional work is needed to make it work regardless of device id.
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ba591e7..437eaae 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -109,7 +109,7 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
-#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SECURE_BL1_ONLY
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h index cda4f26..b46ccad 100644 --- a/include/configs/odroid_xu3.h +++ b/include/configs/odroid_xu3.h @@ -110,15 +110,15 @@ "run kernel_args;" \ "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ "autoboot=" \
"if test -e mmc 0 Image.itb; then; " \
"if test -e mmc 1 Image.itb; then; " \ "run boot_fit;" \
"elif test -e mmc 0 zImage; then; " \
"elif test -e mmc 1 zImage; then; " \ "run boot_zimg;" \
"elif test -e mmc 0 uImage; then; " \
"elif test -e mmc 1 uImage; then; " \ "run boot_uimg;" \ "fi;\0" \ "console=" CONFIG_DEFAULT_CONSOLE \
"mmcbootdev=0\0" \
"mmcbootdev=1\0" \ "mmcbootpart=1\0" \ "mmcrootdev=0\0" \ "mmcrootpart=2\0" \I think you can make it selectable as env value. How you think?
We can use ${mmcbootdev} to select the boot media simply with small changes. But the problem is in CONFIG_SYS_MMC_ENV_DEV. Even though we can change the bootable media through ${mmcbootdev}, we cannot save this environment to MMC or SD card, and have to set the variable again after reboot. So I think that this should be solved in another way.
Thanks, Minkyu Kang.
Best regards, Hyungwon Hwang
participants (3)
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Hyungwon Hwang -
Lukasz Majewski -
Minkyu Kang