There is a board-specific portion for calling watchdog enable itself, in main U-Boot.

Signed-off-by: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap-common/boot-common.c | 4 ++++ board/ti/am335x/board.c | 5 +++++ include/configs/ti_am335x_common.h | 7 +++++++ 3 files changed, 16 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 6b4772b..1880e04 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -14,6 +14,7 @@ #include <asm/arch/omap.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> +#include <watchdog.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -76,6 +77,9 @@ void spl_board_init(void) #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif }

int board_mmc_init(bd_t *bis) diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 0d6912b..0986646 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -27,6 +27,7 @@ #include <miiphy.h> #include <cpsw.h> #include <environment.h> +#include <watchdog.h> #include "board.h"

DECLARE_GLOBAL_DATA_PTR; @@ -354,6 +355,10 @@ int board_init(void) STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; #endif

+#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

gpmc_init(); diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 59c758c..28e7a80 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -43,6 +43,10 @@ #define CONFIG_SPL_BOOTCOUNT_LIMIT #define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000

+/* Enable the HW watchdog, since we can use this with bootcount */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_OMAP_WATCHDOG + /* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and @@ -53,6 +57,9 @@ #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)

+/* Enable the watchdog inside of SPL */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice.