[U-Boot-Users] Bug in AT91RM9200.h
Guys,
A while ago I sent the following the the linux arm ML. I am sure this applies to U-Boot as well!
I just noticed the following:
in incluse/asm-arm/mach-at91rm9200/AT91RM9200.h
#define AT91C_SMC2_DBW (0x1 << 13) // (SMC2) Data Bus Width
and drivers/pcmcia/at91_cf.c uses code like
csr &= ~AT91C_SMC2_DBW;BUT:
According to the User Man the "DBW: Data Bus Width" field is _TWO_ bits. Thus it should be
#define AT91C_SMC2_DBW (0x3 << 13) // (SMC2) Data Bus Width
So please apply this trivial.
* Fix define in AT91RM9200.h Patch by Steven Scholz, 10 Oct 2005
-- Steven
Index: u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h,v retrieving revision 1.11 diff -u -r1.11 AT91RM9200.h --- u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h 4 Oct 2005 23:52:35 -0000 1.11 +++ u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h 10 Oct 2005 12:20:39 -0000 @@ -255,7 +255,7 @@ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ #define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ #define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ +#define AT91C_SMC2_DBW ((unsigned int) 0x3 << 13) /* (SMC2) Data Bus Width */ #define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
Ladies,
there's another wrong define in AT91RM9200.
According the (my) User Man the RWHOLD field of SMC_CSR0..SMC_CSR7 starts at bit 28. Thus
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
is rubbish!
So please apply this trivial patch instead if my previous one:
* Fix defines AT91C_SMC2_DBW and AT91C_SMC2_RWHOLD in AT91RM9200.h Patch by Steven Scholz, 10 Oct 2005
(Machine generate header file - ha, ha!)
-- Steven
Index: u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h =================================================================== RCS file: /cvsroot/u-boot/u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h,v retrieving revision 1.11 diff -u -r1.11 AT91RM9200.h --- u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h 4 Oct 2005 23:52:35 -0000 1.11 +++ u-boot/include/asm-arm/arch-at91rm9200/AT91RM9200.h 10 Oct 2005 12:32:02 -0000 @@ -255,7 +255,7 @@ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ #define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */ #define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */ -#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */ +#define AT91C_SMC2_DBW ((unsigned int) 0x3 << 13) /* (SMC2) Data Bus Width */ #define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */ @@ -265,7 +265,7 @@ #define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */ #define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */ #define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */ -#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ +#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 28) /* (SMC2) Read and Write Signal Hold Time */
/******************************************************************************/ /* SOFTWARE API DEFINITION FOR Power Management Controler */
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Steven Scholz