spl_board_init() is necessary for boot. Remove the #undef that keeps it out of the boot sequence.

Cc: Tom Rini trini@konsulko.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Igor Grinberg grinberg@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- include/configs/cm_t43.h | 1 - 1 file changed, 1 deletion(-)

diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index d3cd38d..d0dfdef 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -98,7 +98,6 @@ #undef CONFIG_SPL_OS_BOOT #undef CONFIG_SPL_GPIO_SUPPORT #undef CONFIG_SPL_NAND_SUPPORT -#undef CONFIG_SPL_BOARD_INIT #undef CONFIG_BOOTDELAY #include <config_distro_defaults.h> #define CONFIG_ZERO_BOOTDELAY_CHECK

Add full support for SPI flash chips to future-proof U-Boot for cm-t43.

Cc: Tom Rini trini@konsulko.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Igor Grinberg grinberg@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- configs/cm_t43_defconfig | 11 +++++++++++ include/configs/cm_t43.h | 2 -- 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 98e21cf..672117a 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -11,3 +11,14 @@ CONFIG_CMD_GPIO=y CONFIG_DM=y CONFIG_SYS_NS16550=y CONFIG_DM_SERIAL=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_ATMEL=y diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 6abc085..3bc3336 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -70,9 +70,7 @@ #define CONFIG_AM437X_USB2PHY2_HOST

/* SPI Flash support */ -#define CONFIG_SPI_FLASH #define CONFIG_TI_SPI_MMAP -#define CONFIG_SPI_FLASH_BAR #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3

Simplify the board file by splitting it to spl portion and u-boot portion. Some unnecessary includes were identified and removed. No functional changes.

Cc: Tom Rini trini@konsulko.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Igor Grinberg grinberg@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_t43/Makefile | 6 +- board/compulab/cm_t43/board.c | 272 ----------------------------------------- board/compulab/cm_t43/cm_t43.c | 144 ++++++++++++++++++++++ board/compulab/cm_t43/spl.c | 134 ++++++++++++++++++++ 4 files changed, 283 insertions(+), 273 deletions(-) delete mode 100644 board/compulab/cm_t43/board.c create mode 100644 board/compulab/cm_t43/cm_t43.c create mode 100644 board/compulab/cm_t43/spl.c

diff --git a/board/compulab/cm_t43/Makefile b/board/compulab/cm_t43/Makefile index 3993689..c749659 100644 --- a/board/compulab/cm_t43/Makefile +++ b/board/compulab/cm_t43/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-y += board.o mux.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o mux.o +else +obj-y += cm_t43.o mux.o +endif diff --git a/board/compulab/cm_t43/board.c b/board/compulab/cm_t43/board.c deleted file mode 100644 index 4272c45..0000000 --- a/board/compulab/cm_t43/board.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (C) 2015 Compulab, Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <i2c.h> -#include <miiphy.h> -#include <cpsw.h> -#include <spl.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mux.h> -#include <asm/arch/ddr_defs.h> -#include <asm/errno.h> -#include <asm/gpio.h> -#include <asm/emif.h> -#include <power/pmic.h> -#include <power/tps65218.h> -#include "board.h" - -DECLARE_GLOBAL_DATA_PTR; - -static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; -const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; -const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; -const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; - -const struct ctrl_ioregs ioregs_ddr3 = { - .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, - .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, - .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, - .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, - .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, - .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, - .emif_sdram_config_ext = 0x0143, -}; - -/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ -struct emif_regs ddr3_emif_regs = { - .sdram_config = 0x638413B2, - .ref_ctrl = 0x00000C30, - .sdram_tim1 = 0xEAAAD4DB, - .sdram_tim2 = 0x266B7FDA, - .sdram_tim3 = 0x107F8678, - .read_idle_ctrl = 0x00050000, - .zq_config = 0x50074BE4, - .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E004008, - .emif_ddr_ext_phy_ctrl_1 = 0x08020080, - .emif_ddr_ext_phy_ctrl_2 = 0x00000066, - .emif_ddr_ext_phy_ctrl_3 = 0x00000091, - .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, - .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, - .emif_rd_wr_exec_thresh = 0x80000405, - .emif_prio_class_serv_map = 0x80000001, - .emif_connect_id_serv_1_map = 0x80000094, - .emif_connect_id_serv_2_map = 0x00000000, - .emif_cos_config = 0x000FFFFF -}; - -const u32 ext_phy_ctrl_const_base_ddr3[] = { - 0x00000000, - 0x00000044, - 0x00000044, - 0x00000046, - 0x00000046, - 0x00000000, - 0x00000059, - 0x00000077, - 0x00000093, - 0x000000A8, - 0x00000000, - 0x00000019, - 0x00000037, - 0x00000053, - 0x00000068, - 0x00000000, - 0x0, - 0x0, - 0x40000000, - 0x08102040 -}; - -void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) -{ - *regs = ext_phy_ctrl_const_base_ddr3; - *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); -} - -const struct dpll_params *get_dpll_ddr_params(void) -{ - return &dpll_ddr; -} - -const struct dpll_params *get_dpll_mpu_params(void) -{ - return &dpll_mpu; -} - -const struct dpll_params *get_dpll_core_params(void) -{ - return &dpll_core; -} - -const struct dpll_params *get_dpll_per_params(void) -{ - return &dpll_per; -} - -static void enable_vtt_regulator(void) -{ - u32 temp; - - writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); - writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); - temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); - temp = temp & ~(GPIO_OE_ENABLE(7)); - writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); -} - -void sdram_init(void) -{ - unsigned long ram_size; - - enable_vtt_regulator(); - config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (ram_size == 0x80000000 || - ram_size == 0x40000000 || - ram_size == 0x20000000) - return; - - ddr3_emif_regs.sdram_config = 0x638453B2; - config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); - ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); - if (ram_size == 0x08000000) - return; - - hang(); -} -#endif - -/* setup board specific PMIC */ -int power_init_board(void) -{ - struct pmic *p; - - power_tps65218_init(I2C_PMIC); - p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) - puts("PMIC: TPS65218\n"); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - gpmc_init(); - set_i2c_pin_mux(); - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); - i2c_probe(TPS65218_CHIP_PM); - - return 0; -} - -#ifdef CONFIG_DRIVER_TI_CPSW - -static void cpsw_control(int enabled) -{ - return; -} - -static struct cpsw_slave_data cpsw_slaves[] = { - { - .slave_reg_ofs = 0x208, - .sliver_reg_ofs = 0xd80, - .phy_addr = 0, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, - { - .slave_reg_ofs = 0x308, - .sliver_reg_ofs = 0xdc0, - .phy_addr = 1, - .phy_if = PHY_INTERFACE_MODE_RGMII, - }, -}; - -static struct cpsw_platform_data cpsw_data = { - .mdio_base = CPSW_MDIO_BASE, - .cpsw_base = CPSW_BASE, - .mdio_div = 0xff, - .channels = 8, - .cpdma_reg_ofs = 0x800, - .slaves = 2, - .slave_data = cpsw_slaves, - .ale_reg_ofs = 0xd00, - .ale_entries = 1024, - .host_port_reg_ofs = 0x108, - .hw_stats_reg_ofs = 0x900, - .bd_ram_ofs = 0x2000, - .mac_control = (1 << 5), - .control = cpsw_control, - .host_port_num = 0, - .version = CPSW_CTRL_VERSION_2, -}; - -#define GPIO_PHY1_RST 170 -#define GPIO_PHY2_RST 168 - -int board_phy_config(struct phy_device *phydev) -{ - unsigned short val; - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - if (phydev->drv->config) - return phydev->drv->config(phydev); - - return 0; -} - -static void board_phy_init(void) -{ - set_mdio_pin_mux(); - writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ - writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ - writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ - - /* For revision A */ - writel(0x2000009, 0x44df2e6c); - writel(0x38a, 0x44df2e70); - - mdelay(10); - - gpio_request(GPIO_PHY1_RST, "phy1_rst"); - gpio_request(GPIO_PHY2_RST, "phy2_rst"); - gpio_direction_output(GPIO_PHY1_RST, 0); - gpio_direction_output(GPIO_PHY2_RST, 0); - mdelay(2); - - gpio_set_value(GPIO_PHY1_RST, 1); - gpio_set_value(GPIO_PHY2_RST, 1); - mdelay(2); -} - -int board_eth_init(bd_t *bis) -{ - int rv; - - set_rgmii_pin_mux(); - writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); - board_phy_init(); - - rv = cpsw_register(&cpsw_data); - if (rv < 0) - printf("Error %d registering CPSW switch\n", rv); - - return rv; -} -#endif diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c new file mode 100644 index 0000000..445b609 --- /dev/null +++ b/board/compulab/cm_t43/cm_t43.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2015 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <asm/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/emif.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + + power_tps65218_init(I2C_PMIC); + p = pmic_get("TPS65218_PMIC"); + if (p && !pmic_probe(p)) + puts("PMIC: TPS65218\n"); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_probe(TPS65218_CHIP_PM); + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW + +static void cpsw_control(int enabled) +{ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_addr = 0, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_addr = 1, + .phy_if = PHY_INTERFACE_MODE_RGMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 2, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#define GPIO_PHY1_RST 170 +#define GPIO_PHY2_RST 168 + +int board_phy_config(struct phy_device *phydev) +{ + unsigned short val; + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} + +static void board_phy_init(void) +{ + set_mdio_pin_mux(); + writel(0x40003, 0x44e10a74); /* Mux pin as clkout2 */ + writel(0x10006, 0x44df4108); /* Select EXTDEV as clock source */ + writel(0x4, 0x44df2e60); /* Set EXTDEV as MNbypass */ + + /* For revision A */ + writel(0x2000009, 0x44df2e6c); + writel(0x38a, 0x44df2e70); + + mdelay(10); + + gpio_request(GPIO_PHY1_RST, "phy1_rst"); + gpio_request(GPIO_PHY2_RST, "phy2_rst"); + gpio_direction_output(GPIO_PHY1_RST, 0); + gpio_direction_output(GPIO_PHY2_RST, 0); + mdelay(2); + + gpio_set_value(GPIO_PHY1_RST, 1); + gpio_set_value(GPIO_PHY2_RST, 1); + mdelay(2); +} + +int board_eth_init(bd_t *bis) +{ + int rv; + + set_rgmii_pin_mux(); + writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel); + board_phy_init(); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + + return rv; +} +#endif diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c new file mode 100644 index 0000000..03ecf8a --- /dev/null +++ b/board/compulab/cm_t43/spl.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2016 Compulab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr_defs.h> +#include <asm/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; +const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; +const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; +const struct dpll_params dpll_ddr = { 400, 23, 1, -1, 1, -1, -1 }; + +const struct ctrl_ioregs ioregs_ddr3 = { + .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, + .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, + .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, + .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, + .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, + .emif_sdram_config_ext = 0x0143, +}; + +/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ +struct emif_regs ddr3_emif_regs = { + .sdram_config = 0x638413B2, + .ref_ctrl = 0x00000C30, + .sdram_tim1 = 0xEAAAD4DB, + .sdram_tim2 = 0x266B7FDA, + .sdram_tim3 = 0x107F8678, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x50074BE4, + .temp_alert_config = 0x0, + .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_ext_phy_ctrl_1 = 0x08020080, + .emif_ddr_ext_phy_ctrl_2 = 0x00000066, + .emif_ddr_ext_phy_ctrl_3 = 0x00000091, + .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, + .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, + .emif_rd_wr_exec_thresh = 0x80000405, + .emif_prio_class_serv_map = 0x80000001, + .emif_connect_id_serv_1_map = 0x80000094, + .emif_connect_id_serv_2_map = 0x00000000, + .emif_cos_config = 0x000FFFFF +}; + +const u32 ext_phy_ctrl_const_base_ddr3[] = { + 0x00000000, + 0x00000044, + 0x00000044, + 0x00000046, + 0x00000046, + 0x00000000, + 0x00000059, + 0x00000077, + 0x00000093, + 0x000000A8, + 0x00000000, + 0x00000019, + 0x00000037, + 0x00000053, + 0x00000068, + 0x00000000, + 0x0, + 0x0, + 0x40000000, + 0x08102040 +}; + +void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) +{ + *regs = ext_phy_ctrl_const_base_ddr3; + *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +const struct dpll_params *get_dpll_mpu_params(void) +{ + return &dpll_mpu; +} + +const struct dpll_params *get_dpll_core_params(void) +{ + return &dpll_core; +} + +const struct dpll_params *get_dpll_per_params(void) +{ + return &dpll_per; +} + +static void enable_vtt_regulator(void) +{ + u32 temp; + + writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); + writel(GPIO_SETDATAOUT(7), AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); + temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); + temp = temp & ~(GPIO_OE_ENABLE(7)); + writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); +} + +void sdram_init(void) +{ + unsigned long ram_size; + + enable_vtt_regulator(); + config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); + ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (ram_size == 0x80000000 || + ram_size == 0x40000000 || + ram_size == 0x20000000) + return; + + ddr3_emif_regs.sdram_config = 0x638453B2; + config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0); + ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (ram_size == 0x08000000) + return; + + hang(); +} +

Set TPS65218 FSEAL bit to 1 so that RTC could be powered using on-board 3V battery. This is necessary so that time and date will survive reboots and power offs.

Cc: Tom Rini trini@konsulko.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Igor Grinberg grinberg@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_t43/cm_t43.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/board/compulab/cm_t43/cm_t43.c b/board/compulab/cm_t43/cm_t43.c index 445b609..0d5da6f 100644 --- a/board/compulab/cm_t43/cm_t43.c +++ b/board/compulab/cm_t43/cm_t43.c @@ -23,11 +23,18 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; int power_init_board(void) { struct pmic *p; + uchar tps_status = 0;

power_tps65218_init(I2C_PMIC); p = pmic_get("TPS65218_PMIC"); - if (p && !pmic_probe(p)) + if (p && !pmic_probe(p)) { puts("PMIC: TPS65218\n"); + /* We don't care if fseal is locked, but we do need it set */ + tps65218_lock_fseal(); + tps65218_reg_read(TPS65218_STATUS, &tps_status); + if (!(tps_status & TPS65218_FSEAL)) + printf("WARNING: RTC not backed by battery!\n"); + }

return 0; }

During boot, U-Boot raises the CPU frequency but the CORE and MPU regulators are not updated. This is not a problem in cold boot since the default values that the pmic outputs are correct, but if Linux were to switch the module to a low power OPP, the new voltage values will be retained after a reboot and the module will likely hang once U-Boot raises the CPU frequency back up.

Set both CORE and MPU regulators to to 1.1V on boot.

Cc: Tom Rini trini@konsulko.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Igor Grinberg grinberg@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- board/compulab/cm_t43/spl.c | 15 +++++++++++++++ include/configs/cm_t43.h | 2 ++ 2 files changed, 17 insertions(+)

diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index 520de24..b7d118e 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -6,9 +6,13 @@

#include <common.h> #include <spl.h> +#include <i2c.h> #include <asm/arch/clock.h> #include <asm/arch/ddr_defs.h> #include <asm/gpio.h> +#include <power/pmic.h> +#include <power/tps65218.h> +#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

@@ -100,6 +104,17 @@ const struct dpll_params *get_dpll_per_params(void) return &dpll_per; }

+void scale_vcores(void) +{ + set_i2c_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + if (i2c_probe(TPS65218_CHIP_PM)) + return; + + tps65218_voltage_update(TPS65218_DCDC1, TPS65218_DCDC_VOLT_SEL_1100MV); + tps65218_voltage_update(TPS65218_DCDC2, TPS65218_DCDC_VOLT_SEL_1100MV); +} + void sdram_init(void) { unsigned long ram_size; diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 3bc3336..329a5ea 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -167,5 +167,7 @@ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT

#endif /* __CONFIG_CM_T43_H */

Commit 755324 (configs: Use config_distro_defaults.h in ti_armv7_common.h) made ti_armv7_common.h include config_distro_defaults.h. This breaks the bootdelay feature in cm_t43 because now the - #include ti_armv7_common.h (#define CONFIG_BOOTDELAY 1) - #undef CONFIG_BOOTDELAY - #include config_distro_defaults.h (#define CONFIG_BOOTDELAY 2) dance in cm_t43.h is no longer valid and in fact leads to CONFIG_BOOTDELAY not being defined.

Adapt the config file to the new inclusion hierarchy.

Cc: Tom Rini trini@konsulko.com Cc: Albert Aribaud albert.u.boot@aribaud.net Cc: Igor Grinberg grinberg@compulab.co.il Signed-off-by: Nikita Kiryanov nikita@compulab.co.il --- NOTE: this patch depends on the cm-t43 maintenance series: https://www.mail-archive.com/u-boot@lists.denx.de/msg204112.html

include/configs/cm_t43.h | 2 -- 1 file changed, 2 deletions(-)

diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index ae15095..1c1951c 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -98,10 +98,8 @@ #undef CONFIG_SPL_OS_BOOT #undef CONFIG_SPL_GPIO_SUPPORT #undef CONFIG_SPL_NAND_SUPPORT -#undef CONFIG_BOOTDELAY #undef CONFIG_SYS_MONITOR_LEN #undef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR -#include <config_distro_defaults.h> #define CONFIG_ZERO_BOOTDELAY_CHECK #undef CONFIG_CMD_IMLS