[U-Boot] [PATCH v4 00/13] ARM: uniphier: add ARMv8 SoCs support
Masahiro Yamada (13): pinctrl: uniphier: rename function/array names pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20 ARM: uniphier: avoid unaligned access to DT on 64bit SoC ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref board ARM: dts: uniphier: move aliases node up to satisfy fdtgrep ARM: uniphier: add sg_set_iectrl_range() ARM: uniphier: carry on booting for Unknown boot mode ARM: uniphier: rework uniphier_set_fdt_file() ARM: uniphier: add PH1-LD20 SoC support ARM: uniphier: reserve the last 64 byte of SDRAM ARM: dts: uniphier: add SD controller node for PH1-LD20 clk: uniphier: add Media I/O clock driver support for PH1-LD20 ARM: uniphier: increase image load speed from NOR device
arch/arm/dts/uniphier-ph1-ld11-ref.dts | 18 +- arch/arm/dts/uniphier-ph1-ld20-ref.dts | 19 +- arch/arm/dts/uniphier-ph1-ld20.dtsi | 17 ++ arch/arm/mach-uniphier/Kconfig | 5 + arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/arm64/Makefile | 10 + arch/arm/mach-uniphier/arm64/arm-cci500.c | 41 +++ arch/arm/mach-uniphier/arm64/mem_map.c | 28 ++ arch/arm/mach-uniphier/arm64/smp.S | 19 ++ arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 31 +++ arch/arm/mach-uniphier/arm64/timer.c | 38 +++ arch/arm/mach-uniphier/board_common.c | 6 +- arch/arm/mach-uniphier/board_early_init_f.c | 8 + arch/arm/mach-uniphier/board_late_init.c | 66 ++--- arch/arm/mach-uniphier/boards.c | 25 ++ arch/arm/mach-uniphier/boot-mode/Makefile | 1 + arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 + arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c | 77 ++++++ arch/arm/mach-uniphier/boot-mode/boot-mode.c | 4 + arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c | 5 + arch/arm/mach-uniphier/clk/Makefile | 1 + arch/arm/mach-uniphier/clk/clk-ld20.c | 14 + arch/arm/mach-uniphier/cpu_info.c | 2 +- arch/arm/mach-uniphier/dram/Makefile | 1 + arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h | 41 +++ arch/arm/mach-uniphier/dram/umc-ld20-regs.h | 73 ++++++ arch/arm/mach-uniphier/dram/umc-ld20.c | 306 ++++++++++++++++++++++ arch/arm/mach-uniphier/dram_init.c | 10 +- arch/arm/mach-uniphier/early-clk/Makefile | 1 + arch/arm/mach-uniphier/early-clk/early-clk-ld20.c | 30 +++ arch/arm/mach-uniphier/init.h | 7 + arch/arm/mach-uniphier/init/Makefile | 1 + arch/arm/mach-uniphier/init/init-ld20.c | 53 ++++ arch/arm/mach-uniphier/init/init.c | 5 + arch/arm/mach-uniphier/memconf/Makefile | 1 + arch/arm/mach-uniphier/memconf/memconf-pxs2.c | 3 + arch/arm/mach-uniphier/pinctrl/Makefile | 1 + arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 46 ++++ arch/arm/mach-uniphier/sbc/Makefile | 1 + arch/arm/mach-uniphier/sg-regs.h | 11 +- configs/uniphier_ld20_defconfig | 28 ++ drivers/clk/uniphier/clk-uniphier-mio.c | 4 + drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 8 +- drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 34 +-- drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 34 +-- drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 34 +-- drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 34 +-- drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 34 +-- drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 34 +-- include/configs/uniphier.h | 52 +++- 50 files changed, 1151 insertions(+), 174 deletions(-) create mode 100644 arch/arm/mach-uniphier/arm64/Makefile create mode 100644 arch/arm/mach-uniphier/arm64/arm-cci500.c create mode 100644 arch/arm/mach-uniphier/arm64/mem_map.c create mode 100644 arch/arm/mach-uniphier/arm64/smp.S create mode 100644 arch/arm/mach-uniphier/arm64/smp_kick_cpus.c create mode 100644 arch/arm/mach-uniphier/arm64/timer.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c create mode 100644 arch/arm/mach-uniphier/clk/clk-ld20.c create mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h create mode 100644 arch/arm/mach-uniphier/dram/umc-ld20-regs.h create mode 100644 arch/arm/mach-uniphier/dram/umc-ld20.c create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ld20.c create mode 100644 arch/arm/mach-uniphier/init/init-ld20.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c create mode 100644 configs/uniphier_ld20_defconfig
Make function/array names match the file names for consistency.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 34 ++++++++++++------------ drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 34 ++++++++++++------------ drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 34 ++++++++++++------------ drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 34 ++++++++++++------------ drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 34 ++++++++++++------------ drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 34 ++++++++++++------------ 6 files changed, 102 insertions(+), 102 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index 8f7574e..ca66dee 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -9,7 +9,7 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin ph1_ld4_pins[] = { +static const struct uniphier_pinctrl_pin uniphier_ld4_pins[] = { UNIPHIER_PINCTRL_PIN(53, 0), UNIPHIER_PINCTRL_PIN(54, 0), UNIPHIER_PINCTRL_PIN(55, 0), @@ -62,7 +62,7 @@ static const unsigned usb2_muxvals[] = {4, 4}; static const unsigned usb2b_pins[] = {67, 68}; static const unsigned usb2b_muxvals[] = {23, 23};
-static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { +static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(i2c0), @@ -83,7 +83,7 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(usb2b), };
-static const char * const ph1_ld4_functions[] = { +static const char * const uniphier_ld4_functions[] = { "emmc", "i2c0", "i2c1", @@ -100,30 +100,30 @@ static const char * const ph1_ld4_functions[] = { "usb2", };
-static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = { - .pins = ph1_ld4_pins, - .pins_count = ARRAY_SIZE(ph1_ld4_pins), - .groups = ph1_ld4_groups, - .groups_count = ARRAY_SIZE(ph1_ld4_groups), - .functions = ph1_ld4_functions, - .functions_count = ARRAY_SIZE(ph1_ld4_functions), +static struct uniphier_pinctrl_socdata uniphier_ld4_pinctrl_socdata = { + .pins = uniphier_ld4_pins, + .pins_count = ARRAY_SIZE(uniphier_ld4_pins), + .groups = uniphier_ld4_groups, + .groups_count = ARRAY_SIZE(uniphier_ld4_groups), + .functions = uniphier_ld4_functions, + .functions_count = ARRAY_SIZE(uniphier_ld4_functions), };
-static int ph1_ld4_pinctrl_probe(struct udevice *dev) +static int uniphier_ld4_pinctrl_probe(struct udevice *dev) { - return uniphier_pinctrl_probe(dev, &ph1_ld4_pinctrl_socdata); + return uniphier_pinctrl_probe(dev, &uniphier_ld4_pinctrl_socdata); }
-static const struct udevice_id ph1_ld4_pinctrl_match[] = { +static const struct udevice_id uniphier_ld4_pinctrl_match[] = { { .compatible = "socionext,ph1-ld4-pinctrl" }, { /* sentinel */ } };
-U_BOOT_DRIVER(ph1_ld4_pinctrl) = { - .name = "ph1-ld4-pinctrl", +U_BOOT_DRIVER(uniphier_ld4_pinctrl) = { + .name = "uniphier-ld4-pinctrl", .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(ph1_ld4_pinctrl_match), - .probe = ph1_ld4_pinctrl_probe, + .of_match = of_match_ptr(uniphier_ld4_pinctrl_match), + .probe = uniphier_ld4_pinctrl_probe, .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 2a5d5f3..0fd4dc4 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -9,7 +9,7 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin ph1_ld6b_pins[] = { +static const struct uniphier_pinctrl_pin uniphier_ld6b_pins[] = { UNIPHIER_PINCTRL_PIN(113, 0), UNIPHIER_PINCTRL_PIN(114, 0), UNIPHIER_PINCTRL_PIN(115, 0), @@ -61,7 +61,7 @@ static const unsigned usb2_muxvals[] = {0, 0}; static const unsigned usb3_pins[] = {62, 63}; static const unsigned usb3_muxvals[] = {0, 0};
-static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { +static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(i2c0), @@ -83,7 +83,7 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(usb3), };
-static const char * const ph1_ld6b_functions[] = { +static const char * const uniphier_ld6b_functions[] = { "emmc", "i2c0", "i2c1", @@ -100,30 +100,30 @@ static const char * const ph1_ld6b_functions[] = { "usb3", };
-static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = { - .pins = ph1_ld6b_pins, - .pins_count = ARRAY_SIZE(ph1_ld6b_pins), - .groups = ph1_ld6b_groups, - .groups_count = ARRAY_SIZE(ph1_ld6b_groups), - .functions = ph1_ld6b_functions, - .functions_count = ARRAY_SIZE(ph1_ld6b_functions), +static struct uniphier_pinctrl_socdata uniphier_ld6b_pinctrl_socdata = { + .pins = uniphier_ld6b_pins, + .pins_count = ARRAY_SIZE(uniphier_ld6b_pins), + .groups = uniphier_ld6b_groups, + .groups_count = ARRAY_SIZE(uniphier_ld6b_groups), + .functions = uniphier_ld6b_functions, + .functions_count = ARRAY_SIZE(uniphier_ld6b_functions), };
-static int ph1_ld6b_pinctrl_probe(struct udevice *dev) +static int uniphier_ld6b_pinctrl_probe(struct udevice *dev) { - return uniphier_pinctrl_probe(dev, &ph1_ld6b_pinctrl_socdata); + return uniphier_pinctrl_probe(dev, &uniphier_ld6b_pinctrl_socdata); }
-static const struct udevice_id ph1_ld6b_pinctrl_match[] = { +static const struct udevice_id uniphier_ld6b_pinctrl_match[] = { { .compatible = "socionext,ph1-ld6b-pinctrl" }, { /* sentinel */ } };
-U_BOOT_DRIVER(ph1_ld6b_pinctrl) = { - .name = "ph1-ld6b-pinctrl", +U_BOOT_DRIVER(uniphier_ld6b_pinctrl) = { + .name = "uniphier-ld6b-pinctrl", .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(ph1_ld6b_pinctrl_match), - .probe = ph1_ld6b_pinctrl_probe, + .of_match = of_match_ptr(uniphier_ld6b_pinctrl_match), + .probe = uniphier_ld6b_pinctrl_probe, .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 60fbbaf..9ed7c74 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -9,7 +9,7 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin ph1_pro4_pins[] = { +static const struct uniphier_pinctrl_pin uniphier_pro4_pins[] = { };
static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53}; @@ -54,7 +54,7 @@ static const unsigned usb2_muxvals[] = {0, 0}; static const unsigned usb3_pins[] = {186, 187}; static const unsigned usb3_muxvals[] = {0, 0};
-static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { +static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(i2c0), @@ -76,7 +76,7 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(usb3), };
-static const char * const ph1_pro4_functions[] = { +static const char * const uniphier_pro4_functions[] = { "emmc", "i2c0", "i2c1", @@ -96,31 +96,31 @@ static const char * const ph1_pro4_functions[] = { "usb3", };
-static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = { - .pins = ph1_pro4_pins, - .pins_count = ARRAY_SIZE(ph1_pro4_pins), - .groups = ph1_pro4_groups, - .groups_count = ARRAY_SIZE(ph1_pro4_groups), - .functions = ph1_pro4_functions, - .functions_count = ARRAY_SIZE(ph1_pro4_functions), +static struct uniphier_pinctrl_socdata uniphier_pro4_pinctrl_socdata = { + .pins = uniphier_pro4_pins, + .pins_count = ARRAY_SIZE(uniphier_pro4_pins), + .groups = uniphier_pro4_groups, + .groups_count = ARRAY_SIZE(uniphier_pro4_groups), + .functions = uniphier_pro4_functions, + .functions_count = ARRAY_SIZE(uniphier_pro4_functions), .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE, };
-static int ph1_pro4_pinctrl_probe(struct udevice *dev) +static int uniphier_pro4_pinctrl_probe(struct udevice *dev) { - return uniphier_pinctrl_probe(dev, &ph1_pro4_pinctrl_socdata); + return uniphier_pinctrl_probe(dev, &uniphier_pro4_pinctrl_socdata); }
-static const struct udevice_id ph1_pro4_pinctrl_match[] = { +static const struct udevice_id uniphier_pro4_pinctrl_match[] = { { .compatible = "socionext,ph1-pro4-pinctrl" }, { /* sentinel */ } };
-U_BOOT_DRIVER(ph1_pro4_pinctrl) = { - .name = "ph1-pro4-pinctrl", +U_BOOT_DRIVER(uniphier_pro4_pinctrl) = { + .name = "uniphier-pro4-pinctrl", .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(ph1_pro4_pinctrl_match), - .probe = ph1_pro4_pinctrl_probe, + .of_match = of_match_ptr(uniphier_pro4_pinctrl_match), + .probe = uniphier_pro4_pinctrl_probe, .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 30c9b4d..6597f1c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -9,7 +9,7 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin ph1_pro5_pins[] = { +static const struct uniphier_pinctrl_pin uniphier_pro5_pins[] = { UNIPHIER_PINCTRL_PIN(47, 0), UNIPHIER_PINCTRL_PIN(48, 0), UNIPHIER_PINCTRL_PIN(49, 0), @@ -67,7 +67,7 @@ static const unsigned usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {128, 129}; static const unsigned usb2_muxvals[] = {0, 0};
-static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { +static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(i2c0), @@ -91,7 +91,7 @@ static const struct uniphier_pinctrl_group ph1_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(usb2), };
-static const char * const ph1_pro5_functions[] = { +static const char * const uniphier_pro5_functions[] = { "emmc", "i2c0", "i2c1", @@ -110,31 +110,31 @@ static const char * const ph1_pro5_functions[] = { "usb2", };
-static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = { - .pins = ph1_pro5_pins, - .pins_count = ARRAY_SIZE(ph1_pro5_pins), - .groups = ph1_pro5_groups, - .groups_count = ARRAY_SIZE(ph1_pro5_groups), - .functions = ph1_pro5_functions, - .functions_count = ARRAY_SIZE(ph1_pro5_functions), +static struct uniphier_pinctrl_socdata uniphier_pro5_pinctrl_socdata = { + .pins = uniphier_pro5_pins, + .pins_count = ARRAY_SIZE(uniphier_pro5_pins), + .groups = uniphier_pro5_groups, + .groups_count = ARRAY_SIZE(uniphier_pro5_groups), + .functions = uniphier_pro5_functions, + .functions_count = ARRAY_SIZE(uniphier_pro5_functions), .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE, };
-static int ph1_pro5_pinctrl_probe(struct udevice *dev) +static int uniphier_pro5_pinctrl_probe(struct udevice *dev) { - return uniphier_pinctrl_probe(dev, &ph1_pro5_pinctrl_socdata); + return uniphier_pinctrl_probe(dev, &uniphier_pro5_pinctrl_socdata); }
-static const struct udevice_id ph1_pro5_pinctrl_match[] = { +static const struct udevice_id uniphier_pro5_pinctrl_match[] = { { .compatible = "socionext,ph1-pro5-pinctrl" }, { /* sentinel */ } };
-U_BOOT_DRIVER(ph1_pro5_pinctrl) = { - .name = "ph1-pro5-pinctrl", +U_BOOT_DRIVER(uniphier_pro5_pinctrl) = { + .name = "uniphier-pro5-pinctrl", .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(ph1_pro5_pinctrl_match), - .probe = ph1_pro5_pinctrl_probe, + .of_match = of_match_ptr(uniphier_pro5_pinctrl_match), + .probe = uniphier_pro5_pinctrl_probe, .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 976bb2f..cfec877 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -9,7 +9,7 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin proxstream2_pins[] = { +static const struct uniphier_pinctrl_pin uniphier_pxs2_pins[] = { UNIPHIER_PINCTRL_PIN(113, 0), UNIPHIER_PINCTRL_PIN(114, 0), UNIPHIER_PINCTRL_PIN(115, 0), @@ -61,7 +61,7 @@ static const unsigned usb2_muxvals[] = {8, 8}; static const unsigned usb3_pins[] = {62, 63}; static const unsigned usb3_muxvals[] = {8, 8};
-static const struct uniphier_pinctrl_group proxstream2_groups[] = { +static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(i2c0), @@ -85,7 +85,7 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = { UNIPHIER_PINCTRL_GROUP(usb3), };
-static const char * const proxstream2_functions[] = { +static const char * const uniphier_pxs2_functions[] = { "emmc", "i2c0", "i2c1", @@ -107,30 +107,30 @@ static const char * const proxstream2_functions[] = { "usb3", };
-static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = { - .pins = proxstream2_pins, - .pins_count = ARRAY_SIZE(proxstream2_pins), - .groups = proxstream2_groups, - .groups_count = ARRAY_SIZE(proxstream2_groups), - .functions = proxstream2_functions, - .functions_count = ARRAY_SIZE(proxstream2_functions), +static struct uniphier_pinctrl_socdata uniphier_pxs2_pinctrl_socdata = { + .pins = uniphier_pxs2_pins, + .pins_count = ARRAY_SIZE(uniphier_pxs2_pins), + .groups = uniphier_pxs2_groups, + .groups_count = ARRAY_SIZE(uniphier_pxs2_groups), + .functions = uniphier_pxs2_functions, + .functions_count = ARRAY_SIZE(uniphier_pxs2_functions), };
-static int proxstream2_pinctrl_probe(struct udevice *dev) +static int uniphier_pxs2_pinctrl_probe(struct udevice *dev) { - return uniphier_pinctrl_probe(dev, &proxstream2_pinctrl_socdata); + return uniphier_pinctrl_probe(dev, &uniphier_pxs2_pinctrl_socdata); }
-static const struct udevice_id proxstream2_pinctrl_match[] = { +static const struct udevice_id uniphier_pxs2_pinctrl_match[] = { { .compatible = "socionext,proxstream2-pinctrl" }, { /* sentinel */ } };
-U_BOOT_DRIVER(proxstream2_pinctrl) = { - .name = "proxstream2-pinctrl", +U_BOOT_DRIVER(uniphier_pxs2_pinctrl) = { + .name = "uniphier-pxs2-pinctrl", .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(proxstream2_pinctrl_match), - .probe = proxstream2_pinctrl_probe, + .of_match = of_match_ptr(uniphier_pxs2_pinctrl_match), + .probe = uniphier_pxs2_pinctrl_probe, .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 6cbf215..5a733b3 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -9,7 +9,7 @@
#include "pinctrl-uniphier.h"
-static const struct uniphier_pinctrl_pin ph1_sld8_pins[] = { +static const struct uniphier_pinctrl_pin uniphier_sld8_pins[] = { UNIPHIER_PINCTRL_PIN(32, 8), UNIPHIER_PINCTRL_PIN(33, 8), UNIPHIER_PINCTRL_PIN(34, 8), @@ -72,7 +72,7 @@ static const unsigned usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {114, 115}; static const unsigned usb2_muxvals[] = {1, 1};
-static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { +static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), UNIPHIER_PINCTRL_GROUP(i2c0), @@ -91,7 +91,7 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(usb2), };
-static const char * const ph1_sld8_functions[] = { +static const char * const uniphier_sld8_functions[] = { "emmc", "i2c0", "i2c1", @@ -108,30 +108,30 @@ static const char * const ph1_sld8_functions[] = { "usb2", };
-static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = { - .pins = ph1_sld8_pins, - .pins_count = ARRAY_SIZE(ph1_sld8_pins), - .groups = ph1_sld8_groups, - .groups_count = ARRAY_SIZE(ph1_sld8_groups), - .functions = ph1_sld8_functions, - .functions_count = ARRAY_SIZE(ph1_sld8_functions), +static struct uniphier_pinctrl_socdata uniphier_sld8_pinctrl_socdata = { + .pins = uniphier_sld8_pins, + .pins_count = ARRAY_SIZE(uniphier_sld8_pins), + .groups = uniphier_sld8_groups, + .groups_count = ARRAY_SIZE(uniphier_sld8_groups), + .functions = uniphier_sld8_functions, + .functions_count = ARRAY_SIZE(uniphier_sld8_functions), };
-static int ph1_sld8_pinctrl_probe(struct udevice *dev) +static int uniphier_sld8_pinctrl_probe(struct udevice *dev) { - return uniphier_pinctrl_probe(dev, &ph1_sld8_pinctrl_socdata); + return uniphier_pinctrl_probe(dev, &uniphier_sld8_pinctrl_socdata); }
-static const struct udevice_id ph1_sld8_pinctrl_match[] = { +static const struct udevice_id uniphier_sld8_pinctrl_match[] = { { .compatible = "socionext,ph1-sld8-pinctrl" }, { /* sentinel */ } };
-U_BOOT_DRIVER(ph1_sld8_pinctrl) = { - .name = "ph1-sld8-pinctrl", +U_BOOT_DRIVER(uniphier_sld8_pinctrl) = { + .name = "uniphier-sld8-pinctrl", .id = UCLASS_PINCTRL, - .of_match = of_match_ptr(ph1_sld8_pinctrl_match), - .probe = ph1_sld8_pinctrl_probe, + .of_match = of_match_ptr(uniphier_sld8_pinctrl_match), + .probe = uniphier_sld8_pinctrl_probe, .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops,
I found many mistakes in the initial version.
Fixes: 8a3328c209d0 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver") Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 3d5ac5f..fe154b7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -22,13 +22,13 @@ static const unsigned i2c3_muxvals[] = {1, 1}; static const unsigned i2c4_pins[] = {61, 62}; static const unsigned i2c4_muxvals[] = {1, 1}; static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, - 15, 16}; -static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0}; + 15, 16, 17}; +static const unsigned nand_muxvals[] = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 2}; static const unsigned nand_cs1_pins[] = {}; static const unsigned nand_cs1_muxvals[] = {}; static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17}; -static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8}; /* No SDVOLC */ +static const unsigned sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */ static const unsigned uart0_pins[] = {54, 55}; static const unsigned uart0_muxvals[] = {0, 0}; static const unsigned uart1_pins[] = {58, 59};
Because DT properties are 4-byte aligned, the pointer access *(fdt64_t *) in this code causes unaligned access.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/mach-uniphier/dram_init.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 815f243..ef0e2e8 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -6,6 +6,7 @@
#include <common.h> #include <libfdt.h> +#include <fdtdec.h> #include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR; @@ -40,8 +41,7 @@ int dram_init(void)
val += ac;
- gd->ram_size = sc == 2 ? fdt64_to_cpu(*(fdt64_t *)val) : - fdt32_to_cpu(*val); + gd->ram_size = fdtdec_get_number(val, sc);
debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
@@ -71,11 +71,9 @@ void dram_init_banksize(void)
for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells; i++, len -= cells) { - gd->bd->bi_dram[i].start = ac == 2 ? - fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val); + gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac); val += ac; - gd->bd->bi_dram[i].size = sc == 2 ? - fdt64_to_cpu(*(fdt64_t *)val) : fdt32_to_cpu(*val); + gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc); val += sc;
debug("DRAM bank %d: start = %08lx, size = %08lx\n",
This makes the EEPROM device on the Reference Daughter board available.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/dts/uniphier-ph1-ld20-ref.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts index 108adeb..1af2ebe 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts @@ -8,6 +8,7 @@
/dts-v1/; /include/ "uniphier-ph1-ld20.dtsi" +/include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi"
/ {
Currently, fdtgrep would not accept uniphier-ph1-ld20-ref.dtb and uniphier-ph1-ld11-ref.dtb unless the aliases node comes the first in the root node.
$ make -s uniphier_pxs2_ld6b_defconfig $ make CROSS_COMPILE=arm-linux-gnueabi- DEVICE_TREE=uniphier-ph1-ld20-ref [snip] LDS spl/u-boot-spl.lds LD spl/u-boot-spl OBJCOPY spl/u-boot-spl-nodtb.bin FDTGREP spl/u-boot-spl.dtb Error at 'fdt_find_regions': FDT_ERR_BADLAYOUT /aliases node must come before all other nodes Error: FDT_ERR_BADMAGIC make[1]: *** [spl/u-boot-spl.dtb] Error 1 make: *** [spl/u-boot-spl] Error 2
This commit moves the aliases node as the error message from the fdtgrep tool suggests, although this requirement does not sound reasonable to me.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/dts/uniphier-ph1-ld11-ref.dts | 18 +++++++++--------- arch/arm/dts/uniphier-ph1-ld20-ref.dts | 18 +++++++++--------- 2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ph1-ld11-ref.dts index a624a49..88e7f53 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld11-ref.dts @@ -14,15 +14,6 @@ model = "UniPhier PH1-LD11 Reference Board"; compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11";
- memory { - device_type = "memory"; - reg = <0 0x80000000 0 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial0 = &serial0; serial1 = &serial1; @@ -35,6 +26,15 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; };
ðsc { diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ph1-ld20-ref.dts index 1af2ebe..3049016 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ph1-ld20-ref.dts @@ -15,15 +15,6 @@ model = "UniPhier PH1-LD20 Reference Board"; compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
- memory { - device_type = "memory"; - reg = <0 0x80000000 0 0xc0000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - aliases { serial0 = &serial0; serial1 = &serial1; @@ -36,6 +27,15 @@ i2c4 = &i2c4; i2c5 = &i2c5; }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xc0000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; };
ðsc {
For PH1-LD20 or later, per-pin input-enable control is supported, that is, we need to set-up IECTRL registers for a group of pins. This helper function will be useful for a bunch of register settings.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/mach-uniphier/sg-regs.h | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 2cdc2db..4044245 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -126,6 +126,14 @@ static inline void sg_set_iectrl(unsigned pin) writel(tmp, reg); }
+static inline void sg_set_iectrl_range(unsigned min, unsigned max) +{ + int i; + + for (i = min; i <= max; i++) + sg_set_iectrl(i); +} + #endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */
No need to stop booting U-Boot even if boot mode is unknown. Setting the "bootmode" environment is only useful for booting Linux Kernel. Anyway, U-Boot has already booted by this point.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: - Newly added
Changes in v3: None Changes in v2: None
arch/arm/mach-uniphier/board_late_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 6e2008c..591b972 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -85,8 +85,8 @@ int board_late_init(void) setenv("bootmode", "usbboot"); break; default: - printf("Unsupported Boot Mode\n"); - return -1; + printf("Unknown\n"); + break; }
uniphier_set_fdt_file();
The current table look-up for the DTB file name turned out bothersome in terms of maintainability; I ended up adding a new entry every time a new board is supported.
There is a common pattern between the DT compatible string and the corresponding file name; drop the vendor prefix "socionext," and prefix it with "uniphier-" and suffix it with ".dtb".
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: - Newly added
Changes in v3: None Changes in v2: None
arch/arm/mach-uniphier/board_late_init.c | 62 ++++++++++++++++---------------- 1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 591b972..845f047 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -28,38 +28,37 @@ static void nand_denali_wp_disable(void) #endif }
-struct uniphier_fdt_file { - const char *compatible; - const char *file_name; -}; - -static const struct uniphier_fdt_file uniphier_fdt_files[] = { - { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", }, - { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", }, - { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", }, - { "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", }, - { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", }, - { "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", }, - { "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", }, - { "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", }, - { "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", }, - { "socionext,proxstream2-gentil", "uniphier-proxstream2-gentil.dtb", }, - { "socionext,proxstream2-vodka", "uniphier-proxstream2-vodka.dtb", }, -}; - -static void uniphier_set_fdt_file(void) +#define VENDOR_PREFIX "socionext," +#define DTB_FILE_PREFIX "uniphier-" + +static int uniphier_set_fdt_file(void) { DECLARE_GLOBAL_DATA_PTR; - int i; - - /* lookup DTB file name based on the compatible string */ - for (i = 0; i < ARRAY_SIZE(uniphier_fdt_files); i++) { - if (!fdt_node_check_compatible(gd->fdt_blob, 0, - uniphier_fdt_files[i].compatible)) { - setenv("fdt_file", uniphier_fdt_files[i].file_name); - return; - } - } + const char *compat; + char dtb_name[256]; + int buf_len = 256; + int ret; + + ret = fdt_get_string(gd->fdt_blob, 0, "compatible", &compat); + if (ret) + return -EINVAL; + + if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX))) + return -EINVAL; + + compat += strlen(VENDOR_PREFIX); + + strncat(dtb_name, DTB_FILE_PREFIX, buf_len); + buf_len -= strlen(DTB_FILE_PREFIX); + + strncat(dtb_name, compat, buf_len); + buf_len -= strlen(compat); + + strncat(dtb_name, ".dtb", buf_len); + + setenv("fdt_file", dtb_name); + + return 0; }
int board_late_init(void) @@ -89,7 +88,8 @@ int board_late_init(void) break; }
- uniphier_set_fdt_file(); + if (uniphier_set_fdt_file()) + printf("fdt_file environment was not set correctly\n");
return 0; }
This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: - Implement spin-table - Add timer_init - Add cci-500 init
Changes in v2: - Enable booti command - add early_clk_init func()
arch/arm/mach-uniphier/Kconfig | 5 + arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/arm64/Makefile | 10 + arch/arm/mach-uniphier/arm64/arm-cci500.c | 41 +++ arch/arm/mach-uniphier/arm64/mem_map.c | 28 ++ arch/arm/mach-uniphier/arm64/smp.S | 19 ++ arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 31 +++ arch/arm/mach-uniphier/arm64/timer.c | 38 +++ arch/arm/mach-uniphier/board_common.c | 6 +- arch/arm/mach-uniphier/board_early_init_f.c | 8 + arch/arm/mach-uniphier/boards.c | 25 ++ arch/arm/mach-uniphier/boot-mode/Makefile | 1 + arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 + arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c | 77 ++++++ arch/arm/mach-uniphier/boot-mode/boot-mode.c | 4 + arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c | 5 + arch/arm/mach-uniphier/clk/Makefile | 1 + arch/arm/mach-uniphier/clk/clk-ld20.c | 14 + arch/arm/mach-uniphier/cpu_info.c | 2 +- arch/arm/mach-uniphier/dram/Makefile | 1 + arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h | 41 +++ arch/arm/mach-uniphier/dram/umc-ld20-regs.h | 73 ++++++ arch/arm/mach-uniphier/dram/umc-ld20.c | 306 ++++++++++++++++++++++ arch/arm/mach-uniphier/early-clk/Makefile | 1 + arch/arm/mach-uniphier/early-clk/early-clk-ld20.c | 30 +++ arch/arm/mach-uniphier/init.h | 7 + arch/arm/mach-uniphier/init/Makefile | 1 + arch/arm/mach-uniphier/init/init-ld20.c | 53 ++++ arch/arm/mach-uniphier/init/init.c | 5 + arch/arm/mach-uniphier/memconf/Makefile | 1 + arch/arm/mach-uniphier/memconf/memconf-pxs2.c | 3 + arch/arm/mach-uniphier/pinctrl/Makefile | 1 + arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 46 ++++ arch/arm/mach-uniphier/sbc/Makefile | 1 + arch/arm/mach-uniphier/sg-regs.h | 3 +- configs/uniphier_ld20_defconfig | 28 ++ include/configs/uniphier.h | 47 +++- 37 files changed, 956 insertions(+), 10 deletions(-) create mode 100644 arch/arm/mach-uniphier/arm64/Makefile create mode 100644 arch/arm/mach-uniphier/arm64/arm-cci500.c create mode 100644 arch/arm/mach-uniphier/arm64/mem_map.c create mode 100644 arch/arm/mach-uniphier/arm64/smp.S create mode 100644 arch/arm/mach-uniphier/arm64/smp_kick_cpus.c create mode 100644 arch/arm/mach-uniphier/arm64/timer.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c create mode 100644 arch/arm/mach-uniphier/clk/clk-ld20.c create mode 100644 arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h create mode 100644 arch/arm/mach-uniphier/dram/umc-ld20-regs.h create mode 100644 arch/arm/mach-uniphier/dram/umc-ld20.c create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ld20.c create mode 100644 arch/arm/mach-uniphier/init/init-ld20.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c create mode 100644 configs/uniphier_ld20_defconfig
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 4724af5..87d1675 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC" select CPU_V7
+config ARCH_UNIPHIER_LD20 + bool "UniPhier PH1-LD20 SoC" + select ARM64 + select SPL_SEPARATE_BSS + endchoice
config ARCH_UNIPHIER_LD4 diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 35edca1..774ea99 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
obj-$(CONFIG_CPU_V7) += arm32/ +obj-$(CONFIG_ARM64) += arm64/ diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile new file mode 100644 index 0000000..5ed030a --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -0,0 +1,10 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y += timer.o +else +obj-y += mem_map.o smp.o smp_kick_cpus.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += arm-cci500.o +endif diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c new file mode 100644 index 0000000..607f96a --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c @@ -0,0 +1,41 @@ +/* + * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect + * + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define CCI500_BASE 0x5FD00000 +#define CCI500_SLAVE_OFFSET 0x1000 + +#define CCI500_SNOOP_CTRL +#define CCI500_SNOOP_CTRL_EN_DVM BIT(1) +#define CCI500_SNOOP_CTRL_EN_SNOOP BIT(0) + +void cci500_init(unsigned int nr_slaves) +{ + unsigned long slave_base = CCI500_BASE + CCI500_SLAVE_OFFSET; + int i; + + for (i = 0; i < nr_slaves; i++) { + void __iomem *base; + u32 tmp; + + base = map_sysmem(slave_base, SZ_4K); + + tmp = readl(base); + tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP; + writel(tmp, base); + + unmap_sysmem(base); + + slave_base += CCI500_SLAVE_OFFSET; + } +} diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c new file mode 100644 index 0000000..74ef919 --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/mem_map.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/types.h> +#include <asm/armv8/mmu.h> + +static struct mm_region uniphier_mem_map[] = { + { + .base = 0x00000000, + .size = 0x80000000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + .base = 0x80000000, + .size = 0xc0000000, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { /* sentinel */ } +}; + +struct mm_region *mem_map = uniphier_mem_map; diff --git a/arch/arm/mach-uniphier/arm64/smp.S b/arch/arm/mach-uniphier/arm64/smp.S new file mode 100644 index 0000000..9348ec9 --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/smp.S @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +ENTRY(uniphier_smp_setup) + mrs x0, s3_1_c15_c2_1 /* CPUECTLR_EL1 */ + orr x0, x0, #(1 << 6) /* SMPEN */ + msr s3_1_c15_c2_1, x0 + ret +ENDPROC(uniphier_smp_setup) + +ENTRY(uniphier_secondary_startup) + bl uniphier_smp_setup + b _start +ENDPROC(uniphier_secondary_startup) diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c new file mode 100644 index 0000000..64412e0 --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200 + +void uniphier_smp_setup(void); +void uniphier_secondary_startup(void); + +void uniphier_smp_kick_all_cpus(void) +{ + void __iomem *rom_boot_rsv0; + + rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); + + writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); + readq(rom_boot_rsv0); /* relax */ + + unmap_sysmem(rom_boot_rsv0); + + uniphier_smp_setup(); + + asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ +} diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c new file mode 100644 index 0000000..4beab9d --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/timer.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mapmem.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h> + +#define CNT_CONTROL_BASE 0x60E00000 + +#define CNTCR 0x000 +#define CNTCR_EN BIT(0) + +/* setup ARMv8 Generic Timer */ +int timer_init(void) +{ + void __iomem *base; + u32 tmp; + + base = map_sysmem(CNT_CONTROL_BASE, SZ_4K); + + /* + * Note: + * In a system that implements both Secure and Non-secure states, + * this register is only writable in Secure state. + */ + tmp = readl(base + CNTCR); + tmp |= CNTCR_EN; + writel(tmp, base + CNTCR); + + unmap_sysmem(base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c index 020ffca..330d690 100644 --- a/arch/arm/mach-uniphier/board_common.c +++ b/arch/arm/mach-uniphier/board_common.c @@ -8,9 +8,13 @@
#include "micro-support-card.h"
+void uniphier_smp_kick_all_cpus(void); + int board_init(void) { led_puts("Uboo"); - +#ifdef CONFIG_ARM64 + uniphier_smp_kick_all_cpus(); +#endif return 0; } diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 6f2adf1..2a7ae1b 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -62,6 +62,14 @@ int board_early_init_f(void) uniphier_pxs2_clk_init(); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + uniphier_ld20_pin_init(); + led_puts("U1"); + uniphier_ld20_clk_init(); + cci500_init(2); + break; +#endif default: break; } diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 0d2b94d..f0547c3 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = { }; #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20) +static const struct uniphier_board_data uniphier_ld20_data = { + .dram_freq = 1866, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0x100000000UL, + .size = 0x40000000, + .width = 32, + }, +}; +#endif + struct uniphier_board_id { const char *compatible; const struct uniphier_board_data *param; @@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { "socionext,ph1-ld6b", &uniphier_ld6b_data, }, #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + { "socionext,ph1-ld20", &uniphier_ld20_data, }, +#endif };
const struct uniphier_board_data *uniphier_get_board_param(void) diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 278df64..6cd096e 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h index 2e05a47..bd44d73 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-device.h +++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h @@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void); u32 uniphier_ld4_boot_device(void); u32 uniphier_pro5_boot_device(void); u32 uniphier_pxs2_boot_device(void); +u32 uniphier_ld20_boot_device(void);
void uniphier_sld3_boot_mode_show(void); void uniphier_ld4_boot_mode_show(void); void uniphier_pro5_boot_mode_show(void); void uniphier_pxs2_boot_mode_show(void); +void uniphier_ld20_boot_mode_show(void);
u32 spl_boot_device_raw(void);
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c new file mode 100644 index 0000000..100275e --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <linux/io.h> + +#include "../sg-regs.h" +#include "boot-device.h" + +static struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_NONE, "Reserved"}, +}; + +static int get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 uniphier_ld20_boot_device(void) +{ + int boot_mode; + + if (~readl(SG_PINMON0) & 0x00000780) + return BOOT_DEVICE_USB; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} + +void uniphier_ld20_boot_mode_show(void) +{ + int mode_sel, i; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); +} diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index b08cd6c..48e478c 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -39,6 +39,10 @@ u32 spl_boot_device_raw(void) case SOC_UNIPHIER_LD6B: return uniphier_pxs2_boot_device(); #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + return uniphier_ld20_boot_device(); +#endif default: return BOOT_DEVICE_NONE; } diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c index bccab62..fa97dc5 100644 --- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c @@ -39,6 +39,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) uniphier_pxs2_boot_mode_show(); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + uniphier_ld20_boot_mode_show(); + break; +#endif default: break; } diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index 1d736a5..93e9d91 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o diff --git a/arch/arm/mach-uniphier/clk/clk-ld20.c b/arch/arm/mach-uniphier/clk/clk-ld20.c new file mode 100644 index 0000000..556a30a --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ld20.c @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" + +void uniphier_ld20_clk_init(void) +{ +} diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index aae8d1f..f9646c0 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -48,7 +48,7 @@ int print_cpuinfo(void) puts("PH1-LD11 ()"); break; case 0x32: - puts("PH1-LD20 ()"); + puts("PH1-LD20 (SC1401AJ1)"); break; default: printf("Unknown Processor ID (0x%x)\n", revision); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 615ba2c..41aa53b 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ ddrphy-training.o ddrphy-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h new file mode 100644 index 0000000..b1b4cb0 --- /dev/null +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Socionext Inc. + */ + +#ifndef _DDRPHY_LD20_REGS_H +#define _DDRPHY_LD20_REGS_H + +#define PHY_SCL_DATA_0 0x00000104 +#define PHY_SCL_DATA_1 0x00000108 +#define PHY_SCL_LATENCY 0x0000010C +#define PHY_SCL_START 0x00000100 +#define PHY_SCL_CONFIG_1 0x00000118 +#define PHY_SCL_CONFIG_2 0x0000011C +#define PHY_PAD_CTRL 0x00000120 +#define PHY_DLL_RECALIB 0x00000124 +#define PHY_DLL_ADRCTRL 0x00000128 +#define PHY_LANE_SEL 0x0000012C +#define PHY_DLL_TRIM_1 0x00000130 +#define PHY_DLL_TRIM_2 0x00000134 +#define PHY_DLL_TRIM_3 0x00000138 +#define PHY_SCL_MAIN_CLK_DELTA 0x00000140 +#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C +#define PHY_WRLVL_DYN_ODT 0x00000150 +#define PHY_WRLVL_ON_OFF 0x00000154 +#define PHY_UNQ_ANALOG_DLL_1 0x0000015C +#define PHY_DLL_INCR_TRIM_1 0x00000164 +#define PHY_DLL_INCR_TRIM_3 0x00000168 +#define PHY_SCL_CONFIG_3 0x0000016C +#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170 +#define PHY_SCL_START_ADDR 0x00000188 +#define PHY_DSCL_CNT 0x0000019C +#define PHY_DLL_TRIM_CLK 0x000001A4 +#define PHY_DYNAMIC_BIT_LVL 0x000001AC +#define PHY_SCL_WINDOW_TRIM 0x000001B4 +#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8 +#define PHY_SCL_CONFIG_4 0x000001BC +#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0 +#define PHY_VREF_TRAINING 0x000001C8 +#define PHY_SCL_GATE_TIMING 0x000001E0 + +#endif /* _DDRPHY_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/umc-ld20-regs.h b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h new file mode 100644 index 0000000..46e513c --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-ld20-regs.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2016 Socionext Inc. + */ + +#ifndef UMC_LD20_REGS_H +#define UMC_LD20_REGS_H + +#define UMC_CMDCTLA 0x00000000 +#define UMC_CMDCTLB 0x00000004 +#define UMC_CMDCTLC 0x00000008 +#define UMC_INITCTLA 0x00000020 +#define UMC_INITCTLB 0x00000024 +#define UMC_INITCTLC 0x00000028 +#define UMC_DRMMR0 0x00000030 +#define UMC_DRMMR1 0x00000034 +#define UMC_DRMMR2 0x00000038 +#define UMC_DRMMR3 0x0000003C +#define UMC_INITSET 0x00000040 +#define UMC_INITSTAT 0x00000044 +#define UMC_CMDCTLE 0x00000050 +#define UMC_SPCSETB 0x00000084 +#define UMC_SPCSETB_AREFMD_MASK (0x3) /* Auto Refresh Mode */ +#define UMC_SPCSETB_AREFMD_ARB (0x0) /* control by arbitor */ +#define UMC_SPCSETB_AREFMD_CONT (0x1) /* control by DRAMCONT */ +#define UMC_SPCSETB_AREFMD_REG (0x2) /* control by register */ +#define UMC_ACSCTLA 0x000000C0 +#define UMC_ACSSETA 0x000000C4 +#define UMC_MEMCONF0A 0x00000200 +#define UMC_MEMCONF0B 0x00000204 +#define UMC_MEMCONFCH 0x00000240 +#define UMC_MEMMAPSET 0x00000250 +#define UMC_FLOWCTLA 0x00000400 +#define UMC_FLOWCTLB 0x00000404 +#define UMC_FLOWCTLC 0x00000408 +#define UMC_FLOWCTLG 0x00000508 +#define UMC_RDATACTL_D0 0x00000600 +#define UMC_WDATACTL_D0 0x00000604 +#define UMC_RDATACTL_D1 0x00000608 +#define UMC_WDATACTL_D1 0x0000060C +#define UMC_DATASET 0x00000610 +#define UMC_ODTCTL_D0 0x00000618 +#define UMC_ODTCTL_D1 0x0000061C +#define UMC_RESPCTL 0x00000624 +#define UMC_DIRECTBUSCTRLA 0x00000680 +#define UMC_DCCGCTL 0x00000720 +#define UMC_DICGCTLA 0x00000724 +#define UMC_DICGCTLB 0x00000728 +#define UMC_ERRMASKA 0x00000958 +#define UMC_ERRMASKB 0x0000095C +#define UMC_BSICMAPSET 0x00000988 +#define UMC_DIOCTLA 0x00000C00 +#define UMC_DIOCTLA_CTL_NRST BIT(8) /* ctl_rst_n */ +#define UMC_DIOCTLA_CFG_NRST BIT(0) /* cfg_rst_n */ +#define UMC_DFISTCTLC 0x00000C18 +#define UMC_DFICUPDCTLA 0x00000C20 +#define UMC_DFIPUPDCTLA 0x00000C30 +#define UMC_DFICSOVRRD 0x00000C84 +#define UMC_DFITURNOFF 0x00000C88 + +/* UM registers */ +#define UMC_MBUS0 0x00080004 +#define UMC_MBUS1 0x00081004 +#define UMC_MBUS2 0x00082004 +#define UMC_MBUS3 0x00000C78 +#define UMC_MBUS4 0x00000CF8 +#define UMC_MBUS5 0x00000E78 +#define UMC_MBUS6 0x00000EF8 +#define UMC_MBUS7 0x00001278 +#define UMC_MBUS8 0x000012F8 +#define UMC_MBUS9 0x00002478 +#define UMC_MBUS10 0x000024F8 + +#endif /* UMC_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c new file mode 100644 index 0000000..4614dac --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-ld20.c @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/sizes.h> +#include <asm/processor.h> + +#include "../init.h" +#include "ddrphy-ld20-regs.h" +#include "umc-ld20-regs.h" + +#define DRAM_CH_NR 3 + +enum dram_freq { + DRAM_FREQ_1866M, + DRAM_FREQ_NR, +}; + +enum dram_size { + DRAM_SZ_256M, + DRAM_SZ_512M, + DRAM_SZ_NR, +}; + +/* umc */ +static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; +static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; +static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; +static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; +static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; + +static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801}; +static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130}; +static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803}; + +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; +static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; +static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { + {0x0049071D, 0x0078071D}, +}; + +static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610}; +static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610}; +static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204}; +static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204}; +static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000}; + +static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E}; +static u32 umc_directbusctrla[DRAM_CH_NR] = { + 0x00000000, 0x00000001, 0x00000001 +}; + +/* DDR PHY */ +static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) +{ + writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); + while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) + cpu_relax(); + + writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); + writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); + writel(0x00000000, phy_base + PHY_LANE_SEL); + writel(0x00000005, phy_base + PHY_DLL_TRIM_1); + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); + writel(0x00000006, phy_base + PHY_LANE_SEL); + writel(0x00000005, phy_base + PHY_DLL_TRIM_1); + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); + writel(0x0000000c, phy_base + PHY_LANE_SEL); + writel(0x00000005, phy_base + PHY_DLL_TRIM_1); + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); + writel(0x00000012, phy_base + PHY_LANE_SEL); + writel(0x00000005, phy_base + PHY_DLL_TRIM_1); + writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); + writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); + writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); + writel(0x50bb40b1, phy_base + PHY_PAD_CTRL); + writel(0x00000070, phy_base + PHY_VREF_TRAINING); + writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); + writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); + writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); + writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); + writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); + writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING); + writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); + writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); + writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); + writel(0x00000000, phy_base + PHY_LANE_SEL); + writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); + writel(0xa800100d, phy_base + PHY_DLL_RECALIB); + writel(0x00005076, phy_base + PHY_SCL_LATENCY); +} + +static int ddrphy_training(void __iomem *phy_base) +{ + writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM); + writel(0x00010000, phy_base + PHY_DLL_TRIM_2); + writel(0x50000000, phy_base + PHY_SCL_START); + + while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + cpu_relax(); + + writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL); + writel(0xff00ff00, phy_base + PHY_SCL_DATA_0); + writel(0xff00ff00, phy_base + PHY_SCL_DATA_1); + writel(0x00080000, phy_base + PHY_SCL_START_ADDR); + writel(0x11000000, phy_base + PHY_SCL_START); + + while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + cpu_relax(); + + writel(0x00000000, phy_base + PHY_SCL_START_ADDR); + writel(0x30500000, phy_base + PHY_SCL_START); + + while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + cpu_relax(); + + writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL); + writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA); + writel(0x789b3de0, phy_base + PHY_SCL_DATA_0); + writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1); + writel(0x11000000, phy_base + PHY_SCL_START); + + while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + cpu_relax(); + + writel(0x34000000, phy_base + PHY_SCL_START); + + while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + cpu_relax(); + + writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL); + + return 0; +} + +static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, + unsigned long size, int ch) +{ + enum dram_size size_e; + + switch (size) { + case 0: + return 0; + case SZ_256M: + size_e = DRAM_SZ_256M; + break; + case SZ_512M: + size_e = DRAM_SZ_512M; + break; + default: + pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n", + size, ch); + return -EINVAL; + } + + /* Wait for PHY Init Complete */ + while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) + cpu_relax(); + + writel(0x00000001, dc_base + UMC_DFICSOVRRD); + writel(0x00000000, dc_base + UMC_DFITURNOFF); + + writel(umc_initctla[freq], dc_base + UMC_INITCTLA); + writel(umc_initctlb[freq], dc_base + UMC_INITCTLB); + writel(umc_initctlc[freq], dc_base + UMC_INITCTLC); + + writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0); + writel(0x00000004, dc_base + UMC_DRMMR1); + writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2); + writel(0x00000000, dc_base + UMC_DRMMR3); + + writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A); + writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B); + writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); + writel(0x00000008, dc_base + UMC_MEMMAPSET); + + writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); + writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); + writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); + writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE); + + writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0); + writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1); + + writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0); + writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1); + writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0); + writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1); + writel(umc_dataset[freq], dc_base + UMC_DATASET); + + writel(0x00400020, dc_base + UMC_DCCGCTL); + writel(0x00000003, dc_base + UMC_ACSCTLA); + writel(0x00000103, dc_base + UMC_FLOWCTLG); + writel(0x00010200, dc_base + UMC_ACSSETA); + + writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA); + writel(0x00004444, dc_base + UMC_FLOWCTLC); + writel(0x00000000, dc_base + UMC_DFICUPDCTLA); + + writel(0x00202000, dc_base + UMC_FLOWCTLB); + writel(0x00000000, dc_base + UMC_BSICMAPSET); + writel(0x00000000, dc_base + UMC_ERRMASKA); + writel(0x00000000, dc_base + UMC_ERRMASKB); + + writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA); + + writel(0x00000001, dc_base + UMC_INITSET); + /* Wait for PHY Init Complete */ + while (readl(dc_base + UMC_INITSTAT) & BIT(0)) + cpu_relax(); + + writel(0x2A0A0A00, dc_base + UMC_SPCSETB); + writel(0x00000000, dc_base + UMC_DFICSOVRRD); + + return 0; +} + +static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, + enum dram_freq freq, unsigned long size, int ch) +{ + void __iomem *dc_base = umc_ch_base + 0x00011000; + void __iomem *phy_base = phy_ch_base; + int ret; + + /* PHY Update Mode (ON) */ + writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA); + + /* deassert PHY reset signals */ + writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, + dc_base + UMC_DIOCTLA); + + ddrphy_init(phy_base, freq); + + ret = umc_dc_init(dc_base, freq, size, ch); + if (ret) + return ret; + + ret = ddrphy_training(phy_base); + if (ret) + return ret; + + return 0; +} + +static void um_init(void __iomem *um_base) +{ + writel(0x000000ff, um_base + UMC_MBUS0); + writel(0x000000ff, um_base + UMC_MBUS1); + writel(0x000000ff, um_base + UMC_MBUS2); + writel(0x00000001, um_base + UMC_MBUS3); + writel(0x00000001, um_base + UMC_MBUS4); + writel(0x00000001, um_base + UMC_MBUS5); + writel(0x00000001, um_base + UMC_MBUS6); + writel(0x00000001, um_base + UMC_MBUS7); + writel(0x00000001, um_base + UMC_MBUS8); + writel(0x00000001, um_base + UMC_MBUS9); + writel(0x00000001, um_base + UMC_MBUS10); +} + +int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) +{ + void __iomem *um_base = (void __iomem *)0x5b600000; + void __iomem *umc_ch_base = (void __iomem *)0x5b800000; + void __iomem *phy_ch_base = (void __iomem *)0x6e200000; + enum dram_freq freq; + int ch, ret; + + switch (bd->dram_freq) { + case 1866: + freq = DRAM_FREQ_1866M; + break; + default: + pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); + return -EINVAL; + } + + for (ch = 0; ch < bd->dram_nr_ch; ch++) { + unsigned long size = bd->dram_ch[ch].size; + unsigned int width = bd->dram_ch[ch].width; + + ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, + size / (width / 16), ch); + if (ret) { + pr_err("failed to initialize UMC ch%d\n", ch); + return ret; + } + + umc_ch_base += 0x00200000; + phy_ch_base += 0x00004000; + } + + um_init(um_base); + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 59058cd..9242b41 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c new file mode 100644 index 0000000..37adb37 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | + SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | + SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | + SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 3abf4aa..f5b3fa8 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); int uniphier_pro5_init(const struct uniphier_board_data *bd); int uniphier_pxs2_init(const struct uniphier_board_data *bd); +int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD) int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd); @@ -86,6 +87,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
@@ -93,6 +95,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); +int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pin_init(void); void uniphier_ld4_pin_init(void); @@ -101,11 +104,15 @@ void uniphier_sld8_pin_init(void); void uniphier_pro5_pin_init(void); void uniphier_pxs2_pin_init(void); void uniphier_ld6b_pin_init(void); +void uniphier_ld20_pin_init(void);
void uniphier_ld4_clk_init(void); void uniphier_pro4_clk_init(void); void uniphier_pro5_clk_init(void); void uniphier_pxs2_clk_init(void); +void uniphier_ld20_clk_init(void); + +void cci500_init(int nr_slaves);
#define pr_err(fmt, args...) printf(fmt, ##args)
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile index 34b15e3..b58e6c8 100644 --- a/arch/arm/mach-uniphier/init/Makefile +++ b/arch/arm/mach-uniphier/init/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c new file mode 100644 index 0000000..0ad264c --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +#include "../init.h" +#include "../micro-support-card.h" + +int uniphier_ld20_init(const struct uniphier_board_data *bd) +{ + uniphier_sbc_init_savepin(bd); + + support_card_reset(); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + uniphier_pxs2_memconf_init(bd); + + led_puts("L1"); + + uniphier_ld20_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = uniphier_ld20_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index c56c44c..15a53ce 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -55,6 +55,11 @@ void spl_board_init(void) uniphier_pxs2_init(param); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + uniphier_ld20_init(param); + break; +#endif default: break; } diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile index 78bb677..6ed1419 100644 --- a/arch/arm/mach-uniphier/memconf/Makefile +++ b/arch/arm/mach-uniphier/memconf/Makefile @@ -6,3 +6,4 @@ obj-y += memconf.o obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += memconf-pxs2.o diff --git a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c index bf14d0d..e98eb48 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c +++ b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c @@ -49,6 +49,9 @@ int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd) case SZ_512M: tmp |= SG_MEMCONF_CH2_SZ_512M; break; + case SZ_1G: + tmp |= SG_MEMCONF_CH2_SZ_1G; + break; default: pr_err("error: unsupported DRAM Ch2 size\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index 5504c24..b579cb0 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c new file mode 100644 index 0000000..6066b16 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sg-regs.h" + +void uniphier_ld20_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */ + sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */ + sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */ + sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */ + sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */ + sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */ + sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */ + sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */ + sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */ + sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */ + sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */ + sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */ + sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */ + sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ + sg_set_iectrl_range(3, 17); +#endif + +#ifdef CONFIG_USB_XHCI_UNIPHIER + sg_set_pinsel(46, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(47, 0, 8, 4); /* USB0OD -> USB0OD */ + sg_set_pinsel(48, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(49, 0, 8, 4); /* USB1OD -> USB1OD */ + sg_set_pinsel(50, 0, 8, 4); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(51, 0, 8, 4); /* USB2OD -> USB2OD */ + sg_set_pinsel(52, 0, 8, 4); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(53, 0, 8, 4); /* USB3OD -> USB3OD */ + sg_set_iectrl_range(46, 53); +#endif +} diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index e515af9..3c1e92a 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 4044245..1d71ce8 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -50,10 +50,11 @@ #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16)) #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24) #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) -/* PH1-LD6b, ProXstream2 only */ +/* PH1-LD6b, ProXstream2, PH1-LD20 only */ #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4) diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig new file mode 100644 index 0000000..3a5bf02 --- /dev/null +++ b/configs/uniphier_ld20_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_LD20=y +CONFIG_MICRO_SUPPORT_CARD=y +CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +# CONFIG_CMD_MISC is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_MMC_UNIPHIER=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_UNIPHIER_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index c6fc90f..fb405a9 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -71,8 +71,7 @@ /* serial console configuration */ #define CONFIG_BAUDRATE 115200
- -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) #define CONFIG_USE_ARCH_MEMSET #define CONFIG_USE_ARCH_MEMCPY #endif @@ -99,8 +98,18 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 1
+#ifdef CONFIG_ARM64 +#define CONFIG_ARMV8_MULTIENTRY +#define CPU_RELEASE_ADDR 0x80000100 +#define COUNTER_FREQUENCY 50000000 +#define CONFIG_GICV3 +#define GICD_BASE 0x5fe00000 +#define GICR_BASE 0x5fe80000 +#else /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 +#endif +
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_MAX_CHIPS 2 @@ -176,21 +185,34 @@ "bootm $fit_addr_r\0" \ "__nfsboot=run tftpboot\0" #else +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI +#define CONFIG_BOOTFILE "Image" +#define LINUXBOOT_CMD "booti" +#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" +#define KERNEL_SIZE "kernel_size=0x00c00000\0" +#define RAMDISK_ADDR "ramdisk_addr=0x00e00000\0" +#else #define CONFIG_CMD_BOOTZ #define CONFIG_BOOTFILE "zImage" +#define LINUXBOOT_CMD "bootz" +#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" +#define KERNEL_SIZE "kernel_size=0x00800000\0" +#define RAMDISK_ADDR "ramdisk_addr=0x00a00000\0" +#endif #define LINUXBOOT_ENV_SETTINGS \ "fdt_addr=0x00100000\0" \ "fdt_addr_r=0x84100000\0" \ "fdt_size=0x00008000\0" \ "kernel_addr=0x00200000\0" \ - "kernel_addr_r=0x80208000\0" \ - "kernel_size=0x00800000\0" \ - "ramdisk_addr=0x00a00000\0" \ + KERNEL_ADDR_R \ + KERNEL_SIZE \ + RAMDISK_ADDR \ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ - "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \ "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ @@ -238,14 +260,21 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \ +#if defined(CONFIG_ARM64) +#define CONFIG_SPL_TEXT_BASE 0x30000000 +#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ + defined(CONFIG_ARCH_UNIPHIER_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 #else #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#define CONFIG_SPL_STACK (0x3001c000) +#else #define CONFIG_SPL_STACK (0x00100000) +#endif #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_PANIC_HANG @@ -253,8 +282,10 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NOR_SUPPORT +#ifndef CONFIG_ARM64 #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_MMC_SUPPORT +#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -270,5 +301,7 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 #define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x30016000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */
The last 64 byte of each DDR channel of PH1-LD20 is periodically used as a scratch area for the DDR PHY training.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
include/configs/uniphier.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index fb405a9..a25ac8d 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -259,6 +259,8 @@
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 +/* for LD20; the last 64 byte is used for dynamic DDR PHY training */ +#define CONFIG_SYS_MEM_TOP_HIDE 64
#if defined(CONFIG_ARM64) #define CONFIG_SPL_TEXT_BASE 0x30000000
PH1-LD20 does not support 1.8V signaling for SD card; only Default Speed and High Speed (up to 50MHz) with 3.3V signaling is supported.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
arch/arm/dts/uniphier-ph1-ld20.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ph1-ld20.dtsi index fc1c6bf..f9cc3c4 100644 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ b/arch/arm/dts/uniphier-ph1-ld20.dtsi @@ -226,6 +226,23 @@ reg = <0x59801000 0x400>; };
+ mio: mioctrl@59810000 { + compatible = "socionext,ph1-ld20-mioctrl"; + reg = <0x59810000 0x800>; + #clock-cells = <1>; + }; + + sd: sdhc@5a400000 { + compatible = "socionext,uniphier-sdhc"; + status = "disabled"; + reg = <0x5a400000 0x800>; + interrupts = <0 76 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd>; + clocks = <&mio 0>; + bus-width = <4>; + }; + pinctrl: pinctrl@5f801000 { compatible = "socionext,ph1-ld20-pinctrl", "syscon"; reg = <0x5f801000 0xe00>;
PH1-LD20 needs this for its SD card controller.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
drivers/clk/uniphier/clk-uniphier-mio.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index d91ae34..a2b0e80 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -164,6 +164,10 @@ static const struct udevice_id uniphier_mio_clk_match[] = { .compatible = "socionext,proxstream2-mioctrl", .data = (ulong)&uniphier_mio_clk_data, }, + { + .compatible = "socionext,ph1-ld20-mioctrl", + .data = (ulong)&uniphier_mio_clk_data, + }, { /* sentinel */ } };
Copy the kernel image double-word-wise rather than byte-wise.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v4: None Changes in v3: None Changes in v2: None
include/configs/uniphier.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index a25ac8d..8ecfc6f 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -214,7 +214,8 @@ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ - "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \ + "setexpr kernel_size $kernel_size / 4 &&" \ + "cp $kernel_addr $kernel_addr_r $kernel_size &&" \ "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \ "run boot_common\0" \
2016-04-21 14:43 GMT+09:00 Masahiro Yamada yamada.masahiro@socionext.com:
Masahiro Yamada (13): pinctrl: uniphier: rename function/array names pinctrl: uniphier: fix NAND and SD pin-mux settings for PH1-LD11/LD20 ARM: uniphier: avoid unaligned access to DT on 64bit SoC ARM: dts: uniphier: use Ref Daughter board on PH1-LD20 Ref board ARM: dts: uniphier: move aliases node up to satisfy fdtgrep ARM: uniphier: add sg_set_iectrl_range() ARM: uniphier: carry on booting for Unknown boot mode ARM: uniphier: rework uniphier_set_fdt_file() ARM: uniphier: add PH1-LD20 SoC support ARM: uniphier: reserve the last 64 byte of SDRAM ARM: dts: uniphier: add SD controller node for PH1-LD20 clk: uniphier: add Media I/O clock driver support for PH1-LD20 ARM: uniphier: increase image load speed from NOR device
Series, applied to u-boot-uniphier/master.
participants (1)
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Masahiro Yamada