[U-Boot] [PATCH v2 0/4] enable support for x16 NAND devices

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[U-Boot] [PATCH] arm: Tegra: Use...

Pekon Gupta

30 Sep 2013 30 Sep '13

8:22 p.m.

*changes in v2* [PATCH 1/4]: - dropped NAND_BUSWIDTH_AUTO, instead using CONFIG_SYS_NAND_ONFI_DETECTION - added check in nand_flash_detect_onfi() for x8 mode [PATCH 2/4]: (new) Adds CONFIG_SYS_NAND_DEVICE_WIDTH - updated for auto-detection of bus-width in non-SPL and ONFI_DETECTION mode Refer: http://lists.denx.de/pipermail/u-boot/2013-September/163748.html [PATCH 3/4] <no update> [PATCH 4/4] disabled Pulls on output only I/O pads. - updated commit description to add details about NAND cape

*original v1* This series includes independent patch-sets aiming to enable x16 NAND support on AM33xx boards (like beaglebone-LT). [PATCH 1/4]: This patch is ported from linux driver/mtd/nand to allow detection device-width of NAND by reading ONFI parameter page. [PATCH 2/4]: enable NAND_BUSWIDTH_AUTO feature in omap_nand.c [PATCH 3/4]: cleaning of GPMC configs for NAND and NOR [PATCH 4/4]: enable x16 and x8 NAND device pin-muxing for beagle-bone LT (white)

---

Matthieu CASTET (1): [PATCH 1/4] mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width

Pekon Gupta (3): [PATCH 2/4] am33xx: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width [PATCH 3/4] am335x: fix GPMC config for NAND and NOR SPL boot [PATCH 4/4] am33xx: add support for beaglebone x16 NAND cape

-- 1.8.1

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Pekon Gupta

30 Sep 30 Sep

8:22 p.m.

New subject: [U-Boot] [PATCH v2 1/4] mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width

From: Matthieu CASTET matthieu.castet@parrot.com

This patch is modified version from following linux patch http://lists.infradead.org/pipermail/linux-mtd/2012-November/044803.html So retaining the authorship to Matthieu CASTET matthieu.castet@parrot.com

*Modifications from original patch* (1) use CONFIG_SYS_NAND_ONFI_DETECTION instead of (chip->options & NAND_BUSWIDTH_AUTO) (2) allow re-assigning of callbacks in nand_set_defaults() depending on bus-width

*Original patch message* The driver call nand_scan_ident in 8 bit mode, then readid or onfi detection are done (and detect bus width). The driver should update its bus width before calling nand_scan_tail.

This work because readid and onfi are read work 8 byte mode.

Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID, NAND_CMD_PARAM), address and read data The ONFI specificication is not very clear for x16 device if high byte of address should be driven to 0, but according to [1] it should be ok to not drive it during autodetection.

[1] 3.3.2. Target Initialization

[...] The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page.

Signed-off-by: Pekon Gupta pekon@ti.com --- drivers/mtd/nand/nand_base.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 9e05cef..4ef0edb 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2514,7 +2514,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)

if (!chip->select_chip) chip->select_chip = nand_select_chip; - if (!chip->read_byte) + if ((!chip->read_byte) || (chip->read_byte == nand_read_byte)) chip->read_byte = busw ? nand_read_byte16 : nand_read_byte; if (!chip->read_word) chip->read_word = nand_read_word; @@ -2522,11 +2522,11 @@ static void nand_set_defaults(struct nand_chip *chip, int busw) chip->block_bad = nand_block_bad; if (!chip->block_markbad) chip->block_markbad = nand_default_block_markbad; - if (!chip->write_buf) + if ((!chip->write_buf) || (chip->write_buf == nand_write_buf)) chip->write_buf = busw ? nand_write_buf16 : nand_write_buf; - if (!chip->read_buf) + if ((!chip->read_buf) || (chip->read_buf == nand_read_buf)) chip->read_buf = busw ? nand_read_buf16 : nand_read_buf; - if (!chip->verify_buf) + if ((!chip->verify_buf) || (chip->verify_buf == nand_verify_buf)) chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf; if (!chip->scan_bbt) chip->scan_bbt = nand_default_bbt; @@ -2575,6 +2575,10 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int i; int val;

+ if (chip->options & NAND_BUSWIDTH_16) { + printf("nand: error: ONFI detection works only in x8 mode\n"); + return 0; + } /* Try ONFI for unknown chip or LP */ chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1); if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' || @@ -2976,6 +2980,14 @@ ident_done: if (nand_manuf_ids[maf_idx].id == *maf_id) break; } +#if defined(CONFIG_SYS_NAND_ONFI_DETECTION) + if (chip->options & NAND_BUSWIDTH_16) { + return ERR_PTR(-EINVAL); + } else { + chip->options |= busw; + nand_set_defaults(chip, busw); + } +#endif

/* * Check, if buswidth is correct. Hardware drivers should set

-- 1.8.1

Scott Wood

8 Oct 8 Oct

11:08 p.m.

New subject: [U-Boot] [PATCH v2 1/4] mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width

On Mon, 2013-09-30 at 23:52 +0530, Pekon Gupta wrote:

...

From: Matthieu CASTET matthieu.castet@parrot.com

This patch is modified version from following linux patch http://lists.infradead.org/pipermail/linux-mtd/2012-November/044803.html So retaining the authorship to Matthieu CASTET matthieu.castet@parrot.com

*Modifications from original patch* (1) use CONFIG_SYS_NAND_ONFI_DETECTION instead of (chip->options & NAND_BUSWIDTH_AUTO) (2) allow re-assigning of callbacks in nand_set_defaults() depending on bus-width

*Original patch message* The driver call nand_scan_ident in 8 bit mode, then readid or onfi detection are done (and detect bus width). The driver should update its bus width before calling nand_scan_tail.

This work because readid and onfi are read work 8 byte mode.

Note that nand_scan_ident send command (NAND_CMD_RESET, NAND_CMD_READID, NAND_CMD_PARAM), address and read data The ONFI specificication is not very clear for x16 device if high byte of address should be driven to 0, but according to [1] it should be ok to not drive it during autodetection.

[1] 3.3.2. Target Initialization

[...] The Read ID and Read Parameter Page commands only use the lower 8-bits of the data bus. The host shall not issue commands that use a word data width on x16 devices until the host determines the device supports a 16-bit data bus width in the parameter page.

Signed-off-by: Pekon Gupta pekon@ti.com

drivers/mtd/nand/nand_base.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 9e05cef..4ef0edb 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2514,7 +2514,7 @@ static void nand_set_defaults(struct nand_chip *chip, int busw)

if (!chip->select_chip) chip->select_chip = nand_select_chip;

if (!chip->read_byte)

if ((!chip->read_byte) || (chip->read_byte == nand_read_byte)) chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;

Unnecessary parens (and doesn't match equivalent Linux code).

This change corresponds to Linux commit 68e8078072e802e77134664f11d2ffbfbd2f8fbe.

-Scott

Scott Wood

11:26 p.m.

New subject: [U-Boot] [PATCH v2 1/4] mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width

On Mon, 2013-09-30 at 23:52 +0530, Pekon Gupta wrote:

...

@@ -2575,6 +2575,10 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip, int i; int val;
if (chip->options & NAND_BUSWIDTH_16) {
printf("nand: error: ONFI detection works only in x8 mode\n");
return 0;
}

This should just fail silently, as I may be trying to probe a non-ONFI 16-bit chip (but don't want to disable ONFI support at compile time).

-Scott

Pekon Gupta

30 Sep 30 Sep

8:22 p.m.

New subject: [U-Boot] [PATCH v2 2/4] am33xx: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width

NAND driver needs to know bus-width of the connected NAND device, in order to perform proper I/O and initialize itself. Currently there is no CONFIG option to provide this information to NAND driver. - SPL NAND driver does not have framework to parse ONFI parameter page. - NAND drivers which cannot self initialize !defined(CONFIG_SYS_NAND_SELF_INIT) do not have any information about device bus-width during board_nand_init(), So, any device-width specific configurations are not possible there. - There should be some mechanism to pass device bus-width information for non-ONFI compliant devices.

This patch (1) adds CONFIG_SYS_NAND_DEVICE_WIDTH which can take following value 16: NAND device with x16 bus-width 8: NAND device with x8 bus-width (2) removes GPMC_NAND_ECC_LP_x16_LAYOUT, as NAND layout is determined based on ecc-scheme and oobsize during initialization in board_nand_init(). Thus this config is redundant.

diff --git a/doc/README.nand b/doc/README.nand index f9c921e..287eec5 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -179,6 +179,15 @@ Configuration Options: This is used by SoC platforms which do not have built-in ELM hardware engine required for BCH ECC correction.

+ CONFIG_SYS_NAND_DEVICE_WIDTH + Specifies bus-width of the default NAND device connected to SoC. + This config is useful for driver which cannot self initialize or + parse ONFI parameter (like SPL drivers), or for supporting non-ONFI + compliant devices. + This config can take following values: + - 8: x8 NAND devices is connected + - 16: x16 NAND device is connected + Platform specific options =========================

diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 24e6f8f..a7261f9 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -759,13 +759,19 @@ int board_nand_init(struct nand_chip *nand) nand->priv = &bch_priv; nand->cmd_ctrl = omap_nand_hwcontrol; nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; - /* If we are 16 bit dev, our gpmc config tells us that */ - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) - nand->options |= NAND_BUSWIDTH_16; - nand->chip_delay = 100; nand->ecc.layout = &omap_ecclayout;

+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_NAND_ONFI_DETECTION) + /* device bus-width determined from ONFI params */ + nand->options &= ~NAND_BUSWIDTH_16; +#else + /* device bus-width passed via CONFIG_xx */ + if (CONFIG_SYS_NAND_DEVICE_WIDTH == 16) + nand->options |= NAND_BUSWIDTH_16; + else + nand->options &= ~NAND_BUSWIDTH_16; +#endif /* select ECC scheme */ if (omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, CONFIG_SYS_NAND_PAGE_SIZE, @@ -782,5 +788,13 @@ int board_nand_init(struct nand_chip *nand) nand->dev_ready = omap_spl_dev_ready; #endif

+ /* reconfigure GPMC.CONFIG1 register with correct device-width */ + gpmc_config = readl(&gpmc_cfg->cs[cs].config1); + if (CONFIG_SYS_NAND_DEVICE_WIDTH == 16) + gpmc_config |= (0x1 << 12); + else + gpmc_config &= ~(0x1 << 12); + writel(gpmc_config, &gpmc_cfg->cs[cs].config1); + return 0; } diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 994e235..c2ccc97 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -216,6 +216,7 @@

#ifdef CONFIG_NAND #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_BLOCK_SIZE 131072 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 @@ -364,7 +365,6 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 1fd2508..0985221 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -269,7 +269,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE

#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */

@@ -332,6 +331,7 @@

#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */

@@ -326,6 +325,7 @@

/* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index bc5b66c..1e3dd0d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -164,8 +164,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* Environment information */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index cb79b4e..d6c64a3 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND @@ -318,6 +316,7 @@

#if defined(CONFIG_CMD_NET) diff --git a/include/configs/igep0033.h b/include/configs/igep0033.h index 3e18a65..ce6b9be 100644 --- a/include/configs/igep0033.h +++ b/include/configs/igep0033.h @@ -188,7 +188,6 @@ /* NAND support */ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION 1 @@ -248,11 +247,12 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 9982cf6..7e5bc9b 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -268,7 +268,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_BASE NAND_BASE -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ @@ -354,6 +353,7 @@

#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */

@@ -385,6 +384,7 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"

/* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c1245e7..9050f55 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -184,8 +184,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */

@@ -424,6 +422,7 @@

#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index ee6db51..e198c4c 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -298,7 +298,6 @@

#if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 88380a4..de06e20 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -120,8 +120,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND @@ -317,6 +315,7 @@

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c747d52..1dd7b9c 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -138,8 +138,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index cb8c7ec..9ca7fbe 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -158,7 +158,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1

/* Environment information */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 5426ee8..197accc 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -182,11 +182,12 @@ #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 10, 11, 12, 13, 14, 15, 16, 17, \ @@ -433,7 +434,6 @@ "\0"

#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 60dd8ff..1f31a87 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -188,7 +188,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M

#define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */

@@ -252,6 +251,7 @@ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000

/* NAND boot config */ +#define CONFIG_SYS_NAND_DEVICE_WIDTH 8 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_OOBSIZE 64 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 27db618..019052a 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -106,8 +106,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_BCH @@ -284,6 +282,7 @@

-- 1.8.1

Scott Wood

8 Oct 8 Oct

11:27 p.m.

New subject: [U-Boot] [PATCH v2 2/4] am33xx: add CONFIG_SYS_NAND_DEVICE_WIDTH to determine NAND device bus-width

On Mon, 2013-09-30 at 23:52 +0530, Pekon Gupta wrote:

...

+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_NAND_ONFI_DETECTION)

/* device bus-width determined from ONFI params */

nand->options &= ~NAND_BUSWIDTH_16;

+#else
/* device bus-width passed via CONFIG_xx */

if (CONFIG_SYS_NAND_DEVICE_WIDTH == 16)
nand->options |= NAND_BUSWIDTH_16;
else
nand->options &= ~NAND_BUSWIDTH_16;
+#endif

BTW, CONFIG_SYS_NAND_ONFI_DETECTION is misnamed -- it should be CONFIG_NAND_ONFI_DETECTION and it should only indicate whether we're building ONFI support, rather than making an assertion about whether the device actually is ONFI. You could do what the Linux driver does, and retry as 16-bit if an 8-bit ident fails.

-Scott

Pekon Gupta

30 Sep 30 Sep

8:22 p.m.

New subject: [U-Boot] [PATCH v2 3/4] am335x: fix GPMC config for NAND and NOR SPL boot

GPMC controller is common IP to interface with both NAND and NOR flash devices. Also, it supports max 8 chip-selects, which can be independently connected to any of the devices. But ROM code expects the boot-device to be connected to only chip-select[0]. Thus to resolve conflict between NOR and NAND boot. This patch: - combines NOR and NAND configs spread in board files to common gpmc_init() - configures GPMC based on boot-mode selected for SPL boot.

Signed-off-by: Pekon Gupta pekon@ti.com --- arch/arm/cpu/armv7/am33xx/mem.c | 48 +++++++++++++++++----------------- arch/arm/include/asm/arch-am33xx/mem.h | 5 ---- board/ti/am335x/board.c | 12 --------- 3 files changed, 24 insertions(+), 41 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index b6eb466..22ab25b 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -22,17 +22,6 @@

struct gpmc *gpmc_cfg;

-#if defined(CONFIG_CMD_NAND) -static const u32 gpmc_m_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, 0 -}; -#endif -

void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) @@ -61,11 +50,28 @@ void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - -#ifdef CONFIG_CMD_NAND - const u32 *gpmc_config = NULL; - u32 base = 0; - u32 size = 0; +#if defined(CONFIG_NOR) + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +static const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; #endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); @@ -81,12 +87,6 @@ void gpmc_init(void) */ writel(0, &gpmc_cfg->cs[0].config7); sdelay(1000); - -#ifdef CONFIG_CMD_NAND - gpmc_config = gpmc_m_nand; - - base = PISMO1_NAND_BASE; - size = PISMO1_NAND_SIZE; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); -#endif + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index 983ea28..e7e8c58 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -68,9 +68,4 @@ #define PISMO2_NAND_CS0 7 #define PISMO2_NAND_CS1 8

-/* make it readable for the gpmc_init */ -#define PISMO1_NOR_BASE FLASH_BASE -#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE -#define PISMO1_NAND_SIZE GPMC_SIZE_256M - #endif /* endif _MEM_H_ */ diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index cc04426..49d8fc9 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -333,22 +333,10 @@ void sdram_init(void) */ int board_init(void) { -#ifdef CONFIG_NOR - const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; -#endif - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

gpmc_init();

-#ifdef CONFIG_NOR - /* Reconfigure CS0 for NOR instead of NAND. */ - enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], - CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); -#endif - return 0; }

-- 1.8.1

Pekon Gupta

8:22 p.m.

New subject: [U-Boot] [PATCH v2 4/4] am33xx: add support for beaglebone x16 NAND cape

beaglebone board can be connected to expansion boards to add devices to them. These expansion boards are called 'capes'. This patch updates pin-mux for 'NAND' cape which can be used with beaglebone LT (white). Further information and datasheets of this NAND cape can be found at: - http://beagleboardtoys.info/index.php?title=BeagleBone_Memory_Expansion - http://beagleboardtoys.info/index.php?title=BeagleBone_4Gb_16-Bit_NAND_Modul...

*Specifics for Beaglebone Cape* (1) set CONFIG_SYS_NAND_DEVICE_WIDTH = 16 for detection of x16 NAND device

(2) On Memory-Expander Cape boot modes can be optionally be selected via DIP switch(SW2) present on cape board. SW2[SWITCH_BOOT] == 0: boot mode selected via DIP switch(SW2) SW2[SWITCH_BOOT] == 1: follow default boot order MMC-> SPI -> UART -> USB .. 24MHz

(2) As BOOTSEL values are sampled only at POR, so after changing any setting on SW2 (DIP switch), disconnect and reconnect all board power supply (including mini-USB) to POR the beaglebone.

Signed-off-by: Pekon Gupta pekon@ti.com --- board/ti/am335x/mux.c | 71 ++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 51 insertions(+), 20 deletions(-)

diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index b2bfda5..1985a78 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -171,25 +171,53 @@ static struct module_pin_mux mii1_pin_mux[] = { {-1}, };

-static struct module_pin_mux nand_pin_mux[] = { - {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ - {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ - {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ - {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ - {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ - {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ - {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ - {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ - {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ - {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ - {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ - {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ - {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ - {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ - {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ +#ifdef CONFIG_NAND +static struct module_pin_mux nand_x16_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_ad8), (MODE(0) | RXACTIVE)}, /* NAND AD8 */ + {OFFSET(gpmc_ad9), (MODE(0) | RXACTIVE)}, /* NAND AD9 */ + {OFFSET(gpmc_ad10), (MODE(0) | RXACTIVE)}, /* NAND AD10 */ + {OFFSET(gpmc_ad11), (MODE(0) | RXACTIVE)}, /* NAND AD11 */ + {OFFSET(gpmc_ad12), (MODE(0) | RXACTIVE)}, /* NAND AD12 */ + {OFFSET(gpmc_ad13), (MODE(0) | RXACTIVE)}, /* NAND AD13 */ + {OFFSET(gpmc_ad14), (MODE(0) | RXACTIVE)}, /* NAND AD14 */ + {OFFSET(gpmc_ad15), (MODE(0) | RXACTIVE)}, /* NAND AD15 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /*NAND WAIT*/ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /*NAND_WPN need pullup*/ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDDIS)}, /* NAND_CS0 */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDDIS)}, /* NAND_WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDDIS)}, /* NAND_OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDDIS)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDDIS)}, /* NAND_BE_CLE */ {-1}, };

+static struct module_pin_mux nand_x8_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /*NAND WAIT*/ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /*NAND_WPN need pullup*/ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDDIS)}, /* NAND_CS0 */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDDIS)}, /* NAND_WEN */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDDIS)}, /* NAND_OE */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDDIS)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDDIS)}, /* NAND_BE_CLE */ + {-1}, +}; +#endif #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) static struct module_pin_mux bone_norcape_pin_mux[] = { {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ @@ -336,11 +364,12 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) configure_module_pin_mux(i2c1_pin_mux); configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); -#ifndef CONFIG_NOR - configure_module_pin_mux(mmc1_pin_mux); -#endif #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) configure_module_pin_mux(bone_norcape_pin_mux); +#elif defined(CONFIG_NAND) + configure_module_pin_mux(nand_x16_pin_mux); +#else + configure_module_pin_mux(mmc1_pin_mux); #endif } else if (board_is_gp_evm(header)) { /* General Purpose EVM */ @@ -351,8 +380,10 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header) if (profile & ~PROFILE_2) configure_module_pin_mux(i2c1_pin_mux); /* Profiles 2 & 3 don't have NAND */ +#ifdef CONFIG_NAND if (profile & ~(PROFILE_2 | PROFILE_3)) - configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(nand_x8_pin_mux); +#endif else if (profile == PROFILE_2) { configure_module_pin_mux(mmc1_pin_mux); configure_module_pin_mux(spi0_pin_mux);

-- 1.8.1

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Pekon Gupta
Scott Wood