[U-Boot] [PATCH] platform: sifive: Embed unleashed DTS due to broken DT bindings
The DT bindings of upstream linux kernel have diverged and are not backward compatible so we embed a DTB in FW_PAYLOAD which follows upstream linux kernel DT bindings. The U-Boot drivers will also be fixed to use the updated DT bindings as-per upstream Linux kernel.
By embedding updated DTS in FW_PAYLOAD, we allow users to easily migrate to update DT bindings using OpenSBI+U-Boot.
Signed-off-by: Anup Patel anup.patel@wdc.com --- platform/sifive/fu540/HiFiveUnleashed.dts | 269 ++++++++++++++++++++++ platform/sifive/fu540/config.mk | 1 + 2 files changed, 270 insertions(+) create mode 100644 platform/sifive/fu540/HiFiveUnleashed.dts
diff --git a/platform/sifive/fu540/HiFiveUnleashed.dts b/platform/sifive/fu540/HiFiveUnleashed.dts new file mode 100644 index 0000000..13ea412 --- /dev/null +++ b/platform/sifive/fu540/HiFiveUnleashed.dts @@ -0,0 +1,269 @@ +/dts-v1/; + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "/soc/serial@10010000:115200"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0", "riscv,plic0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + gemgxlclk: cadence-gemgxl-mgmt@100a0000 { + compatible = "sifive,cadencegemgxlmgmt0"; + reg = <0x0 0x100a0000 0x0 0x1000>; + #clock-cells = <0x0>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci 3>; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci 3>; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci 3>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; + }; + ethernet@10090000 { + compatible = "cdns,macb"; + interrupt-parent = <&plic0>; + interrupts = <0x35>; + reg = <0x0 0x10090000 0x0 0x2000>; + reg-names = "control"; + local-mac-address = [70 b3 d5 92 f0 1f]; + phy-mode = "gmii"; + clock-names = "pclk", "hclk", "tx_clk"; + clocks = <&prci 0x1 &prci 0x1 &gemgxlclk>; + #address-cells = <0x1>; + #size-cells = <0x0>; + + ethernet-phy@0 { + reg = <0x0>; + }; + }; + }; +}; diff --git a/platform/sifive/fu540/config.mk b/platform/sifive/fu540/config.mk index fbb5db8..0e02d69 100644 --- a/platform/sifive/fu540/config.mk +++ b/platform/sifive/fu540/config.mk @@ -27,6 +27,7 @@ FW_JUMP_FDT_ADDR=0x82200000 FW_PAYLOAD=y FW_PAYLOAD_OFFSET=0x200000 FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_FDT=HiFiveUnleashed.dtb
# External Libraries to include PLATFORM_INCLUDE_LIBFDT=y
On Tue, Jun 18, 2019 at 2:47 PM Anup Patel Anup.Patel@wdc.com wrote:
The DT bindings of upstream linux kernel have diverged and are not backward compatible so we embed a DTB in FW_PAYLOAD which follows upstream linux kernel DT bindings. The U-Boot drivers will also be fixed to use the updated DT bindings as-per upstream Linux kernel.
By embedding updated DTS in FW_PAYLOAD, we allow users to easily migrate to update DT bindings using OpenSBI+U-Boot.
Signed-off-by: Anup Patel anup.patel@wdc.com
platform/sifive/fu540/HiFiveUnleashed.dts | 269 ++++++++++++++++++++++ platform/sifive/fu540/config.mk | 1 + 2 files changed, 270 insertions(+) create mode 100644 platform/sifive/fu540/HiFiveUnleashed.dts
diff --git a/platform/sifive/fu540/HiFiveUnleashed.dts b/platform/sifive/fu540/HiFiveUnleashed.dts new file mode 100644 index 0000000..13ea412 --- /dev/null +++ b/platform/sifive/fu540/HiFiveUnleashed.dts @@ -0,0 +1,269 @@ +/dts-v1/;
+/ {
#address-cells = <0x2>;#size-cells = <0x2>;model = "SiFive HiFive Unleashed A00";compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";aliases {serial0 = &uart0;serial1 = &uart1;};chosen {stdout-path = "/soc/serial@10010000:115200";};cpus {#address-cells = <1>;#size-cells = <0>;timebase-frequency = <1000000>;cpu0: cpu@0 {compatible = "sifive,e51", "sifive,rocket0", "riscv";device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <128>;i-cache-size = <16384>;reg = <0>;riscv,isa = "rv64imac";status = "disabled";cpu0_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu1: cpu@1 {compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <32>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <64>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <32>;mmu-type = "riscv,sv39";reg = <1>;riscv,isa = "rv64imafdc";tlb-split;cpu1_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu2: cpu@2 {clock-frequency = <0>;compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <32>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <64>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <32>;mmu-type = "riscv,sv39";reg = <2>;riscv,isa = "rv64imafdc";tlb-split;cpu2_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu3: cpu@3 {clock-frequency = <0>;compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <32>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <64>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <32>;mmu-type = "riscv,sv39";reg = <3>;riscv,isa = "rv64imafdc";tlb-split;cpu3_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};cpu4: cpu@4 {clock-frequency = <0>;compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";d-cache-block-size = <64>;d-cache-sets = <64>;d-cache-size = <32768>;d-tlb-sets = <1>;d-tlb-size = <32>;device_type = "cpu";i-cache-block-size = <64>;i-cache-sets = <64>;i-cache-size = <32768>;i-tlb-sets = <1>;i-tlb-size = <32>;mmu-type = "riscv,sv39";reg = <4>;riscv,isa = "rv64imafdc";tlb-split;cpu4_intc: interrupt-controller {#interrupt-cells = <1>;compatible = "riscv,cpu-intc";interrupt-controller;};};};memory@80000000 {device_type = "memory";reg = <0x0 0x80000000 0x2 0x00000000>;};hfclk: hfclk {#clock-cells = <0>;compatible = "fixed-clock";clock-frequency = <33333333>;clock-output-names = "hfclk";};rtcclk: rtcclk {#clock-cells = <0>;compatible = "fixed-clock";clock-frequency = <1000000>;clock-output-names = "rtcclk";};soc {#address-cells = <2>;#size-cells = <2>;compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";ranges;plic0: interrupt-controller@c000000 {#interrupt-cells = <1>;compatible = "sifive,plic-1.0.0", "riscv,plic0";reg = <0x0 0xc000000 0x0 0x4000000>;riscv,ndev = <53>;interrupt-controller;interrupts-extended = <&cpu0_intc 0xffffffff&cpu1_intc 0xffffffff &cpu1_intc 9&cpu2_intc 0xffffffff &cpu2_intc 9&cpu3_intc 0xffffffff &cpu3_intc 9&cpu4_intc 0xffffffff &cpu4_intc 9>;};prci: clock-controller@10000000 {compatible = "sifive,fu540-c000-prci";reg = <0x0 0x10000000 0x0 0x1000>;clocks = <&hfclk>, <&rtcclk>;#clock-cells = <1>;};gemgxlclk: cadence-gemgxl-mgmt@100a0000 {compatible = "sifive,cadencegemgxlmgmt0";reg = <0x0 0x100a0000 0x0 0x1000>;#clock-cells = <0x0>;};uart0: serial@10010000 {compatible = "sifive,fu540-c000-uart", "sifive,uart0";reg = <0x0 0x10010000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <4>;clocks = <&prci 3>;};uart1: serial@10011000 {compatible = "sifive,fu540-c000-uart", "sifive,uart0";reg = <0x0 0x10011000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <5>;clocks = <&prci 3>;};i2c0: i2c@10030000 {compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";reg = <0x0 0x10030000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <50>;clocks = <&prci 3>;reg-shift = <2>;reg-io-width = <1>;#address-cells = <1>;#size-cells = <0>;};qspi0: spi@10040000 {compatible = "sifive,fu540-c000-spi", "sifive,spi0";reg = <0x0 0x10040000 0x0 0x10000x0 0x20000000 0x0 0x10000000>;interrupt-parent = <&plic0>;interrupts = <51>;clocks = <&prci 3>;#address-cells = <1>;#size-cells = <0>;flash@0 {compatible = "issi,is25wp256", "jedec,spi-nor";reg = <0>;spi-max-frequency = <50000000>;m25p,fast-read;spi-tx-bus-width = <4>;spi-rx-bus-width = <4>;};};qspi1: spi@10041000 {compatible = "sifive,fu540-c000-spi", "sifive,spi0";reg = <0x0 0x10041000 0x0 0x10000x0 0x30000000 0x0 0x10000000>;interrupt-parent = <&plic0>;interrupts = <52>;clocks = <&prci 3>;#address-cells = <1>;#size-cells = <0>;};qspi2: spi@10050000 {compatible = "sifive,fu540-c000-spi", "sifive,spi0";reg = <0x0 0x10050000 0x0 0x1000>;interrupt-parent = <&plic0>;interrupts = <6>;clocks = <&prci 3>;#address-cells = <1>;#size-cells = <0>;mmc@0 {compatible = "mmc-spi-slot";reg = <0>;spi-max-frequency = <20000000>;voltage-ranges = <3300 3300>;disable-wp;};};ethernet@10090000 {compatible = "cdns,macb";interrupt-parent = <&plic0>;interrupts = <0x35>;reg = <0x0 0x10090000 0x0 0x2000>;reg-names = "control";local-mac-address = [70 b3 d5 92 f0 1f];phy-mode = "gmii";clock-names = "pclk", "hclk", "tx_clk";clocks = <&prci 0x1 &prci 0x1 &gemgxlclk>;#address-cells = <0x1>;#size-cells = <0x0>;ethernet-phy@0 {reg = <0x0>;};};};+}; diff --git a/platform/sifive/fu540/config.mk b/platform/sifive/fu540/config.mk index fbb5db8..0e02d69 100644 --- a/platform/sifive/fu540/config.mk +++ b/platform/sifive/fu540/config.mk @@ -27,6 +27,7 @@ FW_JUMP_FDT_ADDR=0x82200000 FW_PAYLOAD=y FW_PAYLOAD_OFFSET=0x200000 FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_FDT=HiFiveUnleashed.dtb
# External Libraries to include PLATFORM_INCLUDE_LIBFDT=y -- 2.17.1
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Sorry for the noise, this patch is for OpenSBI.
Please ignore it.
Regards, Anup
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