[U-Boot] [PATCH 01/16] gdsys: phy: Adapt fixup_88e1518() to latest Release Notes

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Mario Six

29 Mar 2019 29 Mar '19

10:18 a.m.

From: Dirk Eibach dirk.eibach@gdsys.cc

The initialization sequence in the newest release notes of the 88e1518 phy omits two commands.

Remove them from the sequence.

Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc --- board/gdsys/common/phy.c | 2 -- 1 file changed, 2 deletions(-)

diff --git a/board/gdsys/common/phy.c b/board/gdsys/common/phy.c index c4b2256da3a..d40c08d9e94 100644 --- a/board/gdsys/common/phy.c +++ b/board/gdsys/common/phy.c @@ -45,8 +45,6 @@ struct mii_setupcmd fixup_88e1518[] = { { MIICMD_SET, 16, 0x214d }, { MIICMD_SET, 17, 0xcc0c }, { MIICMD_SET, 16, 0x2159 }, - { MIICMD_SET, 22, 0x00fb }, - { MIICMD_SET, 7, 0xc00d }, { MIICMD_SET, 22, 0x0000 }, };

-- 2.20.1

Show replies by date

Mario Six

29 Mar 29 Mar

10:18 a.m.

New subject: [U-Boot] [PATCH 02/16] gdsys: Post ppc4xx removal cleanup

The ppc4xx architecture was removed, and with it several old gdsys 44x boards, but some "debris" from these purged boards was left over.

This patch removes these remnants (mostly entries in Makefiles, some now superfluous data structures and some now obsolete config variables from the whitelist).

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/common/Makefile | 4 -- board/gdsys/common/miiphybb.c | 127 ---------------------------------- include/gdsys_fpga.h | 96 ------------------------- 3 files changed, 227 deletions(-) delete mode 100644 board/gdsys/common/miiphybb.c

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index 9090933e345..ff8d6f49665 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -5,10 +5,6 @@

obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o -obj-$(CONFIG_IO) += miiphybb.o -obj-$(CONFIG_IO64) += miiphybb.o -obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o -obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o obj-$(CONFIG_CONTROLCENTERD) += dp501.o obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o diff --git a/board/gdsys/common/miiphybb.c b/board/gdsys/common/miiphybb.c deleted file mode 100644 index 042835d6af6..00000000000 --- a/board/gdsys/common/miiphybb.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#include <common.h> -#include <miiphy.h> - -#include <asm/io.h> - -struct io_bb_pinset { - int mdio; - int mdc; -}; - -static int io_bb_mii_init(struct bb_miiphy_bus *bus) -{ - return 0; -} - -static int io_bb_mdio_active(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) | pins->mdio); - - return 0; -} - -static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus) -{ - struct io_bb_pinset *pins = bus->priv; - - out_be32((void *)GPIO0_TCR, - in_be32((void *)GPIO0_TCR) & ~pins->mdio); - - return 0; -} - -static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdio); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdio); - - return 0; -} - -static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) -{ - struct io_bb_pinset *pins = bus->priv; - - *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); - - return 0; -} - -static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v) -{ - struct io_bb_pinset *pins = bus->priv; - - if (v) - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) | pins->mdc); - else - out_be32((void *)GPIO0_OR, - in_be32((void *)GPIO0_OR) & ~pins->mdc); - - return 0; -} - -static int io_bb_delay(struct bb_miiphy_bus *bus) -{ - udelay(1); - - return 0; -} - -struct io_bb_pinset io_bb_pinsets[] = { - { - .mdio = CONFIG_SYS_MDIO_PIN, - .mdc = CONFIG_SYS_MDC_PIN, - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .mdio = CONFIG_SYS_MDIO1_PIN, - .mdc = CONFIG_SYS_MDC1_PIN, - }, -#endif -}; - -struct bb_miiphy_bus bb_miiphy_buses[] = { - { - .name = CONFIG_SYS_GBIT_MII_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[0], - }, -#ifdef CONFIG_SYS_GBIT_MII1_BUSNAME - { - .name = CONFIG_SYS_GBIT_MII1_BUSNAME, - .init = io_bb_mii_init, - .mdio_active = io_bb_mdio_active, - .mdio_tristate = io_bb_mdio_tristate, - .set_mdio = io_bb_set_mdio, - .get_mdio = io_bb_get_mdio, - .set_mdc = io_bb_set_mdc, - .delay = io_bb_delay, - .priv = &io_bb_pinsets[1], - }, -#endif -}; - -int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index e9fb4b88b5e..eae67012622 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -86,81 +86,6 @@ struct ihs_fpga { }; #endif

-#ifdef CONFIG_IO -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[8181]; /* 0x0014 */ - u16 reflection_high; /* 0x3ffe */ -}; -#endif - -#ifdef CONFIG_IO64 -struct ihs_fpga_channel { - u16 status_int; - u16 config_int; - u16 switch_connect_config; - u16 tx_destination; -}; - -struct ihs_fpga_hicb { - u16 status_int; - u16 config_int; -}; - -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_features; /* 0x0004 */ - u16 fpga_version; /* 0x0006 */ - u16 reserved_0[5]; /* 0x0008 */ - u16 quad_serdes_reset; /* 0x0012 */ - u16 reserved_1[502]; /* 0x0014 */ - struct ihs_fpga_channel ch[32]; /* 0x0400 */ - struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */ - u16 reserved_2[7487]; /* 0x0580 */ - u16 reflection_high; /* 0x3ffe */ -}; -#endif - -#ifdef CONFIG_IOCON -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[1]; /* 0x0008 */ - u16 top_interrupt; /* 0x000a */ - u16 reserved_1[4]; /* 0x000c */ - struct ihs_gpio gpio; /* 0x0014 */ - u16 mpc3w_control; /* 0x001a */ - u16 reserved_2[2]; /* 0x001c */ - struct ihs_io_ep ep; /* 0x0020 */ - u16 reserved_3[9]; /* 0x002e */ - struct ihs_i2c i2c0; /* 0x0040 */ - u16 reserved_4[10]; /* 0x004c */ - u16 mc_int; /* 0x0060 */ - u16 mc_int_en; /* 0x0062 */ - u16 mc_status; /* 0x0064 */ - u16 mc_control; /* 0x0066 */ - u16 mc_tx_data; /* 0x0068 */ - u16 mc_tx_address; /* 0x006a */ - u16 mc_tx_cmd; /* 0x006c */ - u16 mc_res; /* 0x006e */ - u16 mc_rx_cmd_status; /* 0x0070 */ - u16 mc_rx_data; /* 0x0072 */ - u16 reserved_5[69]; /* 0x0074 */ - u16 reflection_high; /* 0x00fe */ - struct ihs_osd osd0; /* 0x0100 */ - u16 reserved_6[889]; /* 0x010e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) struct ihs_fpga { u16 reflection_low; /* 0x0000 */ @@ -270,25 +195,4 @@ struct ihs_fpga { }; #endif

-#ifdef CONFIG_DLVISION_10G -struct ihs_fpga { - u16 reflection_low; /* 0x0000 */ - u16 versions; /* 0x0002 */ - u16 fpga_version; /* 0x0004 */ - u16 fpga_features; /* 0x0006 */ - u16 reserved_0[10]; /* 0x0008 */ - u16 extended_interrupt; /* 0x001c */ - u16 reserved_1[29]; /* 0x001e */ - u16 mpc3w_control; /* 0x0058 */ - u16 reserved_2[3]; /* 0x005a */ - struct ihs_i2c i2c0; /* 0x0060 */ - u16 reserved_3[2]; /* 0x006c */ - struct ihs_i2c i2c1; /* 0x0070 */ - u16 reserved_4[194]; /* 0x007c */ - struct ihs_osd osd0; /* 0x0200 */ - u16 reserved_5[761]; /* 0x020e */ - u16 videomem0[2048]; /* 0x0800 */ -}; -#endif - #endif

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 03/16] gdsys: mpc8308: Fix style violations

Fix some style violations in the gdsys MPC8308 board files, and make the code more readable.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/mpc8308/hrcon.c | 55 ++++++++++++++++++----------------- board/gdsys/mpc8308/mpc8308.c | 12 ++++---- board/gdsys/mpc8308/strider.c | 49 ++++++++++++++++--------------- 3 files changed, 59 insertions(+), 57 deletions(-)

diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 2d709dee945..79e3b25de8c 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -35,11 +35,11 @@ #define MAX_MUX_CHANNELS 2

enum { - MCFPGA_DONE = 1 << 0, - MCFPGA_INIT_N = 1 << 1, - MCFPGA_PROGRAM_N = 1 << 2, - MCFPGA_UPDATE_ENABLE_N = 1 << 3, - MCFPGA_RESET_N = 1 << 4, + MCFPGA_DONE = BIT(0), + MCFPGA_INIT_N = BIT(1), + MCFPGA_PROGRAM_N = BIT(2), + MCFPGA_UPDATE_ENABLE_N = BIT(3), + MCFPGA_RESET_N = BIT(4), };

enum { @@ -47,7 +47,7 @@ enum { GPIO_MDIO = 1 << 15, };

-unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;

struct { @@ -107,7 +107,7 @@ int checkboard(void)

printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");

- if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -120,12 +120,11 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; u16 fpga_features; bool hw_type_cat = pca9698_get_value(0x20, 20); - bool ch0_rgmii2_present = false; + bool ch0_rgmii2_present;

FPGA_GET_REG(0, fpga_features, &fpga_features);

@@ -137,16 +136,16 @@ int last_stage_init(void)

/* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) { - unsigned int ctr = 0; + uint ctr = 0;

if (i2c_probe(mclink_controllers[k])) continue;

while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { - printf("no done for mclink_controller %d\n", k); + printf("no done for mclink_controller %u\n", k); break; } } @@ -159,8 +158,10 @@ int last_stage_init(void) }

if (hw_type_cat) { + uint mux_ch; int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -179,7 +180,7 @@ int last_stage_init(void) }

/* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500);

mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -207,6 +208,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -233,17 +235,17 @@ int last_stage_init(void) * provide access to fpga gpios and controls (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); }

-void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); }

-int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val;

@@ -252,7 +254,7 @@ int fpga_gpio_get(unsigned int bus, int pin) return val & pin; }

-void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val;

@@ -260,7 +262,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); }

-void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val;

@@ -273,7 +275,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 4, 1); }

-void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 4, state ? 0 : 1); } @@ -285,11 +287,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, (BIT(31 - 11) | BIT(31 - 12))); + setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); }

-int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 19); } @@ -367,7 +369,7 @@ int ft_board_setup(void *blob, bd_t *bd) */

struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -494,5 +496,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, };

-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 0112244fc79..9fe1d66c605 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,14 +24,14 @@

DECLARE_GLOBAL_DATA_PTR;

-int get_fpga_state(unsigned dev) +int get_fpga_state(uint dev) { return gd->arch.fpga_state[dev]; }

int board_early_init_f(void) { - unsigned k; + uint k;

for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; @@ -41,8 +41,8 @@ int board_early_init_f(void)

int board_early_init_r(void) { - unsigned k; - unsigned ctr; + uint k; + uint ctr;

for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) gd->arch.fpga_state[k] = 0; @@ -59,7 +59,7 @@ int board_early_init_r(void) for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) { ctr = 0; while (!mpc8308_get_fpga_done(k)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_DONE_FAILED; @@ -86,7 +86,7 @@ int board_early_init_r(void) if (val == REFLECTION_TESTPATTERN_INV) break;

- udelay(100000); + mdelay(100); if (ctr++ > 5) { gd->arch.fpga_state[k] |= FPGA_STATE_REFLECTION_FAILED; diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index fa26585296a..b1997f453ae 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -50,7 +50,7 @@ enum { GPIO_MDIO = 1 << 15, };

-unsigned int mclink_fpgacount; +uint mclink_fpgacount; struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;

struct { @@ -110,7 +110,7 @@ int checkboard(void)

printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");

- if (s != NULL) { + if (s) { puts(", serial# "); puts(s); } @@ -123,17 +123,17 @@ int checkboard(void) int last_stage_init(void) { int slaves; - unsigned int k; - unsigned int mux_ch; - unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; + uint k; + uint mux_ch; + uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; #ifdef CONFIG_STRIDER_CPU - unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; + uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 }; #endif bool hw_type_cat = pca9698_get_value(0x20, 18); #ifdef CONFIG_STRIDER_CON_DP bool is_dh = pca9698_get_value(0x20, 25); #endif - bool ch0_sgmii2_present = false; + bool ch0_sgmii2_present;

/* Turn on Analog Devices ADV7611 */ pca9698_direction_output(0x20, 8, 0); @@ -146,8 +146,8 @@ int last_stage_init(void)

/* wait for FPGA done, then reset FPGA */ for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) { - unsigned int ctr = 0; - unsigned char *mclink_controllers = mclink_controllers_dvi; + uint ctr = 0; + uchar *mclink_controllers = mclink_controllers_dvi;

#ifdef CONFIG_STRIDER_CPU if (i2c_probe(mclink_controllers[k])) { @@ -161,7 +161,7 @@ int last_stage_init(void) #endif while (!(pca953x_get_val(mclink_controllers[k]) & MCFPGA_DONE)) { - udelay(100000); + mdelay(100); if (ctr++ > 5) { printf("no done for mclink_controller %d\n", k); break; @@ -178,6 +178,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); @@ -196,7 +197,7 @@ int last_stage_init(void) }

/* give slave-PLLs and Parade DP501 some time to be up and running */ - udelay(500000); + mdelay(500);

mclink_fpgacount = CONFIG_SYS_MCLINK_MAX; slaves = mclink_probe(); @@ -235,7 +236,7 @@ int last_stage_init(void) for (k = 1; k <= slaves; ++k) FPGA_SET_REG(k, extended_control, 0x10); /* enable video */

- udelay(500000); + mdelay(500); #endif

for (k = 1; k <= slaves; ++k) { @@ -260,6 +261,7 @@ int last_stage_init(void) if (hw_type_cat) { int retval; struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) return -ENOMEM; strncpy(mdiodev->name, bb_miiphy_buses[k].name, @@ -286,17 +288,17 @@ int last_stage_init(void) * provide access to fpga gpios (for I2C bitbang) * (these may look all too simple but make iocon.h much more readable) */ -void fpga_gpio_set(unsigned int bus, int pin) +void fpga_gpio_set(uint bus, int pin) { FPGA_SET_REG(bus, gpio.set, pin); }

-void fpga_gpio_clear(unsigned int bus, int pin) +void fpga_gpio_clear(uint bus, int pin) { FPGA_SET_REG(bus, gpio.clear, pin); }

-int fpga_gpio_get(unsigned int bus, int pin) +int fpga_gpio_get(uint bus, int pin) { u16 val;

@@ -306,7 +308,7 @@ int fpga_gpio_get(unsigned int bus, int pin) }

#ifdef CONFIG_STRIDER_CON_DP -void fpga_control_set(unsigned int bus, int pin) +void fpga_control_set(uint bus, int pin) { u16 val;

@@ -314,7 +316,7 @@ void fpga_control_set(unsigned int bus, int pin) FPGA_SET_REG(bus, control, val | pin); }

-void fpga_control_clear(unsigned int bus, int pin) +void fpga_control_clear(uint bus, int pin) { u16 val;

@@ -328,7 +330,7 @@ void mpc8308_init(void) pca9698_direction_output(0x20, 26, 1); }

-void mpc8308_set_fpga_reset(unsigned state) +void mpc8308_set_fpga_reset(uint state) { pca9698_set_value(0x20, 26, state ? 0 : 1); } @@ -340,11 +342,11 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); - setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); }

-int mpc8308_get_fpga_done(unsigned fpga) +int mpc8308_get_fpga_done(uint fpga) { return pca9698_get_value(0x20, 20); } @@ -422,7 +424,7 @@ int ft_board_setup(void *blob, bd_t *bd) */

struct fpga_mii { - unsigned fpga; + uint fpga; int mdio; } fpga_mii[] = { { 0, 1}, @@ -549,5 +551,4 @@ struct bb_miiphy_bus bb_miiphy_buses[] = { }, };

-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / - sizeof(bb_miiphy_buses[0]); +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 04/16] gdsys: mpc8308: Use shadow register for output GPIO values

Since the gpio output status on MPC8xxx cannot be read back, it has to be buffered locally.

Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/mpc8308/hrcon.c | 4 ++-- board/gdsys/mpc8308/mpc8308.c | 19 +++++++++++++++++++ board/gdsys/mpc8308/mpc8308.h | 3 +++ board/gdsys/mpc8308/strider.c | 2 +- 4 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 79e3b25de8c..d14a28ec94d 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -287,8 +287,8 @@ void mpc8308_setup_hw(void) /* * set "startup-finished"-gpios */ - setbits_be32(&immr->gpio[0].dir, (BIT(31 - 11) | BIT(31 - 12))); - setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); + setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); }

int mpc8308_get_fpga_done(uint fpga) diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 9fe1d66c605..a53135b8fd0 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,6 +24,25 @@

DECLARE_GLOBAL_DATA_PTR;

+/* as gpio output status cannot be read back, we have to buffer it locally */ +u32 gpio0_out; + +void setbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out |= mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + +void clrbits_gpio0_out(u32 mask) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + gpio0_out &= ~mask; + out_be32(&immr->gpio[0].dat, gpio0_out); +} + int get_fpga_state(uint dev) { return gd->arch.fpga_state[dev]; diff --git a/board/gdsys/mpc8308/mpc8308.h b/board/gdsys/mpc8308/mpc8308.h index dc07d564eb5..1e4f24fb2ae 100644 --- a/board/gdsys/mpc8308/mpc8308.h +++ b/board/gdsys/mpc8308/mpc8308.h @@ -1,6 +1,9 @@ #ifndef __MPC8308_H_ #define __MPC8308_H_

+void setbits_gpio0_out(u32 mask); +void clrbits_gpio0_out(u32 mask); + /* functions to be provided by board implementation */ void mpc8308_init(void); void mpc8308_set_fpga_reset(unsigned state); diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index b1997f453ae..1fdea675bda 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -343,7 +343,7 @@ void mpc8308_setup_hw(void) * set "startup-finished"-gpios */ setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12)); - setbits_be32(&immr->gpio[0].dat, BIT(31 - 12)); + setbits_gpio0_out(BIT(31 - 12)); }

int mpc8308_get_fpga_done(uint fpga)

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 05/16] gdsys: mpc8308: Migrate SYS_FPGA{0, 1}_{BASE, SIZE} to Kconfig

Move CONFIG_SYS_FPGA0_BASE, CONFIG_SYS_FPGA0_SIZE, CONFIG_SYS_FPGA1_BASE, and CONFIG_SYS_FPGA1_SIZE to Kconfig.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/mpc8308/Kconfig | 22 ++++++++++++++++++++++ include/configs/hrcon.h | 8 -------- include/configs/strider.h | 8 -------- 3 files changed, 22 insertions(+), 16 deletions(-)

diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 9d99f686923..cad458ac710 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -4,6 +4,28 @@ config GDSYS_LEGACY_OSD_CMDS Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by gdsys devices.

+config SYS_FPGA0_BASE + hex + default E0600000 + help + The base address of the first FPGA's register map. + +config SYS_FPGA0_SIZE + hex + default 1 + help + The base address of the first FPGA's register map. + +config SYS_FPGA1_BASE + hex + help + The base address of the second FPGA's register map. + +config SYS_FPGA1_SIZE + hex + help + The base address of the second FPGA's register map. + if TARGET_HRCON

config SYS_BOARD diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h index 8029ae9dd75..6e6c1714ce9 100644 --- a/include/configs/hrcon.h +++ b/include/configs/hrcon.h @@ -129,14 +129,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */

-/* - * FPGA - */ -#define CONFIG_SYS_FPGA0_BASE 0xE0600000 -#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ - - -#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE #define CONFIG_SYS_FPGA_DONE(k) 0x0010

#define CONFIG_SYS_FPGA_COUNT 1 diff --git a/include/configs/strider.h b/include/configs/strider.h index 22d255aabb8..8b942e3446a 100644 --- a/include/configs/strider.h +++ b/include/configs/strider.h @@ -127,14 +127,6 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */

#define CONFIG_SYS_FPGA_COUNT 1

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 06/16] gdsys: mpc8308: Don't use manual RAM config if RAM driver is active

The "manual" RAM configuration should not be used if the DM RAM driver is active, hence, disable the code if the CONFIG_MPC83XX_SDRAM config variable is defined.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/mpc8308/sdram.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/board/gdsys/mpc8308/sdram.c b/board/gdsys/mpc8308/sdram.c index 3eb0e37b7b5..2a77fed2702 100644 --- a/board/gdsys/mpc8308/sdram.c +++ b/board/gdsys/mpc8308/sdram.c @@ -11,6 +11,8 @@ * board\freescale\mpc8315erdb\sdram.c */

+#ifndef CONFIG_MPC83XX_SDRAM + #include <common.h> #include <mpc83xx.h> #include <spd_sdram.h> @@ -81,3 +83,5 @@ int dram_init(void)

return 0; } + +#endif /* !CONFIG_MPC83XX_SDRAM */

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 07/16] gdsys: Introduce GDSYS_LEGACY_DRIVERS

Future gdsys boards will switch from the legacy drivers in board/gdsys/common to DM-based drivers.

Define a Kconfig option that disables the legacy drivers.

diff --git a/board/gdsys/common/adv7611.c b/board/gdsys/common/adv7611.c index c416bf1dc42..06cdc05825b 100644 --- a/board/gdsys/common/adv7611.c +++ b/board/gdsys/common/adv7611.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h>

@@ -174,3 +176,5 @@ out:

return res; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ch7301.c b/board/gdsys/common/ch7301.c index 1234149f42c..5e42467651d 100644 --- a/board/gdsys/common/ch7301.c +++ b/board/gdsys/common/ch7301.c @@ -6,6 +6,8 @@

/* Chrontel CH7301C DVI Transmitter */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -61,3 +63,5 @@ int ch7301_probe(unsigned screen, bool power)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/dp501.c b/board/gdsys/common/dp501.c index 69d4b8c3334..9ca69ebcbbe 100644 --- a/board/gdsys/common/dp501.c +++ b/board/gdsys/common/dp501.c @@ -6,6 +6,8 @@

/* Parade Technologies Inc. DP501 DisplayPort DVI/HDMI Transmitter */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -155,3 +157,5 @@ int dp501_probe(unsigned screen, bool power)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fanctrl.c b/board/gdsys/common/fanctrl.c index 5e776831dbb..27c875cbec0 100644 --- a/board/gdsys/common/fanctrl.c +++ b/board/gdsys/common/fanctrl.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h>

@@ -29,3 +31,5 @@ void init_fan_controller(u8 addr) val = i2c_reg_read(addr, FAN_CONFIG) | 0x04; i2c_reg_write(addr, FAN_CONFIG, val); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/fpga.c b/board/gdsys/common/fpga.c index f189e5fbd11..5ba6613ed56 100644 --- a/board/gdsys/common/fpga.c +++ b/board/gdsys/common/fpga.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <gdsys_fpga.h>

@@ -22,3 +24,5 @@ int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 8e105012479..91eec3ac7c1 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h>

#include <gdsys_fpga.h> @@ -234,3 +236,5 @@ void ioep_fpga_print_info(unsigned int fpga)

printf(", %d video channel(s)\n", feature_video_channels); } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c index bf89d4e2920..c43d24b26d4 100644 --- a/board/gdsys/common/mclink.c +++ b/board/gdsys/common/mclink.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <asm/io.h> #include <errno.h> @@ -134,3 +136,5 @@ int mclink_receive(u8 slave, u16 addr, u16 *data)

return 0; } + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c index 392d0059da8..10c43291469 100644 --- a/board/gdsys/common/osd.c +++ b/board/gdsys/common/osd.c @@ -4,6 +4,8 @@ * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS + #include <common.h> #include <i2c.h> #include <malloc.h> @@ -497,3 +499,5 @@ U_BOOT_CMD( "size_x(max. " __stringify(MAX_X_CHARS) ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n" ); + +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ \ No newline at end of file diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index cad458ac710..222ab0d20a3 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -4,6 +4,13 @@ config GDSYS_LEGACY_OSD_CMDS Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by gdsys devices.

+config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + config SYS_FPGA0_BASE hex default E0600000 @@ -40,6 +47,9 @@ config SYS_CONFIG_NAME config GDSYS_LEGACY_OSD_CMDS default y

+config GDSYS_LEGACY_DRIVERS + default y + endif

if TARGET_STRIDER @@ -55,6 +65,10 @@ config SYS_CONFIG_NAME

config GDSYS_LEGACY_OSD_CMDS default y + +config GDSYS_LEGACY_DRIVERS + default y + endif

config CMD_IOLOOP diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index a53135b8fd0..ae77fc2fd12 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -24,6 +24,7 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* as gpio output status cannot be read back, we have to buffer it locally */ u32 gpio0_out;

@@ -116,3 +117,4 @@ int board_early_init_r(void)

return 0; } +#endif diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig index 8514d086b97..f5154271d15 100644 --- a/board/gdsys/p1022/Kconfig +++ b/board/gdsys/p1022/Kconfig @@ -1,3 +1,10 @@ +config GDSYS_LEGACY_DRIVERS + bool + help + Enable the gdsys legacy drivers under board/gdsys/common. If this + option is not set, all relevant DM drivers must be configured for the + device in question. + if TARGET_CONTROLCENTERD

config SYS_BOARD @@ -9,4 +16,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "controlcenterd"

+config GDSYS_LEGACY_DRIVERS + default y + endif diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h index eae67012622..6d38a83d903 100644 --- a/include/gdsys_fpga.h +++ b/include/gdsys_fpga.h @@ -7,6 +7,7 @@ #ifndef __GDSYS_FPGA_H #define __GDSYS_FPGA_H

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS int init_func_fpga(void);

enum { @@ -33,6 +34,7 @@ extern struct ihs_fpga *fpga_ptr[]; &fpga_ptr[ix]->fld, \ offsetof(struct ihs_fpga, fld), \ val) +#endif

struct ihs_gpio { u16 read;

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 08/16] gdsys: mpc8308: Add FPGA flavor option

More recent versions of IHS FPGAs feature a different memory layout.

Add a Kconfig option to differentiate between the legacy layout, and the new layout (which is used on the upcoming "Gazerbeam" and later boards).

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/mpc8308/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)

diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index 222ab0d20a3..e6a47960547 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -71,7 +71,27 @@ config GDSYS_LEGACY_DRIVERS

endif

+if TARGET_HRCON || TARGET_STRIDER + +choice + prompt "FPGA flavor selection" + +config SYS_FPGA_FLAVOR_LEGACY + bool "Legacy flavor" + help + This enables support for the gdsys pre-Gazerbeam FPGA memory layout. + +config SYS_FPGA_FLAVOR_GAZERBEAM + bool "Gazerbeam flavor" + help + This enables support for the gdsys FPGA memory layout of the + Gazerbeam board. + +endchoice + config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help These commands provide FPGA tests. + +endif

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 09/16] gdsys: cmd_ioloop: Fix style violations

Fix some style violations in the ioloop command, and make the code more readable where possible.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/common/cmd_ioloop.c | 78 ++++++++++++++++----------------- 1 file changed, 38 insertions(+), 40 deletions(-)

diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index 8e2f4071ef7..a53c80c0add 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -11,33 +11,33 @@ #include <gdsys_fpga.h>

enum { - STATE_TX_PACKET_BUILDING = 1<<0, - STATE_TX_TRANSMITTING = 1<<1, - STATE_TX_BUFFER_FULL = 1<<2, - STATE_TX_ERR = 1<<3, - STATE_RECEIVE_TIMEOUT = 1<<4, - STATE_PROC_RX_STORE_TIMEOUT = 1<<5, - STATE_PROC_RX_RECEIVE_TIMEOUT = 1<<6, - STATE_RX_DIST_ERR = 1<<7, - STATE_RX_LENGTH_ERR = 1<<8, - STATE_RX_FRAME_CTR_ERR = 1<<9, - STATE_RX_FCS_ERR = 1<<10, - STATE_RX_PACKET_DROPPED = 1<<11, - STATE_RX_DATA_LAST = 1<<12, - STATE_RX_DATA_FIRST = 1<<13, - STATE_RX_DATA_AVAILABLE = 1<<15, + STATE_TX_PACKET_BUILDING = BIT(0), + STATE_TX_TRANSMITTING = BIT(1), + STATE_TX_BUFFER_FULL = BIT(2), + STATE_TX_ERR = BIT(3), + STATE_RECEIVE_TIMEOUT = BIT(4), + STATE_PROC_RX_STORE_TIMEOUT = BIT(5), + STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6), + STATE_RX_DIST_ERR = BIT(7), + STATE_RX_LENGTH_ERR = BIT(8), + STATE_RX_FRAME_CTR_ERR = BIT(9), + STATE_RX_FCS_ERR = BIT(10), + STATE_RX_PACKET_DROPPED = BIT(11), + STATE_RX_DATA_LAST = BIT(12), + STATE_RX_DATA_FIRST = BIT(13), + STATE_RX_DATA_AVAILABLE = BIT(15), };

enum { - CTRL_PROC_RECEIVE_ENABLE = 1<<12, - CTRL_FLUSH_TRANSMIT_BUFFER = 1<<15, + CTRL_PROC_RECEIVE_ENABLE = BIT(12), + CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), };

enum { - IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = 1<<5, - IRQ_CPU_PACKET_TRANSMITTED_EVENT = 1<<6, - IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = 1<<7, - IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = 1<<8, + IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), + IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), + IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7), + IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), };

struct io_generic_packet { @@ -52,7 +52,7 @@ unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr;

-static void io_check_status(unsigned int fpga, u16 status, bool silent) +static void io_check_status(uint fpga, u16 status, bool silent) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | @@ -85,9 +85,9 @@ static void io_check_status(unsigned int fpga, u16 status, bool silent) printf("TX_ERR\n"); }

-static void io_send(unsigned int fpga, unsigned int size) +static void io_send(uint fpga, uint size) { - unsigned int k; + uint k; struct io_generic_packet packet = { .source_address = 1, .packet_type = 1, @@ -107,9 +107,8 @@ static void io_send(unsigned int fpga, unsigned int size) tx_ctr++; }

-static void io_receive(unsigned int fpga) +static void io_receive(uint fpga) { - unsigned int k = 0; u16 rx_tx_status;

FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); @@ -123,17 +122,15 @@ static void io_receive(unsigned int fpga) FPGA_GET_REG(fpga, ep.receive_data, &rx);

FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); - - ++k; } }

-static void io_reflect(unsigned int fpga) +static void io_reflect(uint fpga) { u16 buffer[128];

- unsigned int k = 0; - unsigned int n; + uint k = 0; + uint n; u16 rx_tx_status;

FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); @@ -166,8 +163,8 @@ static void io_reflect(unsigned int fpga) */ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int fpga; - unsigned int rate = 0; + uint fpga; + uint rate = 0; unsigned long long last_seen = 0;

if (argc < 2) @@ -181,10 +178,10 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (argc > 2) rate = simple_strtoul(argv[2], NULL, 10);

- /* enable receive path */ + /* Enable receive path */ FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE);

- /* set device address to dummy 1*/ + /* Set device address to dummy 1*/ FPGA_SET_REG(fpga, ep.device_address, 1);

rx_ctr = 0; tx_ctr = 0; err_ctr = 0; @@ -215,18 +212,19 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; }

+#define DISP_LINE_LEN 16 + /* * FPGA io-endpoint looptest * * Syntax: * ioloop {fpga} {size} {rate} */ -#define DISP_LINE_LEN 16 int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - unsigned int fpga; - unsigned int size; - unsigned int rate = 0; + uint fpga; + uint size; + uint rate = 0;

if (argc < 3) return CMD_RET_USAGE; @@ -273,7 +271,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) break; udelay(1000000 / rate); if (!(tx_ctr % rate)) - printf("d %lld, tx %llu, rx %llu, err %llu\n", + printf("d %llu, tx %llu, rx %llu, err %llu\n", tx_ctr - rx_ctr, tx_ctr, rx_ctr, err_ctr); }

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 10/16] gdsys: cmd_ioloop: Introduce commenting enum

Replace the boolean parameter of io_check_status that controls whether the status is printed or not with a documenting enum.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/common/cmd_ioloop.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index a53c80c0add..8f70c1eda22 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -10,6 +10,11 @@

#include <gdsys_fpga.h>

+enum status_print_type { + STATUS_LOUD = 0, + STATUS_SILENT = 1, +}; + enum { STATE_TX_PACKET_BUILDING = BIT(0), STATE_TX_TRANSMITTING = BIT(1), @@ -52,7 +57,7 @@ unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr;

-static void io_check_status(uint fpga, u16 status, bool silent) +static void io_check_status(uint fpga, u16 status, enum status_print_type type) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | STATE_RX_FRAME_CTR_ERR | STATE_RX_FCS_ERR | @@ -66,7 +71,7 @@ static void io_check_status(uint fpga, u16 status, bool silent) err_ctr++; FPGA_SET_REG(fpga, ep.rx_tx_status, status);

- if (silent) + if (type == STATUS_SILENT) return;

if (status & STATE_RX_PACKET_DROPPED) @@ -193,7 +198,7 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FPGA_GET_REG(fpga, top_interrupt, &top_int); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);

- io_check_status(fpga, rx_tx_status, true); + io_check_status(fpga, rx_tx_status, STATUS_SILENT); if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) io_reflect(fpga); @@ -260,7 +265,7 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) FPGA_GET_REG(fpga, top_interrupt, &top_int); FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status);

- io_check_status(fpga, rx_tx_status, false); + io_check_status(fpga, rx_tx_status, STATUS_LOUD); if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) io_send(fpga, size); if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS)

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 11/16] gdsys: cmd_ioloop: Make DM compatible

Make the ioloop command DM compatible, while keeping the old functionality for not-yet-converted boards.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/common/cmd_ioloop.c | 293 +++++++++++++++++++++++++++++++- 1 file changed, 288 insertions(+), 5 deletions(-)

diff --git a/board/gdsys/common/cmd_ioloop.c b/board/gdsys/common/cmd_ioloop.c index 8f70c1eda22..05a14ff1038 100644 --- a/board/gdsys/common/cmd_ioloop.c +++ b/board/gdsys/common/cmd_ioloop.c @@ -10,11 +10,25 @@

#include <gdsys_fpga.h>

+#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +#include <dm.h> +#include <misc.h> +#include <regmap.h> +#include <board.h> + +#include "../../../drivers/misc/gdsys_soc.h" +#include "../../../drivers/misc/gdsys_ioep.h" +#include "../../../drivers/misc/ihs_fpga.h" + +const int HEADER_WORDS = sizeof(struct io_generic_packet) / 2; +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ + enum status_print_type { STATUS_LOUD = 0, STATUS_SILENT = 1, };

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS enum { STATE_TX_PACKET_BUILDING = BIT(0), STATE_TX_TRANSMITTING = BIT(1), @@ -33,11 +47,6 @@ enum { STATE_RX_DATA_AVAILABLE = BIT(15), };

-enum { - CTRL_PROC_RECEIVE_ENABLE = BIT(12), - CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), -}; - enum { IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), @@ -45,6 +54,11 @@ enum { IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), };

+enum { + CTRL_PROC_RECEIVE_ENABLE = BIT(12), + CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), +}; + struct io_generic_packet { u16 target_address; u16 source_address; @@ -52,11 +66,16 @@ struct io_generic_packet { u8 bc; u16 packet_length; } __attribute__((__packed__)); +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

unsigned long long rx_ctr; unsigned long long tx_ctr; unsigned long long err_ctr; +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +struct udevice *dev; +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_check_status(uint fpga, u16 status, enum status_print_type type) { u16 mask = STATE_RX_DIST_ERR | STATE_RX_LENGTH_ERR | @@ -89,7 +108,39 @@ static void io_check_status(uint fpga, u16 status, enum status_print_type type) if (status & STATE_TX_ERR) printf("TX_ERR\n"); } +#else +static void io_check_status(struct udevice *dev, enum status_print_type type) +{ + u16 status = 0; + int ret;

+ ret = misc_call(dev, 0, NULL, 0, &status, 0); + if (!ret) + return; + + err_ctr++; + + if (type != STATUS_LOUD) + return; + + if (status & STATE_RX_PACKET_DROPPED) + printf("RX_PACKET_DROPPED, status %04x\n", status); + + if (status & STATE_RX_DIST_ERR) + printf("RX_DIST_ERR\n"); + if (status & STATE_RX_LENGTH_ERR) + printf("RX_LENGTH_ERR\n"); + if (status & STATE_RX_FRAME_CTR_ERR) + printf("RX_FRAME_CTR_ERR\n"); + if (status & STATE_RX_FCS_ERR) + printf("RX_FCS_ERR\n"); + + if (status & STATE_TX_ERR) + printf("TX_ERR\n"); +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_send(uint fpga, uint size) { uint k; @@ -111,7 +162,29 @@ static void io_send(uint fpga, uint size)

tx_ctr++; } +#else +static void io_send(struct udevice *dev, uint size) +{ + uint k; + u16 buffer[HEADER_WORDS + 128]; + struct io_generic_packet header = { + .source_address = 1, + .packet_type = 1, + .packet_length = size, + }; + const uint words = (size + 1) / 2; + + memcpy(buffer, &header, 2 * HEADER_WORDS); + for (k = 0; k < words; ++k) + buffer[k + HEADER_WORDS] = (2 * k + 1) + ((2 * k) << 8);

+ misc_write(dev, 0, buffer, HEADER_WORDS + words); + + tx_ctr++; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_receive(uint fpga) { u16 rx_tx_status; @@ -129,7 +202,17 @@ static void io_receive(uint fpga) FPGA_GET_REG(fpga, ep.rx_tx_status, &rx_tx_status); } } +#else +static void io_receive(struct udevice *dev) +{ + u16 buffer[HEADER_WORDS + 128];

+ if (!misc_read(dev, 0, buffer, 0)) + rx_ctr++; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS static void io_reflect(uint fpga) { u16 buffer[128]; @@ -159,7 +242,22 @@ static void io_reflect(uint fpga)

tx_ctr++; } +#else +static void io_reflect(struct udevice *dev) +{ + u16 buffer[HEADER_WORDS + 128]; + struct io_generic_packet *header; + + if (misc_read(dev, 0, buffer, 0)) + return; + + header = (struct io_generic_packet *)&buffer;

+ misc_write(dev, 0, buffer, HEADER_WORDS + header->packet_length); +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* * FPGA io-endpoint reflector * @@ -216,9 +314,60 @@ int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

return 0; } +#else +/* + * FPGA io-endpoint reflector + * + * Syntax: + * ioreflect {reportrate} + */ +int do_ioreflect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *fpga; + struct regmap *map; + uint rate = 0; + unsigned long long last_seen = 0; + + if (!dev) { + printf("No device selected\n"); + return 1; + } + + gdsys_soc_get_fpga(dev, &fpga); + regmap_init_mem(dev_ofnode(dev), &map); + + /* Enable receive path */ + misc_set_enabled(dev, true); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + uint top_int; + + ihs_fpga_get(map, top_interrupt, &top_int); + io_check_status(dev, STATUS_SILENT); + if ((top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) && + (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS)) + io_reflect(dev); + + if (rate) { + if (!(tx_ctr % rate) && (tx_ctr != last_seen)) + printf("refl %llu, err %llu\n", tx_ctr, + err_ctr); + last_seen = tx_ctr; + } + + if (ctrlc()) + break; + } + + return 0; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

#define DISP_LINE_LEN 16

+#ifdef CONFIG_GDSYS_LEGACY_DRIVERS /* * FPGA io-endpoint looptest * @@ -284,7 +433,122 @@ int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])

return 0; } +#else +/* + * FPGA io-endpoint looptest + * + * Syntax: + * ioloop {size} {rate} + */ +int do_ioloop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint size; + uint rate = 0; + struct udevice *fpga; + struct regmap *map; + + if (!dev) { + printf("No device selected\n"); + return 1; + }

+ gdsys_soc_get_fpga(dev, &fpga); + regmap_init_mem(dev_ofnode(dev), &map); + + if (argc < 2) + return CMD_RET_USAGE; + + /* + * packet size is specified since argc > 1 + */ + size = simple_strtoul(argv[2], NULL, 10); + + /* + * If another parameter, it is the test rate in packets per second. + */ + if (argc > 2) + rate = simple_strtoul(argv[3], NULL, 10); + + /* Enable receive path */ + misc_set_enabled(dev, true); + + rx_ctr = 0; tx_ctr = 0; err_ctr = 0; + + while (1) { + uint top_int; + + if (ctrlc()) + break; + + ihs_fpga_get(map, top_interrupt, &top_int); + + io_check_status(dev, STATUS_LOUD); + if (top_int & IRQ_CPU_TRANSMITBUFFER_FREE_STATUS) + io_send(dev, size); + if (top_int & IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS) + io_receive(dev); + + if (rate) { + udelay(1000000 / rate); + if (!(tx_ctr % rate)) + printf("d %llu, tx %llu, rx %llu, err %llu\n", + tx_ctr - rx_ctr, tx_ctr, rx_ctr, + err_ctr); + } + } + return 0; +} +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifndef CONFIG_GDSYS_LEGACY_DRIVERS +int do_iodev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *ioep = NULL; + struct udevice *board; + char name[8]; + int ret; + + if (board_get(&board)) + return CMD_RET_FAILURE; + + if (argc > 1) { + int i = simple_strtoul(argv[1], NULL, 10); + + snprintf(name, sizeof(name), "ioep%d", i); + + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep); + + if (ret || !ioep) { + printf("Invalid IOEP %d\n", i); + return CMD_RET_FAILURE; + } + + dev = ioep; + } else { + int i = 0; + + while (1) { + snprintf(name, sizeof(name), "ioep%d", i); + + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep); + + if (ret || !ioep) + break; + + printf("IOEP %d:\t%s\n", i++, ioep->name); + } + + if (dev) + printf("\nSelected IOEP: %s\n", dev->name); + else + puts("\nNo IOEP selected.\n"); + } + + return 0; +} +#endif /* !CONFIG_GDSYS_LEGACY_DRIVERS */ + +#ifdef CONFIG_GDSYS_LEGACY_DRIVERS U_BOOT_CMD( ioloop, 4, 0, do_ioloop, "fpga io-endpoint looptest", @@ -296,3 +560,22 @@ U_BOOT_CMD( "fpga io-endpoint reflector", "fpga reportrate" ); +#else +U_BOOT_CMD( + ioloop, 3, 0, do_ioloop, + "fpga io-endpoint looptest", + "packetsize [packets/sec]" +); + +U_BOOT_CMD( + ioreflect, 2, 0, do_ioreflect, + "fpga io-endpoint reflector", + "reportrate" +); + +U_BOOT_CMD( + iodev, 2, 0, do_iodev, + "fpga io-endpoint listing/selection", + "[ioep device to select]" +); +#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 12/16] gdsys: ioep-fpga: Switch to gazerbeam-style reporting

Use a more extensive FPGA feature reporting style in the gdsys ioep-fpga driver.

Signed-off-by: Mario Six mario.six@gdsys.cc --- board/gdsys/common/ioep-fpga.c | 629 +++++++++++++++++++++++++-------- 1 file changed, 489 insertions(+), 140 deletions(-)

diff --git a/board/gdsys/common/ioep-fpga.c b/board/gdsys/common/ioep-fpga.c index 91eec3ac7c1..066222c563d 100644 --- a/board/gdsys/common/ioep-fpga.c +++ b/board/gdsys/common/ioep-fpga.c @@ -10,231 +10,580 @@

#include <gdsys_fpga.h>

-enum { - UNITTYPE_MAIN_SERVER = 0, - UNITTYPE_MAIN_USER = 1, - UNITTYPE_VIDEO_SERVER = 2, - UNITTYPE_VIDEO_USER = 3, +enum pcb_video_type { + PCB_DVI_SL, + PCB_DP_165MPIX, + PCB_DP_300MPIX, + PCB_HDMI, + PCB_DP_1_2, + PCB_HDMI_2_0, };

-enum { - UNITTYPEPCB_DVI = 0, - UNITTYPEPCB_DP_165 = 1, - UNITTYPEPCB_DP_300 = 2, - UNITTYPEPCB_HDMI = 3, +enum pcb_transmission_type { + PCB_CAT_1G, + PCB_FIBER_3G, + PCB_CAT_10G, + PCB_FIBER_10G, };

-enum { - COMPRESSION_NONE = 0, - COMPRESSION_TYPE_1 = 1, - COMPRESSION_TYPE_1_2 = 3, - COMPRESSION_TYPE_1_2_3 = 7, +enum carrier_speed { + CARRIER_SPEED_1G, + CARRIER_SPEED_3G, + CARRIER_SPEED_2_5G = CARRIER_SPEED_3G, + CARRIER_SPEED_10G, };

-enum { - AUDIO_NONE = 0, - AUDIO_TX = 1, - AUDIO_RX = 2, - AUDIO_RXTX = 3, +enum ram_config { + RAM_DDR2_32BIT_295MBPS, + RAM_DDR3_32BIT_590MBPS, + RAM_DDR3_48BIT_590MBPS, + RAM_DDR3_64BIT_1800MBPS, + RAM_DDR3_48BIT_1800MBPS, };

-enum { - SYSCLK_147456 = 0, +enum sysclock { + SYSCLK_147456, };

-enum { - RAM_DDR2_32 = 0, - RAM_DDR3_32 = 1, - RAM_DDR3_48 = 2, +struct fpga_versions { + bool video_channel; + bool con_side; + enum pcb_video_type pcb_video_type; + enum pcb_transmission_type pcb_transmission_type; + unsigned int hw_version; };

-enum { - CARRIER_SPEED_1G = 0, - CARRIER_SPEED_2_5G = 1, +struct fpga_features { + u8 video_channels; + u8 carriers; + enum carrier_speed carrier_speed; + enum ram_config ram_config; + enum sysclock sysclock; + + bool pcm_tx; + bool pcm_rx; + bool spdif_tx; + bool spdif_rx; + bool usb2; + bool rs232; + bool compression_type1; + bool compression_type2; + bool compression_type3; + bool interlace; + bool osd; + bool compression_pipes; };

-bool ioep_fpga_has_osd(unsigned int fpga) +#ifdef CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) { - u16 fpga_features; - unsigned feature_osd; + enum { + VERSIONS_FPGA_VIDEO_CHANNEL = BIT(12), + VERSIONS_FPGA_CON_SIDE = BIT(13), + VERSIONS_FPGA_SC = BIT(14), + VERSIONS_PCB_CON = BIT(9), + VERSIONS_PCB_SC = BIT(8), + VERSIONS_PCB_VIDEO_MASK = 0x3 << 6, + VERSIONS_PCB_VIDEO_DP_1_2 = 0x0 << 6, + VERSIONS_PCB_VIDEO_HDMI_2_0 = 0x1 << 6, + VERSIONS_PCB_TRANSMISSION_MASK = 0x3 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_10G = 0x0 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_10G = 0x1 << 4, + VERSIONS_PCB_TRANSMISSION_FIBER_3G = 0x2 << 4, + VERSIONS_PCB_TRANSMISSION_CAT_1G = 0x3 << 4, + VERSIONS_HW_VER_MASK = 0xf << 0, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + versions->video_channel = raw_versions & VERSIONS_FPGA_VIDEO_CHANNEL; + versions->con_side = raw_versions & VERSIONS_FPGA_CON_SIDE; + + switch (raw_versions & VERSIONS_PCB_VIDEO_MASK) { + case VERSIONS_PCB_VIDEO_DP_1_2: + versions->pcb_video_type = PCB_DP_1_2; + break; + + case VERSIONS_PCB_VIDEO_HDMI_2_0: + versions->pcb_video_type = PCB_HDMI_2_0; + break; + } + + switch (raw_versions & VERSIONS_PCB_TRANSMISSION_MASK) { + case VERSIONS_PCB_TRANSMISSION_FIBER_10G: + versions->pcb_transmission_type = PCB_FIBER_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_10G: + versions->pcb_transmission_type = PCB_CAT_10G; + break; + + case VERSIONS_PCB_TRANSMISSION_FIBER_3G: + versions->pcb_transmission_type = PCB_FIBER_3G; + break; + + case VERSIONS_PCB_TRANSMISSION_CAT_1G: + versions->pcb_transmission_type = PCB_CAT_1G; + break; + + }

- FPGA_GET_REG(0, fpga_features, &fpga_features); - feature_osd = fpga_features & (1<<11); + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;

- return feature_osd; + return 0; }

-void ioep_fpga_print_info(unsigned int fpga) +static int get_features(unsigned int fpga, struct fpga_features *features) { - u16 versions; - u16 fpga_version; - u16 fpga_features; - unsigned unit_type; - unsigned unit_type_pcb_video; - unsigned feature_compression; - unsigned feature_osd; - unsigned feature_audio; - unsigned feature_sysclock; - unsigned feature_ramconfig; - unsigned feature_carrier_speed; - unsigned feature_carriers; - unsigned feature_video_channels; - - FPGA_GET_REG(fpga, versions, &versions); - FPGA_GET_REG(fpga, fpga_version, &fpga_version); - FPGA_GET_REG(fpga, fpga_features, &fpga_features); - - unit_type = (versions & 0xf000) >> 12; - unit_type_pcb_video = (versions & 0x01c0) >> 6; - feature_compression = (fpga_features & 0xe000) >> 13; - feature_osd = fpga_features & (1<<11); - feature_audio = (fpga_features & 0x0600) >> 9; - feature_sysclock = (fpga_features & 0x0180) >> 7; - feature_ramconfig = (fpga_features & 0x0060) >> 5; - feature_carrier_speed = fpga_features & (1<<4); - feature_carriers = (fpga_features & 0x000c) >> 2; - feature_video_channels = fpga_features & 0x0003; - - switch (unit_type) { - case UNITTYPE_MAIN_SERVER: - case UNITTYPE_MAIN_USER: - printf("Mainchannel"); + enum { + FEATURE_SPDIF_RX = BIT(15), + FEATURE_SPDIF_TX = BIT(14), + FEATURE_PCM_RX = BIT(13), + FEATURE_PCM_TX = BIT(12), + FEATURE_RAM_MASK = GENMASK(11, 8), + FEATURE_RAM_DDR2_32BIT_295MBPS = 0x0 << 8, + FEATURE_RAM_DDR3_32BIT_590MBPS = 0x1 << 8, + FEATURE_RAM_DDR3_48BIT_590MBPS = 0x2 << 8, + FEATURE_RAM_DDR3_64BIT_1800MBPS = 0x3 << 8, + FEATURE_RAM_DDR3_48BIT_1800MBPS = 0x4 << 8, + FEATURE_CARRIER_SPEED_MASK = GENMASK(7, 6), + FEATURE_CARRIER_SPEED_1G = 0x0 << 6, + FEATURE_CARRIER_SPEED_2_5G = 0x1 << 6, + FEATURE_CARRIER_SPEED_10G = 0x2 << 6, + FEATURE_CARRIERS_MASK = GENMASK(5, 4), + FEATURE_CARRIERS_0 = 0x0 << 4, + FEATURE_CARRIERS_1 = 0x1 << 4, + FEATURE_CARRIERS_2 = 0x2 << 4, + FEATURE_CARRIERS_4 = 0x3 << 4, + FEATURE_USB2 = BIT(3), + FEATURE_VIDEOCHANNELS_MASK = GENMASK(2, 0), + FEATURE_VIDEOCHANNELS_0 = 0x0 << 0, + FEATURE_VIDEOCHANNELS_1 = 0x1 << 0, + FEATURE_VIDEOCHANNELS_1_1 = 0x2 << 0, + FEATURE_VIDEOCHANNELS_2 = 0x3 << 0, + }; + + enum { + EXT_FEATURE_OSD = BIT(15), + EXT_FEATURE_ETHERNET = BIT(9), + EXT_FEATURE_INTERLACE = BIT(8), + EXT_FEATURE_RS232 = BIT(7), + EXT_FEATURE_COMPRESSION_PERF_MASK = GENMASK(6, 4), + EXT_FEATURE_COMPRESSION_PERF_1X = 0x0 << 4, + EXT_FEATURE_COMPRESSION_PERF_2X = 0x1 << 4, + EXT_FEATURE_COMPRESSION_PERF_4X = 0x2 << 4, + EXT_FEATURE_COMPRESSION_TYPE1 = BIT(0), + EXT_FEATURE_COMPRESSION_TYPE2 = BIT(1), + EXT_FEATURE_COMPRESSION_TYPE3 = BIT(2), + }; + + u16 raw_features; + u16 raw_extended_features; + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); + + switch (raw_features & FEATURE_VIDEOCHANNELS_MASK) { + case FEATURE_VIDEOCHANNELS_0: + features->video_channels = 0; break;

- case UNITTYPE_VIDEO_SERVER: - case UNITTYPE_VIDEO_USER: - printf("Videochannel"); + case FEATURE_VIDEOCHANNELS_1: + features->video_channels = 1; break;

- default: - printf("UnitType %d(not supported)", unit_type); + case FEATURE_VIDEOCHANNELS_1_1: + case FEATURE_VIDEOCHANNELS_2: + features->video_channels = 2; break; - } + };

- switch (unit_type) { - case UNITTYPE_MAIN_SERVER: - case UNITTYPE_VIDEO_SERVER: - printf(" Server"); - if (versions & (1<<4)) - printf(" UC"); + switch (raw_features & FEATURE_CARRIERS_MASK) { + case FEATURE_CARRIERS_0: + features->carriers = 0; break;

- case UNITTYPE_MAIN_USER: - case UNITTYPE_VIDEO_USER: - printf(" User"); + case FEATURE_CARRIERS_1: + features->carriers = 1; break;

- default: + case FEATURE_CARRIERS_2: + features->carriers = 2; + break; + + case FEATURE_CARRIERS_4: + features->carriers = 4; break; }

- if (versions & (1<<5)) - printf(" Fiber"); - else - printf(" CAT"); + switch (raw_features & FEATURE_CARRIER_SPEED_MASK) { + case FEATURE_CARRIER_SPEED_1G: + features->carrier_speed = CARRIER_SPEED_1G; + break; + case FEATURE_CARRIER_SPEED_2_5G: + features->carrier_speed = CARRIER_SPEED_2_5G; + break; + case FEATURE_CARRIER_SPEED_10G: + features->carrier_speed = CARRIER_SPEED_10G; + break; + }

- switch (unit_type_pcb_video) { - case UNITTYPEPCB_DVI: - printf(" DVI,"); + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT_295MBPS: + features->ram_config = RAM_DDR2_32BIT_295MBPS; break;

- case UNITTYPEPCB_DP_165: - printf(" DP 165MPix/s,"); + case FEATURE_RAM_DDR3_32BIT_590MBPS: + features->ram_config = RAM_DDR3_32BIT_590MBPS; break;

- case UNITTYPEPCB_DP_300: - printf(" DP 300MPix/s,"); + case FEATURE_RAM_DDR3_48BIT_590MBPS: + features->ram_config = RAM_DDR3_48BIT_590MBPS; break;

- case UNITTYPEPCB_HDMI: - printf(" HDMI,"); + case FEATURE_RAM_DDR3_64BIT_1800MBPS: + features->ram_config = RAM_DDR3_64BIT_1800MBPS; + break; + + case FEATURE_RAM_DDR3_48BIT_1800MBPS: + features->ram_config = RAM_DDR3_48BIT_1800MBPS; break; }

- printf(" FPGA V %d.%02d\n features:", - fpga_version / 100, fpga_version % 100); + features->pcm_tx = raw_features & FEATURE_PCM_TX; + features->pcm_rx = raw_features & FEATURE_PCM_RX; + features->spdif_tx = raw_features & FEATURE_SPDIF_TX; + features->spdif_rx = raw_features & FEATURE_SPDIF_RX; + features->usb2 = raw_features & FEATURE_USB2; + features->rs232 = raw_extended_features & EXT_FEATURE_RS232; + features->compression_type1 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE1; + features->compression_type2 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE2; + features->compression_type3 = raw_extended_features & EXT_FEATURE_COMPRESSION_TYPE3; + features->interlace = raw_extended_features & EXT_FEATURE_INTERLACE; + features->osd = raw_extended_features & EXT_FEATURE_OSD; + features->compression_pipes = raw_extended_features & EXT_FEATURE_COMPRESSION_PERF_MASK; + + return 0; +} + +#else + +static int get_versions(unsigned int fpga, struct fpga_versions *versions) +{ + enum { + /* HW version encoding is a mess, leave it for the moment */ + VERSIONS_HW_VER_MASK = 0xf << 0, + VERSIONS_PIX_CLOCK_GEN_IDT8N3QV01 = BIT(4), + VERSIONS_SFP = BIT(5), + VERSIONS_VIDEO_MASK = 0x7 << 6, + VERSIONS_VIDEO_DVI = 0x0 << 6, + VERSIONS_VIDEO_DP_165 = 0x1 << 6, + VERSIONS_VIDEO_DP_300 = 0x2 << 6, + VERSIONS_VIDEO_HDMI = 0x3 << 6, + VERSIONS_UT_MASK = 0xf << 12, + VERSIONS_UT_MAIN_SERVER = 0x0 << 12, + VERSIONS_UT_MAIN_USER = 0x1 << 12, + VERSIONS_UT_VIDEO_SERVER = 0x2 << 12, + VERSIONS_UT_VIDEO_USER = 0x3 << 12, + }; + u16 raw_versions; + + memset(versions, 0, sizeof(struct fpga_versions)); + + FPGA_GET_REG(fpga, versions, &raw_versions); + + switch (raw_versions & VERSIONS_UT_MASK) { + case VERSIONS_UT_MAIN_SERVER: + versions->video_channel = false; + versions->con_side = false; + break; + + case VERSIONS_UT_MAIN_USER: + versions->video_channel = false; + versions->con_side = true; + break;

+ case VERSIONS_UT_VIDEO_SERVER: + versions->video_channel = true; + versions->con_side = false; + break;

- switch (feature_compression) { - case COMPRESSION_NONE: - printf(" no compression"); + case VERSIONS_UT_VIDEO_USER: + versions->video_channel = true; + versions->con_side = true; break;

- case COMPRESSION_TYPE_1: - printf(" compression type1(delta)"); + } + + switch (raw_versions & VERSIONS_VIDEO_MASK) { + case VERSIONS_VIDEO_DVI: + versions->pcb_video_type = PCB_DVI_SL; break;

- case COMPRESSION_TYPE_1_2: - printf(" compression type1(delta), type2(inline)"); + case VERSIONS_VIDEO_DP_165: + versions->pcb_video_type = PCB_DP_165MPIX; break;

- case COMPRESSION_TYPE_1_2_3: - printf(" compression type1(delta), type2(inline), type3(intempo)"); + case VERSIONS_VIDEO_DP_300: + versions->pcb_video_type = PCB_DP_300MPIX; break;

- default: - printf(" compression %d(not supported)", feature_compression); + case VERSIONS_VIDEO_HDMI: + versions->pcb_video_type = PCB_HDMI; break; }

- printf(", %sosd", feature_osd ? "" : "no "); + versions->hw_version = raw_versions & VERSIONS_HW_VER_MASK;

- switch (feature_audio) { - case AUDIO_NONE: - printf(", no audio"); + if (raw_versions & VERSIONS_SFP) + versions->pcb_transmission_type = PCB_FIBER_3G; + else + versions->pcb_transmission_type = PCB_CAT_1G; + + return 0; +} + +static int get_features(unsigned int fpga, struct fpga_features *features) +{ + enum { + FEATURE_CARRIER_SPEED_2_5 = BIT(4), + FEATURE_RAM_MASK = 0x7 << 5, + FEATURE_RAM_DDR2_32BIT = 0x0 << 5, + FEATURE_RAM_DDR3_32BIT = 0x1 << 5, + FEATURE_RAM_DDR3_48BIT = 0x2 << 5, + FEATURE_PCM_AUDIO_TX = BIT(9), + FEATURE_PCM_AUDIO_RX = BIT(10), + FEATURE_OSD = BIT(11), + FEATURE_USB20 = BIT(12), + FEATURE_COMPRESSION_MASK = 7 << 13, + FEATURE_COMPRESSION_TYPE1 = 0x1 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2 = 0x3 << 13, + FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3 = 0x7 << 13, + }; + + enum { + EXTENDED_FEATURE_SPDIF_AUDIO_TX = BIT(0), + EXTENDED_FEATURE_SPDIF_AUDIO_RX = BIT(1), + EXTENDED_FEATURE_RS232 = BIT(2), + EXTENDED_FEATURE_COMPRESSION_PIPES = BIT(3), + EXTENDED_FEATURE_INTERLACE = BIT(4), + }; + + u16 raw_features; +#ifdef GDSYS_LEGACY_DRIVERS + u16 raw_extended_features; +#endif + + memset(features, 0, sizeof(struct fpga_features)); + + FPGA_GET_REG(fpga, fpga_features, &raw_features); +#ifdef GDSYS_LEGACY_DRIVERS + FPGA_GET_REG(fpga, fpga_ext_features, &raw_extended_features); +#endif + + features->video_channels = raw_features & 0x3; + features->carriers = (raw_features >> 2) & 0x3; + + features->carrier_speed = (raw_features & FEATURE_CARRIER_SPEED_2_5) + ? CARRIER_SPEED_2_5G : CARRIER_SPEED_1G; + + switch (raw_features & FEATURE_RAM_MASK) { + case FEATURE_RAM_DDR2_32BIT: + features->ram_config = RAM_DDR2_32BIT_295MBPS; break;

- case AUDIO_TX: - printf(", audio tx"); + case FEATURE_RAM_DDR3_32BIT: + features->ram_config = RAM_DDR3_32BIT_590MBPS; break;

- case AUDIO_RX: - printf(", audio rx"); + case FEATURE_RAM_DDR3_48BIT: + features->ram_config = RAM_DDR3_48BIT_590MBPS; break; + }

- case AUDIO_RXTX: - printf(", audio rx+tx"); + features->pcm_tx = raw_features & FEATURE_PCM_AUDIO_TX; + features->pcm_rx = raw_features & FEATURE_PCM_AUDIO_RX; +#ifdef GDSYS_LEGACY_DRIVERS + features->spdif_tx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_TX; + features->spdif_rx = raw_extended_features & EXTENDED_FEATURE_SPDIF_AUDIO_RX; +#endif + + features->usb2 = raw_features & FEATURE_USB20; +#ifdef GDSYS_LEGACY_DRIVERS + features->rs232 = raw_extended_features & EXTENDED_FEATURE_RS232; +#endif + + features->compression_type1 = false; + features->compression_type2 = false; + features->compression_type3 = false; + switch (raw_features & FEATURE_COMPRESSION_MASK) { + case FEATURE_COMPRESSION_TYPE1_TYPE2_TYPE3: + features->compression_type3 = true; + case FEATURE_COMPRESSION_TYPE1_TYPE2: + features->compression_type2 = true; + case FEATURE_COMPRESSION_TYPE1: + features->compression_type1 = true; break; + } + +#ifdef GDSYS_LEGACY_DRIVERS + features->interlace = raw_extended_features & EXTENDED_FEATURE_INTERLACE; +#endif + features->osd = raw_features & FEATURE_OSD; +#ifdef GDSYS_LEGACY_DRIVERS + features->compression_pipes = raw_extended_features & EXTENDED_FEATURE_COMPRESSION_PIPES; +#endif

- default: - printf(", audio %d(not supported)", feature_audio); + return 0; +} + +#endif + +bool ioep_fpga_has_osd(unsigned int fpga) +{ + struct fpga_features features; + + get_features(fpga, &features); + + return features.osd; +} + +void ioep_fpga_print_info(unsigned int fpga) +{ + u16 fpga_version; + struct fpga_versions versions; + struct fpga_features features; + + FPGA_GET_REG(fpga, fpga_version, &fpga_version); + get_versions(fpga, &versions); + get_features(fpga, &features); + + if (versions.video_channel) + printf("Videochannel"); + else + printf("Mainchannel"); + + if (versions.con_side) + printf(" User"); + else + printf(" Server"); + +// FIXME +#if 0 + if (versions & (1<<4)) + printf(" UC"); +#endif + + switch(versions.pcb_transmission_type) { + case PCB_CAT_1G: + case PCB_CAT_10G: + printf(" CAT"); + break; + case PCB_FIBER_3G: + case PCB_FIBER_10G: + printf(" Fiber"); + break; + }; + + switch (versions.pcb_video_type) { + case PCB_DVI_SL: + printf(" DVI,"); + break; + case PCB_DP_165MPIX: + printf(" DP 165MPix/s,"); + break; + case PCB_DP_300MPIX: + printf(" DP 300MPix/s,"); + break; + case PCB_HDMI: + printf(" HDMI,"); + break; + case PCB_DP_1_2: + printf(" DP 1.2,"); + break; + case PCB_HDMI_2_0: + printf(" HDMI 2.0,"); break; }

+ printf(" FPGA V %d.%02d\n features: ", + fpga_version / 100, fpga_version % 100); + + if (!features.compression_type1 && + !features.compression_type2 && + !features.compression_type3) + printf("no compression, "); + + if (features.compression_type1) + printf("type1, "); + + if (features.compression_type2) + printf("type2, "); + + if (features.compression_type3) + printf("type3, "); + + printf("%sosd", features.osd ? "" : "no "); + + if (features.pcm_rx && features.pcm_tx) + printf(", pcm rx+tx"); + else if(features.pcm_rx) + printf(", pcm rx"); + else if(features.pcm_tx) + printf(", pcm tx"); + + if (features.spdif_rx && features.spdif_tx) + printf(", spdif rx+tx"); + else if(features.spdif_rx) + printf(", spdif rx"); + else if(features.spdif_tx) + printf(", spdif tx"); + puts(",\n ");

- switch (feature_sysclock) { + switch (features.sysclock) { case SYSCLK_147456: printf("clock 147.456 MHz"); break; - - default: - printf("clock %d(not supported)", feature_sysclock); - break; }

- switch (feature_ramconfig) { - case RAM_DDR2_32: + switch (features.ram_config) { + case RAM_DDR2_32BIT_295MBPS: printf(", RAM 32 bit DDR2"); break; - - case RAM_DDR3_32: + case RAM_DDR3_32BIT_590MBPS: printf(", RAM 32 bit DDR3"); break; - - case RAM_DDR3_48: + case RAM_DDR3_48BIT_590MBPS: + case RAM_DDR3_48BIT_1800MBPS: printf(", RAM 48 bit DDR3"); break; - - default: - printf(", RAM %d(not supported)", feature_ramconfig); + case RAM_DDR3_64BIT_1800MBPS: + printf(", RAM 64 bit DDR3"); break; }

- printf(", %d carrier(s) %s", feature_carriers, - feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s"); + printf(", %d carrier(s)", features.carriers); + + switch(features.carrier_speed) { + case CARRIER_SPEED_1G: + printf(", 1Gbit/s"); + break; + case CARRIER_SPEED_3G: + printf(", 3Gbit/s"); + break; + case CARRIER_SPEED_10G: + printf(", 10Gbit/s"); + break; + }

- printf(", %d video channel(s)\n", feature_video_channels); + printf(", %d video channel(s)\n", features.video_channels); }

#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 13/16] board: gazerbeam: Fix SC detection

The single channel detection in the gazerbeam board driver was not implemented correctly.

Fix the detection.

Signed-off-by: Mario Six mario.six@gdsys.cc --- drivers/board/gazerbeam.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/drivers/board/gazerbeam.c b/drivers/board/gazerbeam.c index 481cce8e809..85de4e440ce 100644 --- a/drivers/board/gazerbeam.c +++ b/drivers/board/gazerbeam.c @@ -61,7 +61,7 @@ static int _read_board_variant_data(struct udevice *dev) struct udevice *i2c_bus; struct udevice *dummy; char *listname; - int mc4, mc2, sc, con; + int mc4, mc2, sc, mc2_sc, con; int gpio_num; int res;

@@ -78,16 +78,16 @@ static int _read_board_variant_data(struct udevice *dev) return -EIO; }

- mc2 = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy); + mc2_sc = !dm_i2c_probe(i2c_bus, MC2_EXPANDER_ADDR, 0, &dummy); mc4 = !dm_i2c_probe(i2c_bus, MC4_EXPANDER_ADDR, 0, &dummy);

- if (mc2 && mc4) { + if (mc2_sc && mc4) { debug("%s: Board hardware configuration inconsistent.\n", dev->name); return -EINVAL; }

- listname = mc2 ? "var-gpios-mc2" : "var-gpios-mc4"; + listname = mc2_sc ? "var-gpios-mc2" : "var-gpios-mc4";

gpio_num = gpio_request_list_by_name(dev, listname, priv->var_gpios, ARRAY_SIZE(priv->var_gpios), @@ -105,12 +105,7 @@ static int _read_board_variant_data(struct udevice *dev) return sc; }

- con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); - if (con < 0) { - debug("%s: Error while reading 'con' GPIO (err = %d)", - dev->name, con); - return con; - } + mc2 = mc2_sc ? (sc ? 0 : 1) : 0;

if ((sc && mc2) || (sc && mc4) || (!sc && !mc2 && !mc4)) { debug("%s: Board hardware configuration inconsistent.\n", @@ -118,6 +113,13 @@ static int _read_board_variant_data(struct udevice *dev) return -EINVAL; }

+ con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); + if (con < 0) { + debug("%s: Error while reading 'con' GPIO (err = %d)", + dev->name, con); + return con; + } + priv->variant = con ? VAR_CON : VAR_CPU;

priv->multichannel = mc4 ? 4 : (mc2 ? 2 : (sc ? 1 : 0));

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 14/16] gazerbeam: Import Linux DT

Import the Linux device tree for the Gazerbeam board.

Signed-off-by: Mario Six mario.six@gdsys.cc --- arch/powerpc/dts/.gitignore | 1 + arch/powerpc/dts/Makefile | 1 + arch/powerpc/dts/gazerbeam.dts | 600 ++++++++++++++++++ arch/powerpc/dts/gdsys/gazerbeam-base.dtsi | 185 ++++++ arch/powerpc/dts/gdsys/mpc8308.dtsi | 354 +++++++++++ .../dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi | 6 + .../powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi | 6 + arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi | 5 + .../gdsys/soc/nor/flash-80k-partition.dtsi | 20 + 9 files changed, 1178 insertions(+) create mode 100644 arch/powerpc/dts/.gitignore create mode 100644 arch/powerpc/dts/gazerbeam.dts create mode 100644 arch/powerpc/dts/gdsys/gazerbeam-base.dtsi create mode 100644 arch/powerpc/dts/gdsys/mpc8308.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi create mode 100644 arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi

diff --git a/arch/powerpc/dts/.gitignore b/arch/powerpc/dts/.gitignore new file mode 100644 index 00000000000..b60ed208c77 --- /dev/null +++ b/arch/powerpc/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index f080a968919..6a28f802c24 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -2,6 +2,7 @@

dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb +dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb

targets += $(dtb-y)

diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts new file mode 100644 index 00000000000..a4408c496c8 --- /dev/null +++ b/arch/powerpc/dts/gazerbeam.dts @@ -0,0 +1,600 @@ +/* + * Gazerbeam CON Device Tree Source + * + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "gdsys/mpc8308.dtsi" + +/include/ "gdsys/gazerbeam-base.dtsi" + +/include/ "gdsys/soc/i2c/cirrus-audio-codec.dtsi" +/include/ "gdsys/soc/i2c/dallas-rtc.dtsi" +/include/ "gdsys/soc/lbc/gazerbeam.dtsi" +/include/ "gdsys/soc/nor/flash-80k-partition.dtsi" + +&board_lbc { + FPGA0:iocon_uart@1,0 { + reg = <0x1 0x0 0x100000>; + little-endian; + interrupts = <48 0x8>; + interrupt-parent = <&ipic>; + }; + + FPGA1:iocon_uart@2,0 { + reg = <0x2 0x0 0x100000>; + little-endian; + interrupts = <17 0x8>; + interrupt-parent = <&ipic>; + }; +}; + +&FPGA0 { + compatible = "gdsys,iocon_fpga"; + #gpio-cells = <2>; + gpio-controller; + bus = <&FPGA0BUS>; + unit_id = <0>; + fpga-type = <1>; + usb_base = <0x0080>; + audio_base = <0x0040>; + timebase_base = <0x013c>; + + /* + * for every interrupt source there must be a dataset specifying + * 1. type (1: standard) + * 2. status register offset + * 3. mask register offset + * 4. default mask + */ + fpga_interrupt_sources = + <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */ + <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */ + /* + * for every interrupt there must be a dataset specifying + * 1. type (1: status, 2: event) + * 2. interrupt source index + * 3. interrupt register bit + * 4. mask register bit + */ + #fpga_interrupt_map-cells = <4>; + fpga_interrupt_map = + <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */ + <1 0 0 0>, /* 1: VIDEO 0 */ + <1 0 1 1>, /* 2: VIDEO 1 */ + <1 0 2 2>, /* 3: VIDEO IC 0 */ + <1 0 3 3>, /* 4: VIDEO IC 1 */ + <1 0 4 4>, /* 5: IIC MAIN */ + <1 0 6 6>, /* 6: IIC VIDEO 0 */ + <1 0 7 7>, /* 7: IIC VIDEO 1 */ + <1 1 0 0>, /* 8: OSD 0 */ + <1 1 1 1>, /* 9: OSD 1 */ + <1 1 2 2>, /* 10: SPDIF 0 */ + <1 1 3 3>, /* 11: SPDIF 1 */ + <1 0 12 12>, /* 12: COMM 0 */ + <1 0 13 13>, /* 13: COMM 1 */ + <1 0 10 10>, /* 14: COMM 2 */ + <1 0 11 11>, /* 15: COMM 3 */ + <2 0 5 5>, /* 16: MDIO */ + <1 0 8 8>, /* 17: PHY */ + <1 1 4 4>, /* 18: RS232 */ + <1 1 5 5>, /* 19: AUDIO */ + <1 1 8 8>, /* 20: PROC_AUDIO */ + <1 1 7 7>, /* 21: USB/ETH-UART INT */ + <2 1 10 10>, /* 22: AXI Bridge 0 */ + <2 1 11 11>, /* 23: AXI Bridge 1 */ + <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */ + <>; +}; + +&FPGA1 { + compatible = "gdsys,iocon_fpga"; + #gpio-cells = <2>; + gpio-controller; + bus = <&FPGA1BUS>; + unit_id = <1>; + fpga-type = <1>; + usb_base = <0x0070>; + audio_base = <0x0040>; + timebase_base = <0x013c>; + + /* + * for every interrupt source there must be a dataset specifying + * 1. type (1: standard) + * 2. status register offset + * 3. mask register offset + * 4. default mask + */ + fpga_interrupt_sources = + <1 0x000a 0x000c 0x4000>, /* 0: TOP_INTERRUPT */ + <1 0x001c 0x001e 0x0000>; /* 1: EXTENDED_INTERRUPT */ + /* + * for every interrupt there must be a dataset specifying + * 1. type (1: status, 2: event) + * 2. interrupt source index + * 3. interrupt register bit + * 4. mask register bit + */ + #fpga_interrupt_map-cells = <4>; + fpga_interrupt_map = + <1 0 14 14>, /* 0: EXTENDED_INTERRUPT */ + <1 0 0 0>, /* 1: VIDEO 0 */ + <1 0 1 1>, /* 2: VIDEO 1 */ + <1 0 2 2>, /* 3: VIDEO IC 0 */ + <1 0 3 3>, /* 4: VIDEO IC 1 */ + <1 0 4 4>, /* 5: IIC MAIN */ + <1 0 6 6>, /* 6: IIC VIDEO 0 */ + <1 0 7 7>, /* 7: IIC VIDEO 1 */ + <1 1 0 0>, /* 8: OSD 0 */ + <1 1 1 1>, /* 9: OSD 1 */ + <1 1 2 2>, /* 10: SPDIF 0 */ + <1 1 3 3>, /* 11: SPDIF 1 */ + <1 0 12 12>, /* 12: COMM 0 */ + <1 0 13 13>, /* 13: COMM 1 */ + <1 0 10 10>, /* 14: COMM 2 */ + <1 0 11 11>, /* 15: COMM 3 */ + <2 0 5 5>, /* 16: MDIO */ + <1 0 8 8>, /* 17: PHY */ + <1 1 4 4>, /* 18: RS232 */ + <1 1 5 5>, /* 19: AUDIO */ + <1 1 8 8>, /* 20: PROC_AUDIO */ + <1 1 7 7>, /* 21: USB/ETH-UART INT */ + <2 1 10 10>, /* 22: AXI Bridge 0 */ + <2 1 11 11>, /* 23: AXI Bridge 1 */ + <2 1 9 9>, /* 24: USB/ETH-Secondary IIC */ + <>; +}; + +/ { + FPGA0BUS: fpga0bus { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x00002000>; + + compatible = "gdsys,soc"; + + fpga0_rs232 { + compatible = "gdsys,ihs_trans_rs232"; + reg = <0x50 0x08>; + little-endian; + }; + + fpga0_uart_usb { + compatible = "gdsys,ihs_simple_uart"; + reg = <0xa0 0x08>; + little-endian; + fpga_interrupts = <21>; + line = <0>; + }; + + fpga0_iic_main { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x60 0x10>; + little-endian; + fpga_interrupts = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_dp_video0_redriver: fpga0_dp_video0_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2c>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + fpga0_dp_video1_redriver: fpga0_dp_video1_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2e>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + ads1015@4b { + compatible = "ti,ads1015"; + reg = <0x4b>; + }; + }; + + fpga0_video0 { + compatible = "gdsys,ihs_video_out"; + reg = <0x100 0x40>; + little-endian; + fpga_interrupts = <1 8>; /* VIDEO OSD */ + osd_base = <0x180>; + osd_buffer_base = <0x1000>; + spdif_audio_base = <0x1e0>; + video_index = <0>; + video_id = <0>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga0_dp_video0>; + clk_gen = <&fpga0_video0_clkgen>; + ddc_ci = <&fpga0_dp_video0>; + }; + + fpga0_iic_video0 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x1c0 0x10>; + little-endian; + fpga_interrupts = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_video0_clkgen: fpga0_video0_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <0>; + }; + }; + + fpga0_axi_video0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x170 0x10>; + little-endian; + fpga_interrupts = <22>; + + fpga0_dp_video0: fpga0_dp_video0 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga0_dp_video0_redriver>; + video_id = <0>; + }; + }; + + fpga0_video1 { + compatible = "gdsys,ihs_video_out"; + reg = <0x200 0x40>; + little-endian; + fpga_interrupts = <2 9>; /* VIDEO OSD */ + osd_base = <0x280>; + osd_buffer_base = <0x2000>; + spdif_audio_base = <0x2e0>; + video_index = <1>; + video_id = <1>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga0_dp_video1>; + clk_gen = <&fpga0_video1_clkgen>; + ddc_ci = <&fpga0_dp_video1>; + }; + + fpga0_iic_video1 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x2c0 0x10>; + little-endian; + fpga_interrupts = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_video1_clkgen: fpga0_video1_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <1>; + }; + }; + + fpga0_axi_video1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x270 0x10>; + little-endian; + fpga_interrupts = <23>; + + fpga0_dp_video1: fpga0_dp_video1 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga0_dp_video1_redriver>; + video_id = <1>; + }; + }; + + fpga0_iic_usb { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0xb0 0x10>; + little-endian; + fpga_interrupts = <24>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + fpga0_ep0 { + compatible = "gdsys,io-endpoint"; + reg = < 0x020 0x10 + 0x320 0x10 + 0x340 0x10 + 0x360 0x10>; + little-endian; + irq-model-local; + fpga_interrupts = <12 13 14 15>; + pollcycle = <200>; + nprot_channel = <16>; + uart_line = <0>; + ep_index = <0>; + line_protocol = <1>; + }; + + fpga0_mdio { + compatible = "gdsys,ihs_mdiomaster"; + reg = <0x0058 0x10>; + little-endian; + fpga_interrupts = <16>; + #address-cells = <1>; + #size-cells = <0>; + + fpga0_phy0 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <0>; + }; + fpga0_phy1 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <1>; + }; + fpga0_phy2 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <2>; + }; + fpga0_phy3 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <3>; + }; + }; + + }; + + + FPGA1BUS: fpga1bus { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x00002000>; + + compatible = "gdsys,soc"; + + fpga1_uart_usb { + compatible = "gdsys,ihs_simple_uart"; + reg = <0xa0 0x08>; + little-endian; + fpga_interrupts = <21>; + line = <4>; /* TODO check and FIX */ + }; + + fpga1_iic_main { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x60 0x10>; + little-endian; + fpga_interrupts = <5>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_dp_video0_redriver: fpga1_dp_video0_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2c>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + fpga1_dp_video1_redriver: fpga1_dp_video1_redriver { + compatible = "ti,sn75dp130"; + reg = <0x2e>; + eq-i2c-enable = <3 2 1 0 + 3 2 1 0 + 3 2 1 0 + 3 2 1 0>; /* 3.5 dB for all pe values for all lanes */ + }; + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + ads1015@4b { + compatible = "ti,ads1015"; + reg = <0x4b>; + }; + }; + + fpga1_video0 { + compatible = "gdsys,ihs_video_out"; + reg = <0x100 0x40>; + little-endian; + fpga_interrupts = <1 8>; /* VIDEO OSD */ + osd_base = <0x180>; + osd_buffer_base = <0x1000>; + spdif_audio_base = <0x1e0>; + video_index = <0>; + video_id = <4>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga1_dp_video0>; + clk_gen = <&fpga1_video0_clkgen>; + ddc_ci = <&fpga1_dp_video0>; + }; + + fpga1_iic_video0 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x1c0 0x10>; + little-endian; + fpga_interrupts = <6>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_video0_clkgen: fpga1_video0_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <4>; + }; + }; + + fpga1_axi_video0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x170 0x10>; + little-endian; + fpga_interrupts = <22>; + + fpga1_dp_video0: fpga1_dp_video0 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga1_dp_video0_redriver>; + video_id = <4>; + }; + }; + + fpga1_video1 { + compatible = "gdsys,ihs_video_out"; + reg = <0x200 0x40>; + little-endian; + fpga_interrupts = <2 9>; /* VIDEO OSD */ + osd_base = <0x280>; + osd_buffer_base = <0x2000>; + spdif_audio_base = <0x2e0>; + video_index = <1>; + video_id = <5>; + fpga-force-pos-pol; + sync-source; + fpga-pb-pixels = <2730>; /* 8192 / 3 */ + fpga-ra-lines = <2>; + video_tx = <&fpga1_dp_video1>; + clk_gen = <&fpga1_video1_clkgen>; + ddc_ci = <&fpga1_dp_video1>; + }; + + fpga1_iic_video1 { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0x2c0 0x10>; + little-endian; + fpga_interrupts = <7>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_video1_clkgen: fpga1_video1_clkgen { + compatible = "idt,ics8n3qv01"; + reg = <0x6e>; + channel = <5>; + }; + }; + + fpga1_axi_video1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "gdsys,ihs_axi"; + reg = <0x270 0x10>; + little-endian; + fpga_interrupts = <23>; + + fpga1_dp_video1: fpga1_dp_video1 { + compatible = "gdsys,logicore_dp_tx"; + reg = <0x44a10000 0x1000>; + little-endian; + redriver = <&fpga1_dp_video1_redriver>; + video_id = <5>; + }; + }; + + fpga1_iic_usb { + compatible = "gdsys,ihs_i2cmaster"; + reg = <0xb0 0x10>; + little-endian; + fpga_interrupts = <24>; + #address-cells = <1>; + #size-cells = <0>; + + pca9555@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + + fpga1_ep0 { + compatible = "gdsys,io-endpoint"; + reg = < 0x020 0x10 + 0x320 0x10 + 0x340 0x10 + 0x360 0x10>; + little-endian; + irq-model-local; + fpga_interrupts = <12 13 14 15>; + pollcycle = <200>; + nprot_channel = <17>; + uart_line = <1>; + ep_index = <0>; + line_protocol = <1>; + }; + + fpga1_mdio { + compatible = "gdsys,ihs_mdiomaster"; + reg = <0x0058 0x10>; + little-endian; + fpga_interrupts = <16>; + #address-cells = <1>; + #size-cells = <0>; + + fpga1_phy0 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <0>; + }; + fpga1_phy1 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <1>; + }; + fpga1_phy2 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <2>; + }; + fpga1_phy3 { + compatible = "ethernet-phy-ieee802.3-c45"; + device_type ="ethernet-phy"; + reg = <3>; + }; + }; + + }; + +}; diff --git a/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi new file mode 100644 index 00000000000..aca05f2cd08 --- /dev/null +++ b/arch/powerpc/dts/gdsys/gazerbeam-base.dtsi @@ -0,0 +1,185 @@ +/* + * Gazerbeam Device Tree Source + * + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/ { + model = "gdsys,gazerbeam"; + compatible = "fsl,mpc8308rdb"; + + aliases { + ethernet0 = &enet0; + ethernet1 = &enet1; + }; + + memory { + device_type = "memory"; + }; +}; + +&enet1 { + status = "okay"; +}; + +&IIC { + fsl,preserve-clocking; + + at97sc3205t@29 { + compatible = "atmel,at97sc3204t"; + reg = <0x29>; + }; + + lm77@48 { + compatible = "national,lm77"; + reg = <0x48>; + }; + + ads1015@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + }; + + lm77@4a { + compatible = "national,lm77"; + reg = <0x4a>; + }; + + emc2305@2e { + compatible = "smsc,emc2305"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2e>; + fan@0 { + reg = <0>; + }; + fan@1 { + reg = <1>; + }; + fan@2 { + reg = <2>; + }; + fan@3 { + reg = <3>; + }; + fan@4 { + reg = <4>; + }; + }; + + emc2305@4c { + compatible = "smsc,emc2305"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4c>; + fan@0 { + reg = <0>; + }; + fan@1 { + reg = <1>; + }; + fan@2 { + reg = <2>; + }; + fan@3 { + reg = <3>; + }; + fan@4 { + reg = <4>; + }; + }; + + at24c512@54 { + compatible = "atmel,24c512"; + reg = <0x54>; + }; + + /* PPC-Board */ + pca9698@22 { + compatible = "nxp,pca9698"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* IO-Board */ + pca9698@20 { + compatible = "nxp,pca9698"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&IIC2 { + fsl,preserve-clocking; + + status = "okay"; + + /* MC2/SC-Board */ + GPIO_VB0: pca9698@20 { + compatible = "nxp,pca9698"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* MC4-Board */ + GPIO_VB1: pca9698@22 { + compatible = "nxp,pca9698"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&SPI { + gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0 + /*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0 + /*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0 + /*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0 + /*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0 + /*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>; + + m25p16@0 { + compatible = "st,n25q128a11"; + reg = <0x0>; + spi-max-frequency = <20000000>; + }; + + m25p16@1 { + compatible = "st,n25q128a11"; + reg = <0x1>; + spi-max-frequency = <20000000>; + }; + + m25p16@2 { + compatible = "st,m25p40"; + reg = <0x2>; + spi-max-frequency = <20000000>; + }; + + m25p16@3 { + compatible = "st,m25p40"; + reg = <0x3>; + spi-max-frequency = <20000000>; + }; + + m25p16@4 { + compatible = "st,m25p40"; + reg = <0x4>; + spi-max-frequency = <20000000>; + }; + + m25p16@5 { + compatible = "st,m25p40"; + reg = <0x5>; + spi-max-frequency = <20000000>; + }; +}; diff --git a/arch/powerpc/dts/gdsys/mpc8308.dtsi b/arch/powerpc/dts/gdsys/mpc8308.dtsi new file mode 100644 index 00000000000..23e7403d911 --- /dev/null +++ b/arch/powerpc/dts/gdsys/mpc8308.dtsi @@ -0,0 +1,354 @@ +/* + * Basic platform for gdsys mpc8308 based devices + * + * (C) Copyright 2014 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * based on mpc8308rdb + * Copyright 2009 Freescale Semiconductor Inc. + * Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/dts-v1/; + +#include <dt-bindings/memory/mpc83xx-sdram.h> + +/ { + compatible = "fsl,mpc8308rdb"; + + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + }; + + memory { + device_type = "memory"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8308@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; + i-cache-line-size = <32>; + d-cache-size = <16384>; + i-cache-size = <16384>; + timebase-frequency = <0>; // from bootloader + bus-frequency = <0>; // from bootloader + clock-frequency = <0>; // from bootloader + }; + }; + + board_lbc: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus"; + reg = <0xe0005000 0x1000>; + interrupts = <77 0x8>; + interrupt-parent = <&ipic>; + }; + + board_soc: immr@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8308-immr", "simple-bus"; + ranges = <0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>; + + wdt@200 { + device_type = "watchdog"; + compatible = "mpc83xx_wdt"; + reg = <0x200 0x100>; + }; + + memory@2000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc83xx-mem-controller"; + reg = <0x2000 0x1000>; + device_type = "memory"; + + driver_software_override = <DSO_ENABLE>; + p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>; + n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>; + odt_termination_value = <ODT_TERMINATION_150_OHM>; + ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>; + + clock_adjust = <CLOCK_ADJUST_05>; + + read_to_write = <0>; + write_to_read = <0>; + read_to_read = <0>; + write_to_write = <0>; + active_powerdown_exit = <2>; + precharge_powerdown_exit = <6>; + odt_powerdown_exit = <8>; + mode_reg_set_cycle = <2>; + + precharge_to_activate = <2>; + activate_to_precharge = <6>; + activate_to_readwrite = <2>; + mcas_latency = <CASLAT_40>; + refresh_recovery = <17>; + last_data_to_precharge = <2>; + activate_to_activate = <2>; + last_write_data_to_read = <2>; + + additive_latency = <0>; + mcas_to_preamble_override = <READ_LAT_PLUS_1_2>; + write_latency = <3>; + read_to_precharge = <2>; + write_cmd_to_write_data = <CLOCK_DELAY_1_2>; + minimum_cke_pulse_width = <3>; + four_activates_window = <5>; + + self_refresh = <SREN_ENABLE>; + sdram_type = <TYPE_DDR2>; + databus_width = <DATA_BUS_WIDTH_32>; + + force_self_refresh = <MODE_NORMAL>; + dll_reset = <DLL_RESET_ENABLE>; + dqs_config = <DQS_TRUE>; + odt_config = <ODT_ASSERT_READS>; + posted_refreshes = <1>; + + refresh_interval = <2084>; + precharge_interval = <256>; + + sdmode = <0x0242>; + esdmode = <0x0440>; + + ram@0 { + reg = <0x0 0x0 0x8000000>; + compatible = "nanya,nt5tu64m16hg"; + + odt_rd_cfg = <ODT_RD_NEVER>; + odt_wr_cfg = <ODT_WR_ONLY_CURRENT>; + bank_bits = <3>; + row_bits = <13>; + col_bits = <10>; + }; + }; + + IIC:i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + }; + + IIC2: i2c@3100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl-i2c"; + reg = <0x3100 0x100>; + interrupts = <15 0x8>; + interrupt-parent = <&ipic>; + dfsrr; + status = "disabled"; + }; + + SPI:spi@7000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + }; + + sdhc@2e000 { + compatible = "fsl,esdhc", "fsl,mpc8308-esdhc"; + reg = <0x2e000 0x1000>; + interrupts = <42 0x8>; + interrupt-parent = <&ipic>; + sdhci,auto-cmd12; + /* Filled in by U-Boot */ + clock-frequency = <0>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <133333333>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <133333333>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + }; + + gpio0: gpio@c00 { + #gpio-cells = <2>; + device_type = "gpio"; + compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio"; + reg = <0xc00 0x18>; + interrupts = <74 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + }; + + /* IPIC + * interrupts cell = <intr #, sense> + * sense values match linux IORESOURCE_IRQ_* defines: + * sense == 8: Level, low assertion + * sense == 2: Edge, high-to-low change + */ + ipic: interrupt-controller@700 { + compatible = "fsl,ipic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + ipic-msi@7c0 { + compatible = "fsl,ipic-msi"; + reg = <0x7c0 0x40>; + msi-available-ranges = <0x0 0x100>; + interrupts = < 0x43 0x8 + 0x4 0x8 + 0x51 0x8 + 0x52 0x8 + 0x56 0x8 + 0x57 0x8 + 0x58 0x8 + 0x59 0x8 >; + interrupt-parent = < &ipic >; + }; + + dma@2c000 { + compatible = "fsl,mpc8308-dma", "fsl,mpc5121-dma"; + reg = <0x2c000 0x1800>; + interrupts = <3 0x8 + 94 0x8>; + interrupt-parent = < &ipic >; + }; + + enet0: ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x24000 0x1000>; + + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar", "fsl,tsec"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 0x8 33 0x8 34 0x8>; + interrupt-parent = <&ipic>; + tbi-handle = < &tbi0 >; + phy-handle = < &phy1 >; + fsl,magic-packet; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + phy1: ethernet-phy@1 { + reg = <0x1>; + }; + phy2: ethernet-phy@0 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + + enet1: ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar", "fsl,tsec"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 0x8 36 0x8 37 0x8>; + interrupt-parent = <&ipic>; + phy-handle = < &phy2 >; + status = "disabled"; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x520 0x20>; + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + }; + }; + + pci0: pcie@e0009000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000 + 0xb0000000 0x01000000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + bus-range = <0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 8 + 0 0 0 2 &ipic 1 8 + 0 0 0 3 &ipic 1 8 + 0 0 0 4 &ipic 1 8>; + interrupts = <0x1 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <0>; + + pcie@0 { + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + reg = <0 0 0 0 0>; + ranges = <0x02000000 0 0xa0000000 + 0x02000000 0 0xa0000000 + 0 0x10000000 + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00800000>; + }; + }; +}; diff --git a/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi b/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi new file mode 100644 index 00000000000..9787e096483 --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/i2c/cirrus-audio-codec.dtsi @@ -0,0 +1,6 @@ +&IIC { + cs4265@4f { + compatible = "cirrus,cs4265"; + reg = <0x0000004f>; + }; +}; diff --git a/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi b/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi new file mode 100644 index 00000000000..336bdcaf2e3 --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/i2c/dallas-rtc.dtsi @@ -0,0 +1,6 @@ +&IIC { + ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; diff --git a/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi b/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi new file mode 100644 index 00000000000..5ff58c28e50 --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/lbc/gazerbeam.dtsi @@ -0,0 +1,5 @@ +&board_lbc { + ranges = <0x0 0x0 0xfe000000 0x00800000 + 0x1 0x0 0xe0600000 0x00003000 + 0x2 0x0 0xe0700000 0x00003000>; +}; diff --git a/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi b/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi new file mode 100644 index 00000000000..c6cc1409e0d --- /dev/null +++ b/arch/powerpc/dts/gdsys/soc/nor/flash-80k-partition.dtsi @@ -0,0 +1,20 @@ +&board_lbc { + flash@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x100000>; + bank-width = <2>; + device-width = <1>; + + u-boot@0 { + reg = <0x0 0x80000>; + }; + env@80000 { + reg = <0x80000 0x10000>; + }; + env1@90000 { + reg = <0x90000 0x10000>; + }; + }; +};

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 15/16] gazerbeam: Add u-boot specific dts include file

Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree.

Signed-off-by: Mario Six mario.six@gdsys.cc --- arch/powerpc/dts/gazerbeam.dts | 2 + arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi | 250 ++++++++++++++++++++ 2 files changed, 252 insertions(+) create mode 100644 arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi

diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts index a4408c496c8..5d171519e01 100644 --- a/arch/powerpc/dts/gazerbeam.dts +++ b/arch/powerpc/dts/gazerbeam.dts @@ -598,3 +598,5 @@ };

}; + +#include "gdsys/gazerbeam-uboot.dtsi" diff --git a/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi new file mode 100644 index 00000000000..1c4977f20f3 --- /dev/null +++ b/arch/powerpc/dts/gdsys/gazerbeam-uboot.dtsi @@ -0,0 +1,250 @@ +#include <dt-bindings/memory/mpc83xx-sdram.h> +#include <dt-bindings/clk/mpc83xx-clk.h> + +/ { + aliases { + i2c0 = &IIC; + i2c1 = &IIC2; + i2c2 = "/fpga0bus/fpga0_iic_main"; + i2c3 = "/fpga0bus/fpga0_iic_video0"; + i2c4 = "/fpga0bus/fpga0_iic_video1"; + i2c5 = "/fpga0bus/fpga0_iic_usb"; + gdsys_soc0 = "/fpga0bus"; + gdsys_soc1 = "/fpga1bus"; + ioep0 = "/fpga0bus/fpga0_ep0"; + ioep1 = "/fpga0bus/fpga1_ep0"; + }; + + chosen { + stdout-path = &serial1; + }; + + cpus { + compatible = "cpu_bus"; + u-boot,dm-pre-reloc; + + PowerPC,8308@0 { + compatible = "fsl,mpc8308"; + clocks = <&socclocks MPC83XX_CLK_CORE + &socclocks MPC83XX_CLK_CSB>; + u-boot,dm-pre-reloc; + }; + }; + + board { + compatible = "gdsys,board_gazerbeam"; + csb = <&board_soc>; + serdes = <&SERDES>; + rxaui0 = <&RXAUI0_0>; + rxaui1 = <&RXAUI0_1>; + rxaui2 = <&RXAUI0_2>; + rxaui3 = <&RXAUI0_3>; + rxaui4 = <&RXAUI1_0>; + rxaui5 = <&RXAUI1_1>; + rxaui6 = <&RXAUI1_2>; + rxaui7 = <&RXAUI1_3>; + fpga0 = <&FPGA0>; + fpga1 = <&FPGA1>; + ioep0 = <&IOEP0>; + ioep1 = <&IOEP1>; + + ver-gpios = <&PPCPCA 12 0 + &PPCPCA 13 0 + &PPCPCA 14 0 + &PPCPCA 15 0>; + + /* MC2/SC-Board */ + var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */ + &GPIO_VB0 11 0>; /* VAR-CON */ + /* MC4-Board */ + var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */ + &GPIO_VB1 11 0>; /* VAR-CON */ + + reset-gpios = <&gpio0 1 0 &gpio0 2 1>; + }; + + socclocks: clocks { + compatible = "fsl,mpc8308-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + + timer { + compatible = "fsl,mpc83xx-timer"; + clocks = <&socclocks MPC83XX_CLK_CSB>; + }; +}; + +&FPGA0 { + reset-gpios = <&PPCPCA 26 0>; + done-gpios = <&GPIO_VB0 19 0>; +}; + +&FPGA1 { + status = "disable"; +}; + +&FPGA0BUS { + ranges = <0x0 0xe0600000 0x00004000>; + fpga = <&FPGA0>; + + fpga0_video0 { + mode = "640_480_60"; + + status = "disabled"; + }; + + RXAUI0_0: fpga0_rxaui@fc0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fc0 0x10>; + }; + + fpga0_iic_video0 { + status = "disabled"; + }; + + fpga0_axi_video0 { + status = "disabled"; + }; + + fpga0_video1 { + mode = "640_480_60"; + status = "disabled"; + }; + + fpga0_iic_video1 { + status = "disabled"; + }; + + fpga0_axi_video1 { + status = "disabled"; + }; + + IOEP0: fpga0_ep0 { + }; + + RXAUI0_1: fpga0_rxaui@fd0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fd0 0x10>; + }; + + RXAUI0_2: fpga0_rxaui@fe0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fe0 0x10>; + }; + + RXAUI0_3: fpga0_rxaui@ff0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0ff0 0x10>; + }; +}; + +&FPGA1BUS { + ranges = <0x0 0xe0700000 0x00004000>; + fpga = <&FPGA1>; + + status = "disable"; + + fpga1_video0 { + mode = "640_480_60"; + }; + + RXAUI1_0: fpga0_rxaui@fc0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fc0 0x10>; + }; + + fpga1_video1 { + mode = "640_480_60"; + }; + + IOEP1: fpga1_ep0 { + }; + + RXAUI1_1: fpga0_rxaui@fd0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fd0 0x10>; + }; + + RXAUI1_2: fpga0_rxaui@fe0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0fe0 0x10>; + }; + + RXAUI1_3: fpga0_rxaui@ff0 { + compatible = "gdsys,rxaui_ctrl"; + reg = <0x0ff0 0x10>; + }; +}; + +&board_soc { + u-boot,dm-pre-reloc; + clocks = <&socclocks MPC83XX_CLK_CSB>; + + memory@2000 { + u-boot,dm-pre-reloc; + }; + + sdhc@2e000 { + clocks = <&socclocks MPC83XX_CLK_SDHC>; + clock-names = "per"; + }; + + SERDES: serdes@e3000 { + reg = <0xe3000 0x200>; + compatible = "fsl,mpc83xx-serdes"; + proto = "pex"; + serdes-clk = <100>; + vdd; + }; +}; + +&IIC { + clocks = <&socclocks MPC83XX_CLK_I2C1>; + + PPCPCA: pca9698@20 { + label = "ppc"; + }; + + IOPCA: pca9698@22 { + label = "io"; + }; + + at97sc3205t@29 { + u-boot,i2c-offset-len = <0>; + }; +}; + +&IIC2 { + clocks = <&socclocks MPC83XX_CLK_I2C2>; + + GPIO_VB0: pca9698@20 { + label = "mc2-sc"; + }; + + GPIO_VB1: pca9698@22 { + label = "mc4"; + }; +}; + +&board_soc { + u-boot,dm-pre-reloc; +}; + +&GPIO_VB0 { + u-boot,dm-pre-reloc; +}; + +&serial0 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + u-boot,dm-pre-reloc; +}; + +&serial1 { + clocks = <&socclocks MPC83XX_CLK_CSB>; + u-boot,dm-pre-reloc; +}; + +&pci0 { + clocks = <&socclocks MPC83XX_CLK_PCIEXP1>; +};

-- 2.20.1

Mario Six

10:18 a.m.

New subject: [U-Boot] [PATCH 16/16] mpc83xx: Add gazerbeam board

From: Dirk Eibach dirk.eibach@gdsys.cc

The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card.

On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional)

Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc Signed-off-by: Mario Six mario.six@gdsys.cc --- arch/powerpc/cpu/mpc83xx/Kconfig | 19 +++ arch/powerpc/dts/gazerbeam.dts | 2 +- board/gdsys/common/Makefile | 1 + board/gdsys/mpc8308/Kconfig | 29 ++++- board/gdsys/mpc8308/MAINTAINERS | 2 + board/gdsys/mpc8308/Makefile | 1 + board/gdsys/mpc8308/gazerbeam.c | 179 ++++++++++++++++++++++++++++ configs/gazerbeam_defconfig | 196 +++++++++++++++++++++++++++++++ include/configs/gazerbeam.h | 137 +++++++++++++++++++++ 9 files changed, 564 insertions(+), 2 deletions(-) create mode 100644 board/gdsys/mpc8308/gazerbeam.c create mode 100644 configs/gazerbeam_defconfig create mode 100644 include/configs/gazerbeam.h

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index fe20e85086b..b99288aa836 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -175,6 +175,25 @@ config TARGET_STRIDER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_PCA953X

+config TARGET_GAZERBEAM + bool "Support gazerbeam" + select ARCH_MPC8308 + select SYS_FSL_ERRATUM_ESDHC111 + imply ENV_IS_IN_FLASH + help + The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH + Systementwicklung based on the NXP MPC8308 SoC for usage in KVM + appliances. + + Features include: + * Two gigabit ethernet ports + * Multiple USB ports (depending on variant) + * Several gigabit ethernet or optical fiber ports (depending on + variant) + * Several display port inputs and outputs, and supporting redrivers + (depending on variant) + * Several FPGAs with custom logic (depending on variant) + endchoice

config MPC83XX_QUICC_ENGINE diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts index 5d171519e01..96c03c77ae8 100644 --- a/arch/powerpc/dts/gazerbeam.dts +++ b/arch/powerpc/dts/gazerbeam.dts @@ -10,7 +10,7 @@ * option) any later version. */

-/include/ "gdsys/mpc8308.dtsi" +#include "gdsys/mpc8308.dtsi"

/include/ "gdsys/gazerbeam-base.dtsi"

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index ff8d6f49665..7dfe104561a 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7 obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o +obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o

ifdef CONFIG_OSD obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index e6a47960547..30811889fbf 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -71,7 +71,28 @@ config GDSYS_LEGACY_DRIVERS

endif

-if TARGET_HRCON || TARGET_STRIDER +if TARGET_GAZERBEAM + +config SYS_BOARD + default "mpc8308" + +config SYS_VENDOR + default "gdsys" + +config SYS_CONFIG_NAME + default "gazerbeam" + +config SYS_FPGA1_BASE + default E0700000 + +config SYS_FPGA1_SIZE + default 1 + +config GDSYS_LEGACY_OSD_CMDS + default y +endif + +if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM

choice prompt "FPGA flavor selection" @@ -89,6 +110,12 @@ config SYS_FPGA_FLAVOR_GAZERBEAM

endchoice

+config EXTENDED_FEATURES + bool "FPGA extended features" + depends on GDSYS_LEGACY_DRIVERS + help + Enable support for the extended features field of the IHS FPGA. + config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index 755b9a23858..ed1b6fa1062 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -6,7 +6,9 @@ F: include/configs/hrcon.h F: configs/hrcon_defconfig F: configs/hrcon_dh_defconfig F: include/configs/strider.h +F: configs/strider_defconfig F: configs/strider_cpu_defconfig F: configs/strider_cpu_dp_defconfig F: configs/strider_con_defconfig F: configs/strider_con_dp_defconfig +F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index dc579479f95..9af5fe04d18 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -6,3 +6,4 @@ obj-y := mpc8308.o sdram.o obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_TARGET_STRIDER) += strider.o +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c new file mode 100644 index 00000000000..cd621744d28 --- /dev/null +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <board.h> +#include <dm.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <misc.h> +#include <tpm-v1.h> +#include <video_osd.h> + +#include "../common/ihs_mdio.h" +#include "../../../drivers/board/gazerbeam.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct ihs_mdio_info ihs_mdio_info[] = { + { .fpga = NULL, .name = "ihs0", .base = 0x58 }, + { .fpga = NULL, .name = "ihs1", .base = 0x58 }, +}; + +static int get_tpm(struct udevice **devp) +{ + int rc; + + rc = uclass_first_device_err(UCLASS_TPM, devp); + if (rc) { + printf("Could not find TPM (ret=%d)\n", rc); + return CMD_RET_FAILURE; + } + + return 0; +} + +int board_early_init_r(void) +{ + struct udevice *board; + struct udevice *serdes; + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + /* Initialize serdes */ + uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes); + + if (board_detect(board)) + puts("Device information detection failed.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + if (mc == 2 || mc == 1) + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22"); + + if (mc == 4) { + dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20"); + dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0"); + dev_enable_by_path("/fpga1bus"); + } + + if (mc == 2 || con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video1"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video1"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video1"); + } + + if (con == VAR_CON) { + dev_enable_by_path("/fpga0bus/fpga0_video0"); + dev_enable_by_path("/fpga0bus/fpga0_iic_video0"); + dev_enable_by_path("/fpga0bus/fpga0_axi_video0"); + } + + return 0; +} + +int checkboard(void) +{ + struct udevice *board; + char *s = env_get("serial#"); + int mc = 0; + int con = 0; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + board_get_int(board, BOARD_MULTICHANNEL, &mc); + board_get_int(board, BOARD_VARIANT, &con); + + puts("Board: Gazerbeam "); + printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC"); + printf("%s", con == VAR_CON ? "CON" : "CPU"); + + if (s) { + puts(", serial# "); + puts(s); + } + + puts("\n"); + + return 0; +} + +static void display_osd_info(struct udevice *osd, + struct video_osd_info *osd_info) +{ + printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n", + osd->name, osd_info->major_version, osd_info->minor_version, + osd_info->width, osd_info->height); +} + +int last_stage_init(void) +{ + int fpga_hw_rev = 0; + int i; + struct udevice *board; + struct udevice *osd; + struct video_osd_info osd_info; + struct udevice *tpm; + int ret; + + if (board_get(&board)) + puts("Could not find board information device.\n"); + + if (board) { + int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev); + + if (res) + printf("Could not determind FPGA HW revision (res = %d)\n", res); + } + + env_set_ulong("fpga_hw_rev", fpga_hw_rev); + + ret = get_tpm(&tpm); + if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) || + tpm_continue_self_test(tpm)) { + printf("TPM init failed\n"); + } + + if (fpga_hw_rev >= 4) { + for (i = 0; i < 4; i++) { + struct udevice *rxaui; + char name[8]; + + snprintf(name, sizeof(name), "rxaui%d", i); + /* Disable RXAUI polarity inversion */ + ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui); + if (!ret) + misc_set_enabled(rxaui, false); + } + } + + for (uclass_first_device(UCLASS_VIDEO_OSD, &osd); + osd; + uclass_next_device(&osd)) { + video_osd_get_info(osd, &osd_info); + display_osd_info(osd, &osd_info); + } + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fsl_fdt_fixup_dr_usb(blob, bd); + fdt_fixup_esdhc(blob, bd); + + return 0; +} +#endif diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig new file mode 100644 index 00000000000..346b1b2eaa8 --- /dev/null +++ b/configs/gazerbeam_defconfig @@ -0,0 +1,196 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_IDENT_STRING=" gazerbeam 0.01" +CONFIG_SYS_CLK_FREQ=33333333 +CONFIG_MPC83xx=y +CONFIG_TARGET_GAZERBEAM=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="INIT_RAM" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xE0700000 +CONFIG_LBLAW2_NAME="FPGA1" +CONFIG_LBLAW2_LENGTH_1_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA0" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="FPGA1" +CONFIG_BR2_OR2_BASE=0xE0700000 +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_1_MBYTES=y +CONFIG_OR2_SCY_5=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y +CONFIG_CMD_IOLOOP=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_CPU=y +CONFIG_CMD_BINOP=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_AXI=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_MII_DRIVER=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_HASH=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT2=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_AXI=y +CONFIG_IHS_AXI=y +CONFIG_CLK=y +CONFIG_ICS8N3QV01=y +CONFIG_CPU=y +CONFIG_CPU_MPC83XX=y +CONFIG_BOARD=y +CONFIG_BOARD_GAZERBEAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_IHS=y +CONFIG_MISC=y +CONFIG_GDSYS_RXAUI_CTRL=y +CONFIG_GDSYS_IOEP=y +CONFIG_MPC83XX_SERDES=y +CONFIG_GDSYS_SOC=y +CONFIG_IHS_FPGA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_RAM=y +CONFIG_MPC83XX_SDRAM=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_MCP83XX=y +CONFIG_TIMER=y +CONFIG_MPC83XX_TIMER=y +CONFIG_TPM_ATMEL_TWI=y +CONFIG_TPM_AUTH_SESSIONS=y +# CONFIG_TPM_V2 is not set +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LOGICORE_DP_TX=y +CONFIG_OSD=y +CONFIG_IHS_VIDEO_OUT=y +CONFIG_TPM=y diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h new file mode 100644 index 00000000000..11d367a1519 --- /dev/null +++ b/include/configs/gazerbeam.h @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2015 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * DDR Setup + */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE + +/* + * Memory test + * TODO: Migrate! + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07e00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/* + * Environment + */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * For booting Linux, the board info and command line data + * have to be in the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +/* TODO: Turn into string option and migrate to Kconfig */ +#define CONFIG_HOSTNAME "gazerbeam" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS1\0" \ + "u-boot=u-boot.bin\0" \ + "kernel_addr=1000000\0" \ + "fdt_addr=C00000\0" \ + "fdtfile=hrcon.dtb\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ + " +${filesize};cp.b ${fileaddr} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp ${kernel_addr} $bootfile;" \ + "tftp ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_MMCBOOTCOMMAND \ + "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ + "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ + "bootm ${kernel_addr} - ${fdt_addr}" + +#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND + +#endif /* __CONFIG_H */

-- 2.20.1

Mario Six

20 May 20 May

2:49 p.m.

New subject: [U-Boot] [PATCH 16/16] mpc83xx: Add gazerbeam board

On Fri, Mar 29, 2019 at 10:18 AM Mario Six mario.six@gdsys.cc wrote:

...

From: Dirk Eibach dirk.eibach@gdsys.cc

The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card.

On board peripherals include:

2x 10/100 Mbit/s Ethernet (optional)

Signed-off-by: Dirk Eibach dirk.eibach@gdsys.cc Signed-off-by: Mario Six mario.six@gdsys.cc

arch/powerpc/cpu/mpc83xx/Kconfig | 19 +++ arch/powerpc/dts/gazerbeam.dts | 2 +- board/gdsys/common/Makefile | 1 + board/gdsys/mpc8308/Kconfig | 29 ++++- board/gdsys/mpc8308/MAINTAINERS | 2 + board/gdsys/mpc8308/Makefile | 1 + board/gdsys/mpc8308/gazerbeam.c | 179 ++++++++++++++++++++++++++++ configs/gazerbeam_defconfig | 196 +++++++++++++++++++++++++++++++ include/configs/gazerbeam.h | 137 +++++++++++++++++++++ 9 files changed, 564 insertions(+), 2 deletions(-) create mode 100644 board/gdsys/mpc8308/gazerbeam.c create mode 100644 configs/gazerbeam_defconfig create mode 100644 include/configs/gazerbeam.h

diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index fe20e85086b..b99288aa836 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -175,6 +175,25 @@ config TARGET_STRIDER select SYS_FSL_ERRATUM_ESDHC111 imply CMD_PCA953X

+config TARGET_GAZERBEAM
  bool "Support gazerbeam"
  select ARCH_MPC8308
  select SYS_FSL_ERRATUM_ESDHC111
  imply ENV_IS_IN_FLASH
  help
    The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH
    Systementwicklung based on the NXP MPC8308 SoC for usage in KVM
    appliances.
    Features include:
    * Two gigabit ethernet ports
    * Multiple USB ports (depending on variant)
    * Several gigabit ethernet or optical fiber ports (depending on
      variant)
    * Several display port inputs and outputs, and supporting redrivers
      (depending on variant)
    * Several FPGAs with custom logic (depending on variant)
endchoice

config MPC83XX_QUICC_ENGINE diff --git a/arch/powerpc/dts/gazerbeam.dts b/arch/powerpc/dts/gazerbeam.dts index 5d171519e01..96c03c77ae8 100644 --- a/arch/powerpc/dts/gazerbeam.dts +++ b/arch/powerpc/dts/gazerbeam.dts @@ -10,7 +10,7 @@

option) any later version.

*/

-/include/ "gdsys/mpc8308.dtsi" +#include "gdsys/mpc8308.dtsi"

/include/ "gdsys/gazerbeam-base.dtsi"

diff --git a/board/gdsys/common/Makefile b/board/gdsys/common/Makefile index ff8d6f49665..7dfe104561a 100644 --- a/board/gdsys/common/Makefile +++ b/board/gdsys/common/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7 obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o obj-$(CONFIG_STRIDER_CON) += osd.o obj-$(CONFIG_STRIDER_CON_DP) += osd.o +obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o

ifdef CONFIG_OSD obj-$(CONFIG_GDSYS_LEGACY_OSD_CMDS) += osd_cmd.o diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig index e6a47960547..30811889fbf 100644 --- a/board/gdsys/mpc8308/Kconfig +++ b/board/gdsys/mpc8308/Kconfig @@ -71,7 +71,28 @@ config GDSYS_LEGACY_DRIVERS

endif

-if TARGET_HRCON || TARGET_STRIDER +if TARGET_GAZERBEAM

+config SYS_BOARD
  default "mpc8308"
+config SYS_VENDOR
  default "gdsys"
+config SYS_CONFIG_NAME
  default "gazerbeam"
+config SYS_FPGA1_BASE
  default E0700000
+config SYS_FPGA1_SIZE
  default 1
+config GDSYS_LEGACY_OSD_CMDS
  default y
+endif

+if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM

choice prompt "FPGA flavor selection" @@ -89,6 +110,12 @@ config SYS_FPGA_FLAVOR_GAZERBEAM

endchoice

+config EXTENDED_FEATURES
  bool "FPGA extended features"
  depends on GDSYS_LEGACY_DRIVERS
  help
    Enable support for the extended features field of the IHS FPGA.
config CMD_IOLOOP bool "Enable 'ioloop' and 'ioreflect' commands" help diff --git a/board/gdsys/mpc8308/MAINTAINERS b/board/gdsys/mpc8308/MAINTAINERS index 755b9a23858..ed1b6fa1062 100644 --- a/board/gdsys/mpc8308/MAINTAINERS +++ b/board/gdsys/mpc8308/MAINTAINERS @@ -6,7 +6,9 @@ F: include/configs/hrcon.h F: configs/hrcon_defconfig F: configs/hrcon_dh_defconfig F: include/configs/strider.h +F: configs/strider_defconfig F: configs/strider_cpu_defconfig F: configs/strider_cpu_dp_defconfig F: configs/strider_con_defconfig F: configs/strider_con_dp_defconfig +F: configs/gazerbeam_defconfig diff --git a/board/gdsys/mpc8308/Makefile b/board/gdsys/mpc8308/Makefile index dc579479f95..9af5fe04d18 100644 --- a/board/gdsys/mpc8308/Makefile +++ b/board/gdsys/mpc8308/Makefile @@ -6,3 +6,4 @@ obj-y := mpc8308.o sdram.o obj-$(CONFIG_TARGET_HRCON) += hrcon.o obj-$(CONFIG_TARGET_STRIDER) += strider.o +obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c new file mode 100644 index 00000000000..cd621744d28 --- /dev/null +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -0,0 +1,179 @@ +/*

(C) Copyright 2015

Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de

SPDX-License-Identifier: GPL-2.0+

*/

+#include <common.h> +#include <board.h> +#include <dm.h> +#include <fdt_support.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <misc.h> +#include <tpm-v1.h> +#include <video_osd.h>

+#include "../common/ihs_mdio.h" +#include "../../../drivers/board/gazerbeam.h"

+DECLARE_GLOBAL_DATA_PTR;

+struct ihs_mdio_info ihs_mdio_info[] = {
  { .fpga = NULL, .name = "ihs0", .base = 0x58 },
  { .fpga = NULL, .name = "ihs1", .base = 0x58 },
+};

+static int get_tpm(struct udevice **devp) +{
  int rc;
  rc = uclass_first_device_err(UCLASS_TPM, devp);
  if (rc) {
          printf("Could not find TPM (ret=%d)\n", rc);
          return CMD_RET_FAILURE;
  }
  return 0;
+}

+int board_early_init_r(void) +{
  struct udevice *board;
  struct udevice *serdes;
  int mc = 0;
  int con = 0;
  if (board_get(&board))
          puts("Could not find board information device.\n");
  /* Initialize serdes */
  uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes);
  if (board_detect(board))
          puts("Device information detection failed.\n");
  board_get_int(board, BOARD_MULTICHANNEL, &mc);
  board_get_int(board, BOARD_VARIANT, &con);
  if (mc == 2 || mc == 1)
          dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
  if (mc == 4) {
          dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@20");
          dev_enable_by_path("/localbus@e0005000/iocon_uart@2,0");
          dev_enable_by_path("/fpga1bus");
  }
  if (mc == 2 || con == VAR_CON) {
          dev_enable_by_path("/fpga0bus/fpga0_video1");
          dev_enable_by_path("/fpga0bus/fpga0_iic_video1");
          dev_enable_by_path("/fpga0bus/fpga0_axi_video1");
  }
  if (con == VAR_CON) {
          dev_enable_by_path("/fpga0bus/fpga0_video0");
          dev_enable_by_path("/fpga0bus/fpga0_iic_video0");
          dev_enable_by_path("/fpga0bus/fpga0_axi_video0");
  }
  return 0;
+}

+int checkboard(void) +{
  struct udevice *board;
  char *s = env_get("serial#");
  int mc = 0;
  int con = 0;
  if (board_get(&board))
          puts("Could not find board information device.\n");
  board_get_int(board, BOARD_MULTICHANNEL, &mc);
  board_get_int(board, BOARD_VARIANT, &con);
  puts("Board: Gazerbeam ");
  printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
  printf("%s", con == VAR_CON ? "CON" : "CPU");
  if (s) {
          puts(", serial# ");
          puts(s);
  }
  puts("\n");
  return 0;
+}

+static void display_osd_info(struct udevice *osd,
                       struct video_osd_info *osd_info)
+{
  printf("OSD-%s: Digital-OSD version %01d.%02d, %d x %d characters\n",
         osd->name, osd_info->major_version, osd_info->minor_version,
         osd_info->width, osd_info->height);
+}

+int last_stage_init(void) +{
  int fpga_hw_rev = 0;
  int i;
  struct udevice *board;
  struct udevice *osd;
  struct video_osd_info osd_info;
  struct udevice *tpm;
  int ret;
  if (board_get(&board))
          puts("Could not find board information device.\n");
  if (board) {
          int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev);
          if (res)
                  printf("Could not determind FPGA HW revision (res = %d)\n", res);
  }
  env_set_ulong("fpga_hw_rev", fpga_hw_rev);
  ret = get_tpm(&tpm);
  if (ret || tpm_init(tpm) || tpm_startup(tpm, TPM_ST_CLEAR) ||
      tpm_continue_self_test(tpm)) {
          printf("TPM init failed\n");
  }
  if (fpga_hw_rev >= 4) {
          for (i = 0; i < 4; i++) {
                  struct udevice *rxaui;
                  char name[8];
                  snprintf(name, sizeof(name), "rxaui%d", i);
                  /* Disable RXAUI polarity inversion */
                  ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui);
                  if (!ret)
                          misc_set_enabled(rxaui, false);
          }
  }
  for (uclass_first_device(UCLASS_VIDEO_OSD, &osd);
       osd;
       uclass_next_device(&osd)) {
          video_osd_get_info(osd, &osd_info);
          display_osd_info(osd, &osd_info);
  }
  return 0;
+}

+#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{
  ft_cpu_setup(blob, bd);
  fsl_fdt_fixup_dr_usb(blob, bd);
  fdt_fixup_esdhc(blob, bd);
  return 0;
+} +#endif diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig new file mode 100644 index 00000000000..346b1b2eaa8 --- /dev/null +++ b/configs/gazerbeam_defconfig @@ -0,0 +1,196 @@ +CONFIG_PPC=y +CONFIG_SYS_TEXT_BASE=0xFE000000 +CONFIG_SYS_MALLOC_F_LEN=0x600 +CONFIG_IDENT_STRING=" gazerbeam 0.01" +CONFIG_SYS_CLK_FREQ=33333333 +CONFIG_MPC83xx=y +CONFIG_TARGET_GAZERBEAM=y +CONFIG_SYSTEM_PLL_VCO_DIV_2=y +CONFIG_SYSTEM_PLL_FACTOR_4_1=y +CONFIG_CORE_PLL_RATIO_3_1=y +CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y +CONFIG_TSEC1_MODE_RGMII=y +CONFIG_TSEC2_MODE_RGMII=y +CONFIG_BAT0=y +CONFIG_BAT0_NAME="SDRAM" +CONFIG_BAT0_BASE=0x00000000 +CONFIG_BAT0_LENGTH_128_MBYTES=y +CONFIG_BAT0_ACCESS_RW=y +CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y +CONFIG_BAT0_USER_MODE_VALID=y +CONFIG_BAT0_SUPERVISOR_MODE_VALID=y +CONFIG_BAT1=y +CONFIG_BAT1_NAME="IMMR" +CONFIG_BAT1_BASE=0xE0000000 +CONFIG_BAT1_LENGTH_8_MBYTES=y +CONFIG_BAT1_ACCESS_RW=y +CONFIG_BAT1_ICACHE_INHIBITED=y +CONFIG_BAT1_ICACHE_GUARDED=y +CONFIG_BAT1_DCACHE_INHIBITED=y +CONFIG_BAT1_DCACHE_GUARDED=y +CONFIG_BAT1_USER_MODE_VALID=y +CONFIG_BAT1_SUPERVISOR_MODE_VALID=y +CONFIG_BAT2=y +CONFIG_BAT2_NAME="FLASH" +CONFIG_BAT2_BASE=0xFE000000 +CONFIG_BAT2_LENGTH_8_MBYTES=y +CONFIG_BAT2_ACCESS_RW=y +CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y +CONFIG_BAT2_DCACHE_INHIBITED=y +CONFIG_BAT2_DCACHE_GUARDED=y +CONFIG_BAT2_USER_MODE_VALID=y +CONFIG_BAT2_SUPERVISOR_MODE_VALID=y +CONFIG_BAT3=y +CONFIG_BAT3_NAME="INIT_RAM" +CONFIG_BAT3_BASE=0xE6000000 +CONFIG_BAT3_ACCESS_RW=y +CONFIG_BAT3_USER_MODE_VALID=y +CONFIG_BAT3_SUPERVISOR_MODE_VALID=y +CONFIG_LBLAW0=y +CONFIG_LBLAW0_BASE=0xFE000000 +CONFIG_LBLAW0_NAME="FLASH" +CONFIG_LBLAW0_LENGTH_8_MBYTES=y +CONFIG_LBLAW1=y +CONFIG_LBLAW1_BASE=0xE0600000 +CONFIG_LBLAW1_NAME="FPGA0" +CONFIG_LBLAW1_LENGTH_1_MBYTES=y +CONFIG_LBLAW2=y +CONFIG_LBLAW2_BASE=0xE0700000 +CONFIG_LBLAW2_NAME="FPGA1" +CONFIG_LBLAW2_LENGTH_1_MBYTES=y +CONFIG_ELBC_BR0_OR0=y +CONFIG_BR0_OR0_NAME="FLASH" +CONFIG_BR0_OR0_BASE=0xFE000000 +CONFIG_BR0_PORTSIZE_16BIT=y +CONFIG_OR0_AM_8_MBYTES=y +CONFIG_OR0_SCY_15=y +CONFIG_OR0_CSNT_EARLIER=y +CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y +CONFIG_OR0_XACS_EXTENDED=y +CONFIG_OR0_TRLX_RELAXED=y +CONFIG_OR0_EHTR_8_CYCLE=y +CONFIG_ELBC_BR1_OR1=y +CONFIG_BR1_OR1_NAME="FPGA0" +CONFIG_BR1_OR1_BASE=0xE0600000 +CONFIG_BR1_PORTSIZE_16BIT=y +CONFIG_OR1_AM_1_MBYTES=y +CONFIG_OR1_SCY_5=y +CONFIG_OR1_CSNT_EARLIER=y +CONFIG_ELBC_BR2_OR2=y +CONFIG_BR2_OR2_NAME="FPGA1" +CONFIG_BR2_OR2_BASE=0xE0700000 +CONFIG_BR2_PORTSIZE_16BIT=y +CONFIG_OR2_AM_1_MBYTES=y +CONFIG_OR2_SCY_5=y +CONFIG_OR2_CSNT_EARLIER=y +CONFIG_HID0_FINAL_EMCP=y +CONFIG_HID0_FINAL_DPM=y +CONFIG_HID0_FINAL_ICE=y +CONFIG_HID2_HBE=y +CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y +CONFIG_SICR_GPIO_A_TSEC2=y +CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y +CONFIG_SICR_IEEE1588_A_GPIO=y +CONFIG_SICR_GTM_GPIO=y +CONFIG_SICR_ETSEC2_GPIO=y +CONFIG_SICR_GPIOSEL_IEEE1588=y +CONFIG_SICR_TMSOBI1_2_5_V=y +CONFIG_SICR_TMSOBI2_2_5_V=y +CONFIG_ACR_PIPE_DEP_4=y +CONFIG_ACR_RPTCNT_4=y +CONFIG_SPCR_TSECEP_3=y +CONFIG_LCRR_DBYP_PLL_BYPASSED=y +CONFIG_LCRR_CLKDIV_2=y +CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y +CONFIG_CMD_IOLOOP=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=5 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_CPUINFO=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_CMD_CPU=y +CONFIG_CMD_BINOP=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_AXI=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_MII=y +CONFIG_CMD_MII_DRIVER=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_HASH=y +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT2=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" +CONFIG_DM=y +CONFIG_REGMAP=y +CONFIG_AXI=y +CONFIG_IHS_AXI=y +CONFIG_CLK=y +CONFIG_ICS8N3QV01=y +CONFIG_CPU=y +CONFIG_CPU_MPC83XX=y +CONFIG_BOARD=y +CONFIG_BOARD_GAZERBEAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_MPC8XXX_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_FSL=y +CONFIG_SYS_I2C_IHS=y +CONFIG_MISC=y +CONFIG_GDSYS_RXAUI_CTRL=y +CONFIG_GDSYS_IOEP=y +CONFIG_MPC83XX_SERDES=y +CONFIG_GDSYS_SOC=y +CONFIG_IHS_FPGA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_PHYLIB_10G=y +CONFIG_PHY_MARVELL=y +CONFIG_DM_ETH=y +CONFIG_TSEC_ENET=y +# CONFIG_PCI is not set +CONFIG_RAM=y +CONFIG_MPC83XX_SDRAM=y +CONFIG_DM_RESET=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_MCP83XX=y +CONFIG_TIMER=y +CONFIG_MPC83XX_TIMER=y +CONFIG_TPM_ATMEL_TWI=y +CONFIG_TPM_AUTH_SESSIONS=y +# CONFIG_TPM_V2 is not set +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_LOGICORE_DP_TX=y +CONFIG_OSD=y +CONFIG_IHS_VIDEO_OUT=y +CONFIG_TPM=y diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h new file mode 100644 index 00000000000..11d367a1519 --- /dev/null +++ b/include/configs/gazerbeam.h @@ -0,0 +1,137 @@ +/*

(C) Copyright 2015

Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de

SPDX-License-Identifier: GPL-2.0+

*/

+#ifndef __CONFIG_H +#define __CONFIG_H

+/*

DDR Setup

*/

+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ +/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE

+/*

Memory test

TODO: Migrate!

*/

+#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07e00000

+/*

The reserved memory

*/

+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */

+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */

+/*

Initial RAM Base Address Setup

*/

+#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET \
  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+/*

FLASH on the Local Bus

*/

+#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */

+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135

+#define CONFIG_SYS_BAUDRATE_TABLE \
  {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+/*

Environment

*/

+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
                           CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE

+#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */

+/*

Miscellaneous configurable options

*/

+#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */

+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */

+/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+/*

For booting Linux, the board info and command line data

have to be in the first 256 MB of memory, since this is

the maximum mapped by the Linux kernel during initialization.

*/

+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */

+/*

Environment Configuration

*/

+#define CONFIG_ENV_OVERWRITE

+#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1

+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */

+/* TODO: Turn into string option and migrate to Kconfig */ +#define CONFIG_HOSTNAME "gazerbeam" +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage"

+#define CONFIG_PREBOOT /* enable preboot variable */

+#define CONFIG_EXTRA_ENV_SETTINGS \
  "netdev=eth0\0"                                                 \
  "consoledev=ttyS1\0"                                            \
  "u-boot=u-boot.bin\0"                                           \
  "kernel_addr=1000000\0"                                 \
  "fdt_addr=C00000\0"                                             \
  "fdtfile=hrcon.dtb\0"                           \
  "load=tftp ${loadaddr} ${u-boot}\0"                             \
  "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
          " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
          " +${filesize};cp.b ${fileaddr} "                       \
          __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
  "upd=run load update\0"                                         \
+#define CONFIG_NFSBOOTCOMMAND \
  "setenv bootargs root=/dev/nfs rw "                             \
  "nfsroot=$serverip:$rootpath "                                  \
  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  "console=$consoledev,$baudrate $othbootargs;"                   \
  "tftp ${kernel_addr} $bootfile;"                                \
  "tftp ${fdt_addr} $fdtfile;"                                    \
  "bootm ${kernel_addr} - ${fdt_addr}"
+#define CONFIG_MMCBOOTCOMMAND \
  "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
  "console=$consoledev,$baudrate $othbootargs;"                   \
  "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
  "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
  "bootm ${kernel_addr} - ${fdt_addr}"
+#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND

+#endif /* __CONFIG_H */

2.20.1

Whole series applied to u-boot-mpc83xx/next.

Best regards, Mario

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Mario Six