[PATCH 1/1] doc: fix board/openpiton/riscv64.rst

* remove duplicate heading to avoid build error with 'make htmldocs' * length of underlines must match header * use appropriate header levels * fix type %s/linux/Linux/
Signed-off-by: Heinrich Schuchardt xypron.glpk@gmx.de --- doc/board/openpiton/riscv64.rst | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst index 253b37c41c..3a97793f07 100644 --- a/doc/board/openpiton/riscv64.rst +++ b/doc/board/openpiton/riscv64.rst @@ -3,8 +3,6 @@ Openpiton RISC-V SoC ====================
-OpenPiton RISC-V SoC --------------------- OpenPiton is an open source, manycore processor and research platform. It is a tiled manycore framework scalable from one to 1/2 billion cores. It supports a number of ISAs including RISC-V with its P-Mesh cache coherence protocol and @@ -14,21 +12,23 @@ running full-stack Debian linux.
RISC-V Standard Bootflow ------------------------- + Currently, OpenPiton implements RISC-V standard bootflow in the following steps mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition --------------------- + If you'd like to build OpenPiton, please go to OpenPiton github repo (at https://github.com/PrincetonUniversity/openpiton) to build from the latest changes
Building Images ---------------------------- +---------------
SPL ---- +~~~
1. Add the RISC-V toolchain to your PATH. 2. Setup ARCH & cross compilation environment variable: @@ -42,7 +42,7 @@ SPL 4. make
U-Boot ------- +~~~~~~
1. Add the RISC-V toolchain to your PATH. 2. Setup ARCH & cross compilation environment variable: @@ -55,9 +55,8 @@ U-Boot 3. make openpiton_riscv64_defconfig 4. make
- opensbi -------- +~~~~~~~
1. Add the RISC-V toolchain to your PATH. 2. Setup ARCH & cross compilation environment variable: @@ -70,9 +69,9 @@ opensbi 3. Go to OpenSBI directory 4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
+Using fw_payload.bin with Linux +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Using fw_payload.bin with linux -------------------------------- Put the generated fw_payload.bin into the /boot directory on the root filesystem, plug in the SD card, then flash the bitstream. Linux will boot automatically.
@@ -81,7 +80,7 @@ Booting Once you plugin the sdcard and power up, you should see the U-Boot prompt.
Sample Dual-core Debian boot log from OpenPiton ------------------------------------------------ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: none
-- 2.30.2

Hi Heinrich,
Many thanks for the patches. I've tested them and they fix the previous errors.
Reviewed-by: Tianrui Wei tianrui-wei@outlook.com
Heinrich Schuchardt xypron.glpk@gmx.de writes:
- remove duplicate heading to avoid build error with 'make
htmldocs'
- length of underlines must match header
- use appropriate header levels
- fix type %s/linux/Linux/
Signed-off-by: Heinrich Schuchardt xypron.glpk@gmx.de
doc/board/openpiton/riscv64.rst | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst index 253b37c41c..3a97793f07 100644 --- a/doc/board/openpiton/riscv64.rst +++ b/doc/board/openpiton/riscv64.rst @@ -3,8 +3,6 @@ Openpiton RISC-V SoC ====================
-OpenPiton RISC-V SoC
OpenPiton is an open source, manycore processor and research platform. It is a tiled manycore framework scalable from one to 1/2 billion cores. It supports a number of ISAs including RISC-V with its P-Mesh cache coherence protocol and @@ -14,21 +12,23 @@ running full-stack Debian linux.
RISC-V Standard Bootflow
Currently, OpenPiton implements RISC-V standard bootflow in the following steps mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition
If you'd like to build OpenPiton, please go to OpenPiton github repo (at https://github.com/PrincetonUniversity/openpiton) to build from the latest changes
Building Images
+---------------
SPL
+~~~
- Add the RISC-V toolchain to your PATH.
- Setup ARCH & cross compilation environment variable:
@@ -42,7 +42,7 @@ SPL 4. make
U-Boot
+~~~~~~
- Add the RISC-V toolchain to your PATH.
- Setup ARCH & cross compilation environment variable:
@@ -55,9 +55,8 @@ U-Boot 3. make openpiton_riscv64_defconfig 4. make
opensbi
+~~~~~~~
- Add the RISC-V toolchain to your PATH.
- Setup ARCH & cross compilation environment variable:
@@ -70,9 +69,9 @@ opensbi 3. Go to OpenSBI directory 4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
+Using fw_payload.bin with Linux +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-Using fw_payload.bin with linux
Put the generated fw_payload.bin into the /boot directory on the root filesystem, plug in the SD card, then flash the bitstream. Linux will boot automatically.
@@ -81,7 +80,7 @@ Booting Once you plugin the sdcard and power up, you should see the U-Boot prompt.
Sample Dual-core Debian boot log from OpenPiton
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. code-block:: none
--
participants (2)
-
Heinrich Schuchardt
-
Tianrui Wei