[PATCH 0/3] boards: ls2080aqds: transition to CONFIG_DM_ETH
This patch set targets to add support for CONFIG_DM_ETH for the NXP LS2080AQDS board.
The main focus is on changing the DTS based on the SERDES protocol used. In order to accomplish this, the MULTI_DTB_FIT feature is employed and the appropriate DTS is chosed on boot from a list of predefined files.
Any unnecessary configurations made for the DPAA2 ethernet devices in the board files are compiled out when CONFIG_DM_ETH is enabled. This is because any information necessary is available in its associated DTS node.
This patch set depends on another series that adds support for DM_ETH in the ldpaa_eth driver and the RDB boards: https://patchwork.ozlabs.org/project/uboot/list/?series=165158&state=*
For the moment, when CONFIG_DM_ETH is enabled DPAA2 networking is supported only for the SERDES block #1 protocol 42 (0x2a).
Ioana Ciornei (3): board: ls2080aqds: transition to DM_ETH arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support configs: ls2080aqds_tfa_defconfig: enable DM_ETH and related
arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls2080a-qds-42-x.dts | 16 ++++ arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 48 ++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 73 +-------------- arch/arm/dts/fsl-ls2080a-qds.dtsi | 78 ++++++++++++++++ board/freescale/ls2080aqds/eth.c | 110 ++++++++++++++++++++++- board/freescale/ls2080aqds/ls2080aqds.c | 4 + configs/ls2088aqds_tfa_defconfig | 10 ++- 8 files changed, 266 insertions(+), 74 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-qds-42-x.dts create mode 100644 arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi create mode 100644 arch/arm/dts/fsl-ls2080a-qds.dtsi
In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- board/freescale/ls2080aqds/eth.c | 13 +++++++++++-- board/freescale/ls2080aqds/ls2080aqds.c | 4 ++++ 2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index bbb70a859a1e..47f57d94b847 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -24,6 +24,8 @@
#define MC_BOOT_ENV_VAR "mcinitcmd"
+#ifndef CONFIG_DM_ETH + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H @@ -889,9 +891,11 @@ void ls2080a_handle_phy_interface_xsgmii(int i) } } #endif +#endif // !CONFIG_DM_ETH
int board_eth_init(bd_t *bis) { +#ifndef CONFIG_DM_ETH int error; #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; @@ -970,8 +974,13 @@ int board_eth_init(bd_t *bis) sgmii_configure_repeater(2); } #endif - error = pci_eth_init(bis); - return error; +#endif // !CONFIG_DM_ETH + +#ifdef CONFIG_DM_ETH + return 0; +#else + return pci_eth_init(bis); +#endif }
#if defined(CONFIG_RESET_PHY_R) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 4034bdee2842..1c91c5b7f052 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -251,6 +251,10 @@ int board_init(void) ppa_init(); #endif
+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif + return 0; }
Add support for selecting the appropriate DTS file depending on the SERDES protocol used.
The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol.
This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x21) on SD#1.
Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls2080a-qds-42-x.dts | 16 ++++ arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 48 ++++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 73 +----------------- arch/arm/dts/fsl-ls2080a-qds.dtsi | 78 +++++++++++++++++++ board/freescale/ls2080aqds/eth.c | 97 ++++++++++++++++++++++++ 6 files changed, 242 insertions(+), 71 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-qds-42-x.dts create mode 100644 arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi create mode 100644 arch/arm/dts/fsl-ls2080a-qds.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9cf65e5be3f9..b6df24fdb2ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -369,6 +369,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ diff --git a/arch/arm/dts/fsl-ls2080a-qds-42-x.dts b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts new file mode 100644 index 000000000000..bd46c395d45c --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080AQDS device tree source for SERDES protocol 42.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls2080a-qds-sd1-42.dtsi" + +/ { + model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi new file mode 100644 index 000000000000..ccbb5de1eaef --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac3 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac5 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac6 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac7 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac8 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index 13461b5c4580..a1196f929287 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a QDS board device tree source + * Freescale ls2080a QDS defaul board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. */
/dts-v1/;
-#include "fsl-ls2080a.dtsi" +#include "fsl-ls2080a-qds.dtsi"
/ { model = "Freescale Layerscape 2080a QDS Board"; @@ -18,72 +18,3 @@ spi1 = &dspi; }; }; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&qspi { - bus-num = <0>; - status = "okay"; - - qflash0: s25fs256s@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi new file mode 100644 index 000000000000..aafabb44205d --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Freescale ls2080a QDS common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a.dtsi" + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fs256s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 47f57d94b847..bbed1324ca4a 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -989,3 +989,100 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 42, true}, + + /* Serdes block #2 */ + {2, 65, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + printf("expected_dts %s\n", expected_dts); + sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + printf("this is not!\n"); + return -1; +} + +#endif
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LS2080AQDS board.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com --- configs/ls2088aqds_tfa_defconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9f49736b4f31..9eb7effce56d 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -3,8 +3,8 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_NR_DRAM_BANKS=3 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y @@ -21,6 +21,7 @@ CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -33,6 +34,8 @@ CONFIG_MP=y # CONFIG_ISO_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds" +CONFIG_OF_LIST="fsl-ls2080a-qds-42-x" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -56,9 +59,14 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y CONFIG_DM_SPI_FLASH=y CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 29, 2020 4:03 PM To: u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 3/3] configs: ls2080aqds_tfa_defconfig: enable DM_ETH and related
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LS2080AQDS board.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
configs/ls2088aqds_tfa_defconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9f49736b4f31..9eb7effce56d 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -3,8 +3,8 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_ENV_SECT_SIZE=0x20000
<snip>
Why you need above change?
Regards Priyanka
Subject: RE: [PATCH 3/3] configs: ls2080aqds_tfa_defconfig: enable DM_ETH and related
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Ioana Ciornei Sent: Wednesday, April 29, 2020 4:03 PM To: u-boot@lists.denx.de; Priyanka Jain priyanka.jain@nxp.com Cc: Alexandru Marginean alexandru.marginean@nxp.com; Madalin Bucur madalin.bucur@nxp.com; Florin Laurentiu Chiculita florinlaurentiu.chiculita@nxp.com; Razvan Ionut Cirjan razvanionut.cirjan@nxp.com; Ioana Ciornei ioana.ciornei@nxp.com Subject: [PATCH 3/3] configs: ls2080aqds_tfa_defconfig: enable DM_ETH and related
Enable CONFIG_DM_ETH and CONFIG_DM_MDIO and related configs for the LS2080AQDS board.
Signed-off-by: Ioana Ciornei ioana.ciornei@nxp.com
configs/ls2088aqds_tfa_defconfig | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 9f49736b4f31..9eb7effce56d 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -3,8 +3,8 @@ CONFIG_TARGET_LS2080AQDS=y CONFIG_TFABOOT=y CONFIG_SYS_TEXT_BASE=0x82000000 CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_ENV_OFFSET=0x500000 +CONFIG_ENV_SECT_SIZE=0x20000
<snip>
Why you need above change?
Regards Priyanka
The change above resulted from a make savedefconfig. It's not needed but it would be good to have the defconfigs aligned with the result of the make command.
Regards, Ioana
participants (2)
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Ioana Ciornei -
Priyanka Jain (OSS)