[U-Boot] [PATCH V2 00/12] ARM: DRA7xx: Update support for DRA7xx Soc's
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt1559...
Testing: Boot tested on DRA752 ES1.0, OMAP5432 ES2.0, OMAP4460 PANDA Verified MAKEALL for armv7 and omap boards.
Changes from v1: * Addressed comments from Tom Rini
Balaji T K (1): mmc: omap_hsmmc: add mmc1 pbias, ldo1
Lokesh Vutla (6): ARM: DRA7xx: Add control id code for DRA7xx ARM: DRA7xx: power Add support for tps659038 PMIC ARM: DRA7xx: clocks: Fixing i2c_init for PMIC ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's ARM: DRA7xx: Update pinmux data ARM: DRA7xx: clocks: Update PLL values
Nishanth Menon (1): ARM: OMAP5: DRA7xx: support class 0 optimized voltages
Sricharan R (4): ARM: DRA7xx: Change the Debug UART to UART1 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ ARM: DRA7xx: Correct SRAM END address ARM: DRA7xx: EMIF: Change settings required for EVM board
arch/arm/cpu/armv7/omap-common/clocks-common.c | 86 +++++++++--- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 2 - arch/arm/cpu/armv7/omap-common/timer.c | 1 + arch/arm/cpu/armv7/omap5/hw_data.c | 156 ++++++++++++++++------ arch/arm/cpu/armv7/omap5/hwinit.c | 22 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 + arch/arm/cpu/armv7/omap5/sdram.c | 170 ++++++++++++++++++++++-- arch/arm/include/asm/arch-omap4/clock.h | 6 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/clock.h | 61 ++++++++- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 7 +- arch/arm/include/asm/arch-omap5/omap.h | 26 ++-- arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/emif.h | 12 +- arch/arm/include/asm/omap_common.h | 26 +++- board/ti/dra7xx/mux_data.h | 38 ++++-- drivers/mmc/omap_hsmmc.c | 26 ++-- drivers/power/palmas.c | 25 +++- include/configs/dra7xx_evm.h | 8 +- include/configs/omap4_common.h | 4 - include/configs/omap5_common.h | 12 +- include/configs/omap5_uevm.h | 7 +- include/palmas.h | 6 +- 24 files changed, 590 insertions(+), 141 deletions(-)
The registers that are used for device identification are changed from OMAP5 to DRA7xx. Using the correct registers for DRA7xx.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 11 +++++++++-- include/configs/dra7xx_evm.h | 3 ++- 2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 6dfedf4..3222996 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -44,8 +44,15 @@ #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
-/* CONTROL_ID_CODE */ -#define CONTROL_ID_CODE 0x4A002204 +/* CONTROL ID CODE */ +#define CONTROL_CORE_ID_CODE 0x4A002204 +#define CONTROL_WKUP_ID_CODE 0x4AE0C204 + +#ifdef CONFIG_DRA7XX +#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE +#else +#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE +#endif
/* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 28a306b..7826d13 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,11 +28,12 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H
+/* High Level Configuration Options */ +#define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_ENV_IS_NOWHERE /* For now. */
#include <configs/omap5_common.h>
-#define CONFIG_DRA7XX /* in a TI DRA7XX core */ #define CONFIG_SYS_PROMPT "DRA752 EVM # "
#endif /* __CONFIG_DRA7XX_EVM_H */
TPS659038 is the power IC used in DRA7XX boards. Adding support for this and also adding pmic data for DRA7XX boards.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 23 ++++++++++++++ arch/arm/cpu/armv7/omap5/hw_data.c | 38 +++++++++++++++++++++++- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/clock.h | 15 ++++++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 3 ++ 6 files changed, 80 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index a1ada58..dc57516 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -30,6 +30,7 @@ * MA 02111-1307 USA */ #include <common.h> +#include <i2c.h> #include <asm/omap_common.h> #include <asm/gpio.h> #include <asm/arch/clock.h> @@ -487,6 +488,9 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) u32 offset = volt_mv; int ret = 0;
+ if (!volt_mv) + return; + pmic->pmic_bus_init(); /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) @@ -534,6 +538,15 @@ void scale_vcores(struct vcores_data const *vcores) do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic);
+ do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, + vcores->gpu.pmic); + + do_scale_vcore(vcores->eve.addr, vcores->eve.value, + vcores->eve.pmic); + + do_scale_vcore(vcores->iva.addr, vcores->iva.value, + vcores->iva.pmic); + if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ writel(2, (*prcm)->prm_sldo_core_setup); @@ -723,3 +736,13 @@ void prcm_init(void) if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) enable_basic_uboot_clocks(); } + +void gpi2c_init(void) +{ + static int gpi2c = 1; + + if (gpi2c) { + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + gpi2c = 0; + } +} diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 585e318..90274a0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -26,6 +26,7 @@ * MA 02111-1307 USA */ #include <common.h> +#include <palmas.h> #include <asm/arch/omap.h> #include <asm/arch/sys_proto.h> #include <asm/omap_common.h> @@ -294,6 +295,19 @@ struct pmic_data palmas = { .pmic_write = omap_vc_bypass_send_value, };
+struct pmic_data tps659038 = { + .base_offset = PALMAS_SMPS_BASE_VOLT_UV, + .step = 10000, /* 10 mV represented in uV */ + /* + * Offset codes 1-6 all give the base voltage in Palmas + * Offset code 0 switches OFF the SMPS + */ + .start_code = 6, + .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, + .pmic_bus_init = gpi2c_init, + .pmic_write = palmas_i2c_write_u8, +}; + struct vcores_data omap5430_volts = { .mpu.value = VDD_MPU, .mpu.addr = SMPS_REG_ADDR_12_MPU, @@ -322,6 +336,28 @@ struct vcores_data omap5430_volts_es2 = { .mm.pmic = &palmas, };
+struct vcores_data dra752_volts = { + .mpu.value = VDD_MPU_DRA752, + .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, + .mpu.pmic = &tps659038, + + .eve.value = VDD_EVE_DRA752, + .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, + .eve.pmic = &tps659038, + + .gpu.value = VDD_GPU_DRA752, + .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, + .gpu.pmic = &tps659038, + + .core.value = VDD_CORE_DRA752, + .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, + .core.pmic = &tps659038, + + .iva.value = VDD_IVA_DRA752, + .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -562,7 +598,7 @@ void hw_data_init(void) case DRA752_ES1_0: *prcm = &dra7xx_prcm; *dplls_data = &dra7xx_dplls; - *omap_vcores = &omap5430_volts_es2; + *omap_vcores = &dra752_volts; *ctrl = &dra7xx_ctrl; break;
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 38d4768..14479ba 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -57,6 +57,7 @@ u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 6673a02..f7ddd5f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -212,9 +212,24 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880
+/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ +#define VDD_MPU_DRA752 1090 +#define VDD_EVE_DRA752 1060 +#define VDD_GPU_DRA752 1060 +#define VDD_CORE_DRA752 1030 +#define VDD_IVA_DRA752 1060 + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000
+/* TPS659038 */ +#define TPS659038_I2C_SLAVE_ADDR 0x58 +#define TPS659038_REG_ADDR_SMPS12_MPU 0x23 +#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B +#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F +#define TPS659038_REG_ADDR_SMPS7_CORE 0x33 +#define TPS659038_REG_ADDR_SMPS8_IVA 0x37 + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 52c2271..8f6f3bf 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -61,6 +61,7 @@ u32 cortex_rev(void); void init_omap_revision(void); void do_io_settings(void); void sri2c_init(void); +void gpi2c_init(void); int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 3f1d31d..6b28f2e 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -510,6 +510,9 @@ struct vcores_data { struct volts mpu; struct volts core; struct volts mm; + struct volts gpu; + struct volts eve; + struct volts iva; };
extern struct prcm_regs const **prcm;
In DRA7xx Soc's voltage scaling is done using GPI2C. So i2c_init should happen before scaling. I2C driver uses __udelay which needs timer to be initialized. So moving timer_init just before voltage scaling. Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 1 + arch/arm/cpu/armv7/omap-common/hwinit-common.c | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index dc57516..0a5bda5 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -721,6 +721,7 @@ void prcm_init(void) case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: enable_basic_clocks(); + timer_init(); scale_vcores(*omap_vcores); setup_dplls(); #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 1645120..5602b0e 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -202,8 +202,6 @@ void s_init(void) #endif prcm_init(); #ifdef CONFIG_SPL_BUILD - timer_init(); - /* For regular u-boot sdram_init() is called from dram_init() */ sdram_init(); #endif
From: Nishanth Menon nm@ti.com
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.
This means that we can now use the optimized voltages which are stored as mV values in efuse and program PMIC accordingly.
This allows us to go with higher OPP as needed in the system without the need for implementing complex AVS logic.
Signed-off-by: Nishanth Menon nm@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 58 +++++++++++++++++++----- arch/arm/cpu/armv7/omap5/hw_data.c | 10 ++++ arch/arm/include/asm/arch-omap5/clock.h | 30 ++++++++++++ arch/arm/include/asm/omap_common.h | 11 +++++ 4 files changed, 97 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 0a5bda5..64fffd3 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -521,6 +521,38 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) gpio_direction_output(pmic->gpio, 1); }
+static u32 optimize_vcore_voltage(struct volts const *v) +{ + u32 val; + if (!v->value) + return 0; + if (!v->efuse.reg) + return v->value; + + switch (v->efuse.reg_bits) { + case 16: + val = readw(v->efuse.reg); + break; + case 32: + val = readl(v->efuse.reg); + break; + default: + printf("Error: efuse 0x%08x bits=%d unknown\n", + v->efuse.reg, v->efuse.reg_bits); + return v->value; + } + + if (!val) { + printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", + v->efuse.reg, v->efuse.reg_bits, v->value); + return v->value; + } + + debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", + __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); + return val; +} + /* * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva * We set the maximum voltages allowed here because Smart-Reflex is not @@ -529,23 +561,25 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) */ void scale_vcores(struct vcores_data const *vcores) { - do_scale_vcore(vcores->core.addr, vcores->core.value, - vcores->core.pmic); + u32 val; + + val = optimize_vcore_voltage(&vcores->core); + do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
- do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, - vcores->mpu.pmic); + val = optimize_vcore_voltage(&vcores->mpu); + do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
- do_scale_vcore(vcores->mm.addr, vcores->mm.value, - vcores->mm.pmic); + val = optimize_vcore_voltage(&vcores->mm); + do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
- do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, - vcores->gpu.pmic); + val = optimize_vcore_voltage(&vcores->gpu); + do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
- do_scale_vcore(vcores->eve.addr, vcores->eve.value, - vcores->eve.pmic); + val = optimize_vcore_voltage(&vcores->eve); + do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
- do_scale_vcore(vcores->iva.addr, vcores->iva.value, - vcores->iva.pmic); + val = optimize_vcore_voltage(&vcores->iva); + do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) { /* Configure LDO SRAM "magic" bits */ diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 90274a0..bddcaed 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -338,22 +338,32 @@ struct vcores_data omap5430_volts_es2 = {
struct vcores_data dra752_volts = { .mpu.value = VDD_MPU_DRA752, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU, .mpu.pmic = &tps659038,
.eve.value = VDD_EVE_DRA752, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE, .eve.pmic = &tps659038,
.gpu.value = VDD_GPU_DRA752, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU, .gpu.pmic = &tps659038,
.core.value = VDD_CORE_DRA752, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, .core.addr = TPS659038_REG_ADDR_SMPS7_CORE, .core.pmic = &tps659038,
.iva.value = VDD_IVA_DRA752, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA, .iva.pmic = &tps659038, }; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index f7ddd5f..6d02835 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -219,6 +219,36 @@ #define VDD_CORE_DRA752 1030 #define VDD_IVA_DRA752 1060
+/* Efuse register offsets for DRA7xx platform */ +#define DRA752_EFUSE_BASE 0x4A002000 +#define DRA752_EFUSE_REGBITS 16 +/* STD_FUSE_OPP_VMIN_IVA_2 */ +#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC) +/* STD_FUSE_OPP_VMIN_IVA_3 */ +#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0) +/* STD_FUSE_OPP_VMIN_IVA_4 */ +#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4) +/* STD_FUSE_OPP_VMIN_DSPEVE_2 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0) +/* STD_FUSE_OPP_VMIN_DSPEVE_3 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4) +/* STD_FUSE_OPP_VMIN_DSPEVE_4 */ +#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8) +/* STD_FUSE_OPP_VMIN_CORE_2 */ +#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4) +/* STD_FUSE_OPP_VMIN_GPU_2 */ +#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08) +/* STD_FUSE_OPP_VMIN_GPU_3 */ +#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C) +/* STD_FUSE_OPP_VMIN_GPU_4 */ +#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10) +/* STD_FUSE_OPP_VMIN_MPU_2 */ +#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20) +/* STD_FUSE_OPP_VMIN_MPU_3 */ +#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24) +/* STD_FUSE_OPP_VMIN_MPU_4 */ +#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28) + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 6b28f2e..1435674 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -500,9 +500,20 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); };
+/** + * struct volts_efuse_data - efuse definition for voltage + * @reg: register address for efuse + * @reg_bits: Number of bits in a register address, mandatory. + */ +struct volts_efuse_data { + u32 reg; + u8 reg_bits; +}; + struct volts { u32 value; u32 addr; + struct volts_efuse_data efuse; struct pmic_data *pmic; };
Slew rate compensation cells are not present for DRA7xx Soc's. So return from function srcomp_enable() if soc is not OMAP54xx.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 3 +++ arch/arm/include/asm/omap_common.h | 8 ++++++++ 2 files changed, 11 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index afb7000..40dbf45 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -201,6 +201,9 @@ void srcomp_enable(void) u32 sysclk_ind = get_sys_clk_index(); u32 omap_rev = omap_revision();
+ if (!is_omap54xx()) + return; + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; div_factor = srcomp_parameters[sysclk_ind].divide_factor;
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 1435674..7007177 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -575,6 +575,14 @@ static inline u32 omap_revision(void) extern u32 *const omap_si_rev; return *omap_si_rev; } + +#define OMAP54xx 0x54000000 + +static inline u8 is_omap54xx(void) +{ + extern u32 *const omap_si_rev; + return ((*omap_si_rev & 0xFF000000) == OMAP54xx); +} #endif
/*
From: Sricharan R r.sricharan@ti.com
Serial UART is connected to UART1. So add the change for the same.
Signed-off-by: Sricharan R r.sricharan@ti.com --- include/configs/dra7xx_evm.h | 3 +++ include/configs/omap5_common.h | 4 ---- include/configs/omap5_uevm.h | 4 ++++ 3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 7826d13..35dec08 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -36,4 +36,7 @@
#define CONFIG_SYS_PROMPT "DRA752 EVM # "
+#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 UART1_BASE +#define CONFIG_BAUDRATE 115200 #endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index deb5e9f..d57c0da 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -81,10 +81,6 @@ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -#define CONFIG_BAUDRATE 115200
/* CPU */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index c791789..ba81e30 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,6 +35,10 @@
#include <configs/omap5_common.h>
+#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 UART3_BASE +#define CONFIG_BAUDRATE 115200 + /* TWL6035 */ #ifndef CONFIG_SPL_BUILD #define CONFIG_PALMAS_POWER
From: Sricharan R r.sricharan@ti.com
The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards.
Signed-off-by: Sricharan R r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/timer.c | 1 + arch/arm/include/asm/arch-omap4/clock.h | 4 ++++ arch/arm/include/asm/arch-omap5/clock.h | 8 ++++++++ include/configs/omap4_common.h | 4 ---- include/configs/omap5_common.h | 4 ---- 5 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 507f687..5926a5a 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -35,6 +35,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/cpu.h> +#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index f544edf..d7b61c2 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -214,6 +214,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1
+/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + struct omap4_scrm_regs { u32 revision; /* 0x0000 */ u32 pad00[63]; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 6d02835..86d4711 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -284,4 +284,12 @@ * into microsec and passing the value. */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 + +#ifdef CONFIG_DRA7XX +#define V_OSCK 20000000 /* Clock output from T2 */ +#else +#define V_OSCK 19200000 /* Clock output from T2 */ +#endif + +#define V_SCLK V_OSCK #endif /* _CLOCKS_OMAP5_H_ */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index d6448b0..3e5d36b 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -45,10 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1
-/* Clock Defines */ -#define V_OSCK 38400000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - #define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1 diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index d57c0da..83b91d1 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -45,10 +45,6 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO
-/* Clock Defines */ -#define V_OSCK 19200000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - #define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT
From: Sricharan R r.sricharan@ti.com
NON SECURE SRAM is 512KB in DRA7xx devices. So fixing it here.
Signed-off-by: Sricharan R r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 3222996..8105c14 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -169,13 +169,14 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */
-/* - * Non-secure SRAM Addresses - * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE - * at 0x40304000(EMU base) so that our code works for both EMU and GP - */ +#ifdef CONFIG_DRA7XX +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ +#else #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ +#endif + /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 8105c14..9abb663 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -106,9 +106,10 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 << 27) #define SDCARD_PWRDNZ (1 << 26) #define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_BIAS_PWRDNZ (1 << 22) +#define SDCARD_BIAS_PWRDNZ2 (1 << 22) #define SDCARD_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__ diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afdfa88..27d1f76 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc) u32 value = 0;
value = readl((*ctrl)->control_pbias); - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; + value &= ~SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(10); /* wait 10 us */ + value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias);
- palmas_mmc1_poweron_ldo(); +#if defined(CONFIG_DRA7XX) + palmas_mmc1_poweron_ldo1(); +#else + palmas_mmc1_poweron_ldo9(); +#endif
value = readl((*ctrl)->control_pbias); - value &= ~SDCARD_BIAS_HIZ_MODE; - value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; + value |= SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); - - value = readl((*ctrl)->control_pbias); - if (value & (1 << 23)) { - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; - writel(value, (*ctrl)->control_pbias); - } + udelay(150); /* wait 150 us */ + value |= SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(150); /* wait 150 us */ } #endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 09c832d..1bcff52 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -28,7 +28,7 @@ void palmas_init_settings(void) return; }
-int palmas_mmc1_poweron_ldo(void) +int palmas_mmc1_poweron_ldo9(void) { u8 val = 0;
@@ -50,3 +50,26 @@ int palmas_mmc1_poweron_ldo(void)
return 0; } + +int palmas_mmc1_poweron_ldo1(void) +{ + u8 val = 0; + + /* set LDO9 TWL6035 to 3V */ + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ + + if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) { + printf("tps659038: could not set LDO1 voltage\n"); + return 1; + } + + /* TURN ON LDO9 */ + val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; + + if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_CTRL, val)) { + printf("tps659038: could not turn on LDO1\n"); + return 1; + } + + return 0; +} diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 83b91d1..ddf2ad4 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -238,6 +238,10 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index ba81e30..f4a2d31 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -39,11 +39,6 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200
-/* TWL6035 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif - /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ diff --git a/include/palmas.h b/include/palmas.h index 3b18589..4218e18 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -28,8 +28,11 @@
/* I2C chip addresses */ #define PALMAS_CHIP_ADDR 0x48 +#define TPS659038_CHIP_ADDR 0x58
/* 0x1XY translates to page 1, register address 0xXY */ +#define LDO1_CTRL 0x50 +#define LDO1_VOLTAGE 0x51 #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61
@@ -53,6 +56,7 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) }
void palmas_init_settings(void); -int palmas_mmc1_poweron_ldo(void); +int palmas_mmc1_poweron_ldo9(void); +int palmas_mmc1_poweron_ldo1(void);
#endif /* PALMAS_H */
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 09c832d..1bcff52 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -28,7 +28,7 @@ void palmas_init_settings(void) return; }
-int palmas_mmc1_poweron_ldo(void) +int palmas_mmc1_poweron_ldo9(void) { u8 val = 0;
@@ -50,3 +50,26 @@ int palmas_mmc1_poweron_ldo(void)
return 0; }
+int palmas_mmc1_poweron_ldo1(void) +{
- u8 val = 0;
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
- if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
printf("tps659038: could not set LDO1 voltage\n");return 1;- }
- /* TURN ON LDO9 */
LDO9?
- val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
Bit LDO_ON in all LDOx_CTRL Palmas registers is Read-Only (and reflects the current status of the LDO). While it makes no harm to try writing to it, this may be misleading about actual LDO operation, and anyway has no sense.
- if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_CTRL, val)) {
printf("tps659038: could not turn on LDO1\n");return 1;- }
[snip]
/* I2C chip addresses */ #define PALMAS_CHIP_ADDR 0x48 +#define TPS659038_CHIP_ADDR 0x58
Now we have a mess again. The files were recently renamed from twl6035.x to palmas.x, implying that palmas is the generic family name of a series of PMICs. Having TPS659038_CHIP_ADDR above is OK, but then we should have TWL603X_CHIP_ADDR instead of PALMAS_CHIP_ADDR.
Best regards, Lubomir
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 09c832d..1bcff52 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -28,7 +28,7 @@ void palmas_init_settings(void) return; }
-int palmas_mmc1_poweron_ldo(void) +int palmas_mmc1_poweron_ldo9(void) { u8 val = 0;
@@ -50,3 +50,26 @@ int palmas_mmc1_poweron_ldo(void)
return 0; }
+int palmas_mmc1_poweron_ldo1(void) +{
- u8 val = 0;
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
- if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
printf("tps659038: could not set LDO1 voltage\n");return 1;- }
- /* TURN ON LDO9 */
LDO9?
- val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
Bit LDO_ON in all LDOx_CTRL Palmas registers is Read-Only (and reflects the current status of the LDO). While it makes no harm to try writing to it, this may be misleading about actual LDO operation, and anyway has no sense.
Yes, I see a similar update in your patch for LDO9. ll do the same for LDO1 also.
Thanks Lokesh
- if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_CTRL, val)) {
printf("tps659038: could not turn on LDO1\n");return 1;- }
[snip]
/* I2C chip addresses */ #define PALMAS_CHIP_ADDR 0x48 +#define TPS659038_CHIP_ADDR 0x58
Now we have a mess again. The files were recently renamed from twl6035.x to palmas.x, implying that palmas is the generic family name of a series of PMICs. Having TPS659038_CHIP_ADDR above is OK, but then we should have TWL603X_CHIP_ADDR instead of PALMAS_CHIP_ADDR.
Best regards, Lubomir
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
- if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
printf("tps659038: could not set LDO1 voltage\n");return 1;- }
- /* TURN ON LDO9 */
LDO9?
- val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
Bit LDO_ON in all LDOx_CTRL Palmas registers is Read-Only (and reflects the current status of the LDO). While it makes no harm to try writing to it, this may be misleading about actual LDO operation, and anyway has no sense.
Yes, I see a similar update in your patch for LDO9. ll do the same for LDO1 also.
But are you sure that the TPS659038 has the same LDOx_CTRL register layout as the TWL6035/37? It belongs to the family, yes, but I don't have a Register Manual for this chip... Hope you have checked.
Thanks Lokesh
[snip]
Best regards, Lubo
Hi Lubomir,, On Tuesday 04 June 2013 01:28 AM, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Ahh sorry, I was in a dilemma whether to ask this or not. Since it is posted I assumed that the patch ll get merged. I have already posted a patch on top of your patch. Ill wait for Tom to comment.
Tom, your opinion?
- if (palmas_i2c_write_u8(TPS659038_CHIP_ADDR, LDO1_VOLTAGE, val)) {
printf("tps659038: could not set LDO1 voltage\n");return 1;- }
- /* TURN ON LDO9 */
LDO9?
- val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
Bit LDO_ON in all LDOx_CTRL Palmas registers is Read-Only (and reflects the current status of the LDO). While it makes no harm to try writing to it, this may be misleading about actual LDO operation, and anyway has no sense.
Yes, I see a similar update in your patch for LDO9. ll do the same for LDO1 also.
But are you sure that the TPS659038 has the same LDOx_CTRL register layout as the TWL6035/37? It belongs to the family, yes, but I don't have a Register Manual for this chip... Hope you have checked.
Yes, TPS659038 has same LDOx_CTRL register layout.
Thanks, Lokesh
Thanks Lokesh
[snip]
Best regards, Lubo
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
On Wednesday 05 June 2013 02:36 AM, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Ok. Ill add the first patch + cleanups and resend it.
Thanks, Lokesh
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
Best regards, Lubo
On Wed, Jun 05, 2013 at 11:03:26AM +0300, Lubomir Popov wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
OK, lets see. That so lets keep your patch as-is, since we've now got -ffunction-sections/-fdata-sections/--gc-sections on ARM for main U-Boot, these small things won't hurt like they used to.
Hi Tom,
On 05/06/13 16:45, Tom Rini wrote:
On Wed, Jun 05, 2013 at 11:03:26AM +0300, Lubomir Popov wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote: > From: Balaji T K balajitk@ti.com > > add dra mmc pbias support and ldo1 power on > > Signed-off-by: Balaji T K balajitk@ti.com > Signed-off-by: Lokesh Vutla lokeshvutla@ti.com > --- > arch/arm/include/asm/arch-omap5/omap.h | 3 ++- > drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ > drivers/power/palmas.c | 25 ++++++++++++++++++++++++- > include/configs/omap5_common.h | 4 ++++ > include/configs/omap5_uevm.h | 5 ----- > include/palmas.h | 6 +++++- > 6 files changed, 49 insertions(+), 20 deletions(-) >
[snip]
> + /* set LDO9 TWL6035 to 3V */ LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
> + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
OK, lets see. That so lets keep your patch as-is, since we've now got -ffunction-sections/-fdata-sections/--gc-sections on ARM for main U-Boot, these small things won't hurt like they used to.
OK, but then I would like to do some cleanup first - remove the audio power stuff (shall have it in my board file), as well as either sort out the function naming:
- Those functions that are specific to a SoC+PMIC combination are named e.g. twl603x_... or tps659038_... so that they explicitly indicate the hardware that they are working with (actually almost all functions are such). This is however sort of regression, and requires fixes in the files calling these functions;
or, alternatively:
- Introduce generic functions with fixed names, palmas_bla_bla(), sort of wrappers, which in their bodies perform the appropriate action based on the #ifdefs defining the platform hardware (where we could also define the particular LDO which for example a palmas_mmc1_poweron_ldo() generic function would manipulate). Drawback: again #ifdefs. Advantage: single place where this stuff is located, and where other PMIC/LDO combinations can be added without affecting other code. And this generic palmas_mmc1_poweron_ldo() function would be called by another generic function, e.g. omap_sdmmc_poweron(), located in the board file, only if needed by the particular hardware. omap_sdmmc_poweron(), on its hand, is the function that is to be called from within the pbias routines in omap_hsmmc.c, and not the hardware- dependant functions directly. So we get the abstraction.
What do you think? Lokesh, your opinion?
Regards, Lubo
Hi Lubomir, On Thursday 06 June 2013 12:55 PM, Lubomir Popov wrote:
Hi Tom,
On 05/06/13 16:45, Tom Rini wrote:
On Wed, Jun 05, 2013 at 11:03:26AM +0300, Lubomir Popov wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote: > Hi Lokesh, > > On 30/05/13 16:19, Lokesh Vutla wrote: >> From: Balaji T K balajitk@ti.com >> >> add dra mmc pbias support and ldo1 power on >> >> Signed-off-by: Balaji T K balajitk@ti.com >> Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >> --- >> arch/arm/include/asm/arch-omap5/omap.h | 3 ++- >> drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ >> drivers/power/palmas.c | 25 ++++++++++++++++++++++++- >> include/configs/omap5_common.h | 4 ++++ >> include/configs/omap5_uevm.h | 5 ----- >> include/palmas.h | 6 +++++- >> 6 files changed, 49 insertions(+), 20 deletions(-) >>
[snip]
>> + /* set LDO9 TWL6035 to 3V */ > LDO9? TWL6035? If this function is used on the DRA7xx boards only (with > TPS659038), you should add some comment above. Ok ll add the comment. > >> + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ > Why not use definitions for the voltage? You could take them from > http://patchwork.ozlabs.org/patch/244103/ where some values are > defined. Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
OK, lets see. That so lets keep your patch as-is, since we've now got -ffunction-sections/-fdata-sections/--gc-sections on ARM for main U-Boot, these small things won't hurt like they used to.
OK, but then I would like to do some cleanup first - remove the audio power stuff (shall have it in my board file), as well as either sort out the function naming:
- Those functions that are specific to a SoC+PMIC combination are
named e.g. twl603x_... or tps659038_... so that they explicitly indicate the hardware that they are working with (actually almost all functions are such). This is however sort of regression, and requires fixes in the files calling these functions;
or, alternatively:
- Introduce generic functions with fixed names, palmas_bla_bla(),
sort of wrappers, which in their bodies perform the appropriate action based on the #ifdefs defining the platform hardware (where we could also define the particular LDO which for example a palmas_mmc1_poweron_ldo() generic function would manipulate). Drawback: again #ifdefs. Advantage: single place where this stuff is located, and where other PMIC/LDO combinations can be added without affecting other code.
I think, we can have function pointers for and can populate data in the beginning or from board file based on Soc, similarly what we did for prcm structure. Regards, Lokesh
And this generic palmas_mmc1_poweron_ldo() function would be called by another generic function, e.g. omap_sdmmc_poweron(), located in the board file, only if needed by the particular hardware. omap_sdmmc_poweron(), on its hand, is the function that is to be called from within the pbias routines in omap_hsmmc.c, and not the hardware- dependant functions directly. So we get the abstraction.
What do you think? Lokesh, your opinion?
Regards, Lubo
Hi Lokesh,
On 06/06/13 14:26, Lokesh Vutla wrote:
Hi Lubomir, On Thursday 06 June 2013 12:55 PM, Lubomir Popov wrote:
Hi Tom,
On 05/06/13 16:45, Tom Rini wrote:
On Wed, Jun 05, 2013 at 11:03:26AM +0300, Lubomir Popov wrote:
[snip]
OK, lets see. That so lets keep your patch as-is, since we've now got -ffunction-sections/-fdata-sections/--gc-sections on ARM for main U-Boot, these small things won't hurt like they used to.
OK, but then I would like to do some cleanup first - remove the audio power stuff (shall have it in my board file), as well as either sort out the function naming:
- Those functions that are specific to a SoC+PMIC combination are
named e.g. twl603x_... or tps659038_... so that they explicitly indicate the hardware that they are working with (actually almost all functions are such). This is however sort of regression, and requires fixes in the files calling these functions;
or, alternatively:
- Introduce generic functions with fixed names, palmas_bla_bla(),
sort of wrappers, which in their bodies perform the appropriate action based on the #ifdefs defining the platform hardware (where we could also define the particular LDO which for example a palmas_mmc1_poweron_ldo() generic function would manipulate). Drawback: again #ifdefs. Advantage: single place where this stuff is located, and where other PMIC/LDO combinations can be added without affecting other code.
I think, we can have function pointers for and can populate data in the beginning or from board file based on Soc, similarly what we did for prcm structure. Regards, Lokesh
OK, sounds reasonable. I think this should be done in a future release however, after careful investigation and planning. At present, I guess, we are staying with the current situation.
Today I shall submit an updated version of my patch to the palmas driver - sort of compromise between clean code and ease of use. I have included your stuff there, so should work out of the box on the dra7xx_evm. Please note that now we have a semi-generic function to power on the appropriate SDMMC LDO: the old palmas_mmc1_poweron_ldo(), which you shall have to call in omap_hsmmc. Differentiation of which particular LDO to control within which PMIC is done in driver, based on the board #ifdefs.
If Tom approves this patch and applies it, we shall all be happy with working boards, although the code may not be perfect.
I would also like to ask you to send me a Register Manual of the TPS659038/9, if possible. If you have any NDA concerns, then just check if the LDO1 control register has a BYPASS option and tell me. Thanks.
Best regards, Lubo
On Wed, Jun 5, 2013 at 3:03 AM, Lubomir Popov lpopov@mm-sol.com wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote:
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/include/asm/arch-omap5/omap.h | 3 ++- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 6 +++++- 6 files changed, 49 insertions(+), 20 deletions(-)
[snip]
- /* set LDO9 TWL6035 to 3V */
LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
- val = 0x2b; /* (3 - 0.9) * 20 + 1 */
Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
I hate this code for many reasons - a) hsmmc is used on many OMAP and DM platforms to my knowledge. b) what is being done here is to power on the LDO supplying MMC.
The implementation *should* be board specific! not an #ifdef madness which works only on TI platforms.
Regards, Nishanth Menon
Hi Nishanth,
On 05/06/13 17:01, Nishanth Menon wrote:
On Wed, Jun 5, 2013 at 3:03 AM, Lubomir Popov lpopov@mm-sol.com wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote:
Hi Lokesh,
On 30/05/13 16:19, Lokesh Vutla wrote: > From: Balaji T K balajitk@ti.com > > add dra mmc pbias support and ldo1 power on > > Signed-off-by: Balaji T K balajitk@ti.com > Signed-off-by: Lokesh Vutla lokeshvutla@ti.com > --- > arch/arm/include/asm/arch-omap5/omap.h | 3 ++- > drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ > drivers/power/palmas.c | 25 ++++++++++++++++++++++++- > include/configs/omap5_common.h | 4 ++++ > include/configs/omap5_uevm.h | 5 ----- > include/palmas.h | 6 +++++- > 6 files changed, 49 insertions(+), 20 deletions(-) >
[snip]
> + /* set LDO9 TWL6035 to 3V */ LDO9? TWL6035? If this function is used on the DRA7xx boards only (with TPS659038), you should add some comment above.
Ok ll add the comment.
> + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ Why not use definitions for the voltage? You could take them from http://patchwork.ozlabs.org/patch/244103/ where some values are defined.
Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
I hate this code for many reasons - a) hsmmc is used on many OMAP and DM platforms to my knowledge. b) what is being done here is to power on the LDO supplying MMC.
Sorry, but I can't get if hsmmc is discussed here, or power.
For OMAP5+TWL603x the LDO powering MMC (actually the removable card interface only; eMMC is another story) is turned on automatically at power-on by the PMIC sequencer, with a default voltage and mode -- otherwise we would not be able to boot from a card (ROM code does not touch the PMIC at all). We are talking here about the possibility to have additional control over this LDO, which should be board-specific, I agree. On the OMAP5 boards, for example, the call to palmas_mmc1_poweron_ldo() from within omap_hsmmc actually does not turn on LDO9 - it is on at this moment anyway. The call just makes it switch from the default bypass mode (with Vout = Vin = 3.3 V) to regulation mode and Vout = 3.0 V. Why is this done is yet another question; to me it seems useless (and possibly wrong) when the card is powered with a fixed voltage of 3.3 V. Therefore it seems reasonable to count on the PMIC defaults and remove this call from omap_hsmmc altogether, thus disengaging the PMIC driver from hsmmc, at least for OMAP5.
For OMAP4 things are somewhat different. Here the TWL6030 PMIC powers both the OMAP interface and the card socket, and in addition can automatically power off the MMC LDO upon detecting card removal. ROM code *does* access the MMC LDO to turn it on and set it to 3.0 V (it starts by default at 1.8 V), but only if booting from a card. So here the call to PMIC driver should stay.
Other OMAPs and derivatives - other scenarios.
Anyway, omap_hsmmc.c is built for TI platforms only. If you mean the #ifdefs here, yes, things could be cleaned up by moving the SoC- specific pbias stuff to the corresponding board files (with the expense of redundancy), but this is quite an amount of work... I'm not volunteering... ;) Moreover, this particular patch is not mine.
The implementation *should* be board specific! not an #ifdef madness which works only on TI platforms.
Regards, Nishanth Menon
Best regards, Lubo
On Wed, Jun 5, 2013 at 11:35 AM, Lubomir Popov lpopov@mm-sol.com wrote:
Hi Nishanth,
On 05/06/13 17:01, Nishanth Menon wrote:
On Wed, Jun 5, 2013 at 3:03 AM, Lubomir Popov lpopov@mm-sol.com wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
Hi Lubomir, On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote: > Hi Lokesh, > > On 30/05/13 16:19, Lokesh Vutla wrote: >> From: Balaji T K balajitk@ti.com >> >> add dra mmc pbias support and ldo1 power on >> >> Signed-off-by: Balaji T K balajitk@ti.com >> Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >> --- >> arch/arm/include/asm/arch-omap5/omap.h | 3 ++- >> drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ >> drivers/power/palmas.c | 25 ++++++++++++++++++++++++- >> include/configs/omap5_common.h | 4 ++++ >> include/configs/omap5_uevm.h | 5 ----- >> include/palmas.h | 6 +++++- >> 6 files changed, 49 insertions(+), 20 deletions(-) >>
[snip]
>> + /* set LDO9 TWL6035 to 3V */ > LDO9? TWL6035? If this function is used on the DRA7xx boards only (with > TPS659038), you should add some comment above. Ok ll add the comment. > >> + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ > Why not use definitions for the voltage? You could take them from > http://patchwork.ozlabs.org/patch/244103/ where some values are > defined. Yes, Ill rebase this patch on top of your patch and use those defines.
Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
I hate this code for many reasons - a) hsmmc is used on many OMAP and DM platforms to my knowledge. b) what is being done here is to power on the LDO supplying MMC.
Sorry, but I can't get if hsmmc is discussed here, or power.
For OMAP5+TWL603x the LDO powering MMC (actually the removable card interface only; eMMC is another story) is turned on automatically at power-on by the PMIC sequencer, with a default voltage and mode -- otherwise we would not be able to boot from a card (ROM code does not touch the PMIC at all). We are talking here about the possibility to have additional control over this LDO, which should be board-specific, I agree. On the OMAP5 boards, for example, the call to palmas_mmc1_poweron_ldo() from within omap_hsmmc actually does not turn on LDO9 - it is on at this moment anyway. The call just makes it switch from the default bypass mode (with Vout = Vin = 3.3 V) to regulation mode and Vout = 3.0 V. Why is this done is yet another question; to me it seems useless (and possibly wrong) when the card is powered with a fixed voltage of 3.3 V. Therefore it seems reasonable to count on the PMIC defaults and remove this call from omap_hsmmc altogether, thus disengaging the PMIC driver from hsmmc, at least for OMAP5.
For OMAP4 things are somewhat different. Here the TWL6030 PMIC powers both the OMAP interface and the card socket, and in addition can automatically power off the MMC LDO upon detecting card removal. ROM code *does* access the MMC LDO to turn it on and set it to 3.0 V (it starts by default at 1.8 V), but only if booting from a card. So here the call to PMIC driver should stay.
Other OMAPs and derivatives - other scenarios.
Anyway, omap_hsmmc.c is built for TI platforms only. If you mean the #ifdefs here, yes, things could be cleaned up by moving the SoC- specific pbias stuff to the corresponding board files (with the expense of redundancy), but this is quite an amount of work... I'm not volunteering... ;) Moreover, this particular patch is not mine.
I understand approximately why we do this, but there are more than a single MMC on OMAP, in general. and different platforms use different PMICs I am just looking at http://patchwork.ozlabs.org/patch/248928/ and I am like - wait a minute, how many #ifdef #else is one going to add per MMC/board? switching on LDOx meant for MMC1 will work for MMC2? makes no sense to me. is'nt better for struct mmc to have a function pointer which is populated by the board(depending on PMIC) to setup voltage necessary?
the trouble I have is not that omap_hsmmc is meant for TI SoCs. I get that. but the fact that the code is starting to look so convoluted that it will ONLY work on TI boards!!! I dont get that!
Regards, Nishanth Menon
Hi Nishanth,
On Wed, Jun 5, 2013 at 11:35 AM, Lubomir Popov lpopov@mm-sol.com wrote:
Hi Nishanth,
On 05/06/13 17:01, Nishanth Menon wrote:
On Wed, Jun 5, 2013 at 3:03 AM, Lubomir Popov lpopov@mm-sol.com wrote:
Hi Tom,
On 05/06/13 00:06, Tom Rini wrote:
On Mon, Jun 03, 2013 at 10:58:27PM +0300, Lubomir Popov wrote:
Hi Lokesh,
> Hi Lubomir, > On Thursday 30 May 2013 07:56 PM, Lubomir Popov wrote: >> Hi Lokesh, >> >> On 30/05/13 16:19, Lokesh Vutla wrote: >>> From: Balaji T K balajitk@ti.com >>> >>> add dra mmc pbias support and ldo1 power on >>> >>> Signed-off-by: Balaji T K balajitk@ti.com >>> Signed-off-by: Lokesh Vutla lokeshvutla@ti.com >>> --- >>> arch/arm/include/asm/arch-omap5/omap.h | 3 ++- >>> drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ >>> drivers/power/palmas.c | 25 ++++++++++++++++++++++++- >>> include/configs/omap5_common.h | 4 ++++ >>> include/configs/omap5_uevm.h | 5 ----- >>> include/palmas.h | 6 +++++- >>> 6 files changed, 49 insertions(+), 20 deletions(-) >>> [snip] >>> + /* set LDO9 TWL6035 to 3V */ >> LDO9? TWL6035? If this function is used on the DRA7xx boards only (with >> TPS659038), you should add some comment above. > Ok ll add the comment. >> >>> + val = 0x2b; /* (3 - 0.9) * 20 + 1 */ >> Why not use definitions for the voltage? You could take them from >> http://patchwork.ozlabs.org/patch/244103/ where some values are >> defined. > Yes, Ill rebase this patch on top of your patch and use those defines. Please be aware that my above mentioned patch has not been reviewed/ tested/acked/nacked/whatever by nobody (except possibly a quick look by Nishanth Menon, who had some objections). I wrote it when bringing up a custom OMAP5 board, and most probably it shall not go into mainline in its current form, if ever. I gave it only as an example of how things could be done cleaner. Feel free to use the code as you wish, but I'm afraid that applying it as a patch to your tree and basing upon it might run you into problems when you later sync with mainline.
Tom, your opinion?
OK, so at the time it was "nothing will really use this code except test functions". Looks like we have a use for mmc1_ldo9 code at least, so lets rework the first patch for adding that + cleanups wrt constants.
Well, I'm not quite sure that this LDO9 function would be the only one used (or LDO1 on the DRA7xx board). Judging from omapboot for the OMAP5 boards for example, SMPS7 (it delivers the common 1.8 V I/O supply) is set to 'Forced PWM' mode in order to reduce board noise - there sure has been a reason to do so and sacrifice converter efficiency. Therefore I added similar functionality in my patch to the Palmas driver (and am explicitly calling it in my board init). The option to bypass LDO9 on OMAP5+TWL603x boards seems quite mandatory as well, if hardware is designed such that the SD card socket has a separate fixed 3.3 V supply which also powers the LDO9 input (the uEVM for example). On the DRA7xx+TPS659038 board the power scheme is different and this does not apply.
I hate this code for many reasons - a) hsmmc is used on many OMAP and DM platforms to my knowledge. b) what is being done here is to power on the LDO supplying MMC.
Sorry, but I can't get if hsmmc is discussed here, or power.
For OMAP5+TWL603x the LDO powering MMC (actually the removable card interface only; eMMC is another story) is turned on automatically at power-on by the PMIC sequencer, with a default voltage and mode -- otherwise we would not be able to boot from a card (ROM code does not touch the PMIC at all). We are talking here about the possibility to have additional control over this LDO, which should be board-specific, I agree. On the OMAP5 boards, for example, the call to palmas_mmc1_poweron_ldo() from within omap_hsmmc actually does not turn on LDO9 - it is on at this moment anyway. The call just makes it switch from the default bypass mode (with Vout = Vin = 3.3 V) to regulation mode and Vout = 3.0 V. Why is this done is yet another question; to me it seems useless (and possibly wrong) when the card is powered with a fixed voltage of 3.3 V. Therefore it seems reasonable to count on the PMIC defaults and remove this call from omap_hsmmc altogether, thus disengaging the PMIC driver from hsmmc, at least for OMAP5.
For OMAP4 things are somewhat different. Here the TWL6030 PMIC powers both the OMAP interface and the card socket, and in addition can automatically power off the MMC LDO upon detecting card removal. ROM code *does* access the MMC LDO to turn it on and set it to 3.0 V (it starts by default at 1.8 V), but only if booting from a card. So here the call to PMIC driver should stay.
Other OMAPs and derivatives - other scenarios.
Anyway, omap_hsmmc.c is built for TI platforms only. If you mean the #ifdefs here, yes, things could be cleaned up by moving the SoC- specific pbias stuff to the corresponding board files (with the expense of redundancy), but this is quite an amount of work... I'm not volunteering... ;) Moreover, this particular patch is not mine.
I understand approximately why we do this, but there are more than a single MMC on OMAP, in general. and different platforms use different PMICs I am just looking at http://patchwork.ozlabs.org/patch/248928/ and I am like - wait a minute, how many #ifdef #else is one going to add per MMC/board? switching on LDOx meant for MMC1 will work for MMC2? makes no sense to me.
Not quite so. The main goal in U-Boot is to guarantee proper setup (even if power is provided prior automatically by the PMIC, or by pure iron hardware) of the interface to the MMC channel connecting removable media, which therefore must, by spec, support dual-voltage signalling. Usually (and for the TI SoCs known to me, actually) we have only one such dedicated channel, which is specific in respect to internal silicon implementation of the interface: all that pbias stuff exists here only, and requires some special setup. If we are using a matching TI PMIC, we have also a dedicated LDO to power this interface. The other MMC channels are not a concern here and should not be messed with; they may have dedicated LDOs or may have not (TI PMICs, for example, power on a eMMC automatically, and even have a pin-configurable option to select the default eMMC core voltage).
is'nt better for struct mmc to have a function pointer which is populated by the board(depending on PMIC) to setup voltage necessary?
Anyway U-Boot, at the hsmmc driver level, assumes that if we are using a MMC channel, it is operational, that is, powered on, and does not care how this is achieved. I don't think it is reasonable to alter the mmc struct.
What could be more appropriate is perhaps to define a generic omap_sdmmc_poweron() function that is called from within the pbias setup routines for each SoC (can't avoid the #ifdefs here, I'm afraid), which is to be implemented in the board files as required by the particular platforms; could be empty if nothing has to be done in software, or call the existing PMIC functions (palmas_mmc1_poweron_ldo or whatever) for TI boards.
the trouble I have is not that omap_hsmmc is meant for TI SoCs. I get that. but the fact that the code is starting to look so convoluted that it will ONLY work on TI boards!!! I dont get that!
Regards, Nishanth Menon
Best regards, Lubo
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- Changes since V2: * Addressed comments from lpopov@mm-sol.com * Rebased on top of http://patchwork.ozlabs.org/patch/244103/ arch/arm/include/asm/arch-omap5/omap.h | 2 +- drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++------------ drivers/power/palmas.c | 25 ++++++++++++++++++++++++- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 8 +++++++- 6 files changed, 50 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 8105c14..1076494 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -106,9 +106,9 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 << 27) #define SDCARD_PWRDNZ (1 << 26) #define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_BIAS_PWRDNZ (1 << 22) #define SDCARD_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__ diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afdfa88..3d3281e 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc) u32 value = 0;
value = readl((*ctrl)->control_pbias); - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; + value &= ~SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(10); /* wait 10 us */ + value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias);
- palmas_mmc1_poweron_ldo(); +#if defined(CONFIG_DRA7XX) + tps659038_mmc1_poweron_ldo1(); +#else + palmas_mmc1_poweron_ldo9(); +#endif
value = readl((*ctrl)->control_pbias); - value &= ~SDCARD_BIAS_HIZ_MODE; - value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; + value |= SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); - - value = readl((*ctrl)->control_pbias); - if (value & (1 << 23)) { - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; - writel(value, (*ctrl)->control_pbias); - } + udelay(150); /* wait 150 us */ + value |= SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(150); /* wait 150 us */ } #endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 1f9bd7e..b94ed5d 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -37,7 +37,7 @@ void palmas_init_settings(void) #endif }
-int palmas_mmc1_poweron_ldo(void) +int palmas_mmc1_poweron_ldo9(void) { u8 val = 0;
@@ -56,6 +56,29 @@ int palmas_mmc1_poweron_ldo(void) return 0; }
+int tps659038_mmc1_poweron_ldo1(void) +{ + u8 val = 0; + + /* set LDO1 to 3V */ + val = LDO_VOLT_3V0; + + if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_VOLTAGE, val)) { + printf("tps659038: could not set LDO1 voltage\n"); + return 1; + } + + /* TURN ON LDO1 */ + val = RSC_MODE_SLEEP | RSC_MODE_ACTIVE; + + if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_CTRL, val)) { + printf("tps659038: could not turn on LDO1\n"); + return 1; + } + + return 0; +} + /* * On some hardware the SD card socket and LDO9_IN are powered by an * external 3.3 V regulator, while the output of LDO9 delivers VDDS_SDCARD diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 83b91d1..ddf2ad4 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -238,6 +238,10 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index ba81e30..f4a2d31 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -39,11 +39,6 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200
-/* TWL6035 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif - /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ diff --git a/include/palmas.h b/include/palmas.h index 7becb97..2355801 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -30,9 +30,14 @@ #define PALMAS_CHIP_P1 0x48 /* Page 1 */ #define PALMAS_CHIP_P2 0x49 /* Page 2 */ #define PALMAS_CHIP_P3 0x4a /* Page 3 */ +#define TPS659038_CHIP_P1 0x58 /* Page 1 */
/* Page 1 registers (0x1XY translates to page 1, reg addr 0xXY): */
+/* LDO1_CTRL */ +#define LDO1_CTRL 0x50 +#define LDO1_VOLTAGE 0x51 + /* LDO9_CTRL */ #define LDO9_CTRL 0x60 #define LDO9_VOLTAGE 0x61 @@ -119,7 +124,8 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) }
void palmas_init_settings(void); -int palmas_mmc1_poweron_ldo(void); +int palmas_mmc1_poweron_ldo9(void); +int tps659038_mmc1_poweron_ldo1(void); int palmas_mmc1_set_ldo9(u8 vsel); int palmas_audio_power(u8 on); int palmas_enable_bb_charge(u8 bb_fields);
From: Balaji T K balajitk@ti.com
add dra mmc pbias support and ldo1 power on
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- Changes since V3: * Addressed comments from Tom
arch/arm/include/asm/arch-omap5/omap.h | 2 +- drivers/mmc/omap_hsmmc.c | 26 +++++++++++----------- drivers/power/palmas.c | 37 ++++++++++++++++++++++++++------ include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- include/palmas.h | 12 +++++++++-- 6 files changed, 59 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 9010666..abf6837 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -106,9 +106,9 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 << 27) #define SDCARD_PWRDNZ (1 << 26) #define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_BIAS_PWRDNZ (1 << 22) #define SDCARD_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__ diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afdfa88..3d3281e 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -113,23 +113,25 @@ static void omap5_pbias_config(struct mmc *mmc) u32 value = 0;
value = readl((*ctrl)->control_pbias); - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; + value &= ~SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(10); /* wait 10 us */ + value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias);
- palmas_mmc1_poweron_ldo(); +#if defined(CONFIG_DRA7XX) + tps659038_mmc1_poweron_ldo1(); +#else + palmas_mmc1_poweron_ldo9(); +#endif
value = readl((*ctrl)->control_pbias); - value &= ~SDCARD_BIAS_HIZ_MODE; - value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; + value |= SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); - - value = readl((*ctrl)->control_pbias); - if (value & (1 << 23)) { - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; - writel(value, (*ctrl)->control_pbias); - } + udelay(150); /* wait 150 us */ + value |= SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(150); /* wait 150 us */ } #endif
diff --git a/drivers/power/palmas.c b/drivers/power/palmas.c index 09c832d..71c4bdc 100644 --- a/drivers/power/palmas.c +++ b/drivers/power/palmas.c @@ -28,23 +28,46 @@ void palmas_init_settings(void) return; }
-int palmas_mmc1_poweron_ldo(void) +int palmas_mmc1_poweron_ldo9(void) { u8 val = 0;
/* set LDO9 TWL6035 to 3V */ - val = 0x2b; /* (3 -.9)*28 +1 */ + val = LDO_VOLT_3V0;
- if (palmas_i2c_write_u8(0x48, LDO9_VOLTAGE, val)) { - printf("twl6035: could not set LDO9 voltage.\n"); + if (palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_VOLTAGE, val)) { + printf("twl603x: could not set LDO9 voltage.\n"); return 1; }
/* TURN ON LDO9 */ - val = LDO_ON | LDO_MODE_SLEEP | LDO_MODE_ACTIVE; + val = LDO_MODE_SLEEP | LDO_MODE_ACTIVE;
- if (palmas_i2c_write_u8(0x48, LDO9_CTRL, val)) { - printf("twl6035: could not turn on LDO9.\n"); + if (palmas_i2c_write_u8(TWL603X_CHIP_P1, LDO9_CTRL, val)) { + printf("twl603x: could not turn on LDO9.\n"); + return 1; + } + + return 0; +} + +int tps659038_mmc1_poweron_ldo1(void) +{ + u8 val = 0; + + /* set LDO1 to 3V */ + val = LDO_VOLT_3V0; + + if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_VOLTAGE, val)) { + printf("tps659038: could not set LDO1 voltage\n"); + return 1; + } + + /* TURN ON LDO1 */ + val = LDO_MODE_SLEEP | LDO_MODE_ACTIVE; + + if (palmas_i2c_write_u8(TPS659038_CHIP_P1, LDO1_CTRL, val)) { + printf("tps659038: could not turn on LDO1\n"); return 1; }
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 83b91d1..ddf2ad4 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -238,6 +238,10 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index ba81e30..f4a2d31 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -39,11 +39,6 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200
-/* TWL6035 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif - /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ diff --git a/include/palmas.h b/include/palmas.h index 3b18589..0361705 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -27,7 +27,12 @@ #include <i2c.h>
/* I2C chip addresses */ -#define PALMAS_CHIP_ADDR 0x48 +#define TWL603X_CHIP_P1 0x48 /* Page 1 */ +#define TPS659038_CHIP_P1 0x58 /* Page 1 */ + +/* LDO1_CTRL */ +#define LDO1_CTRL 0x50 +#define LDO1_VOLTAGE 0x51
/* 0x1XY translates to page 1, register address 0xXY */ #define LDO9_CTRL 0x60 @@ -38,6 +43,8 @@ #define LDO_MODE_SLEEP (1 << 2) #define LDO_MODE_ACTIVE (1 << 0)
+/* LDO Volatge */ +#define LDO_VOLT_3V0 0x2b /* * Functions to read and write from TPS659038/TWL6035/TWL6037 * or other Palmas family of TI PMICs @@ -53,6 +60,7 @@ static inline int palmas_i2c_read_u8(u8 chip_no, u8 reg, u8 *val) }
void palmas_init_settings(void); -int palmas_mmc1_poweron_ldo(void); +int palmas_mmc1_poweron_ldo9(void); +int tps659038_mmc1_poweron_ldo1(void);
#endif /* PALMAS_H */
From: Balaji T K balajitk@ti.com
Update pbias programming sequence for OMAP5 ES2.0/DRA7
Signed-off-by: Balaji T K balajitk@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- Changes since V4: * Rebased on top of http://patchwork.ozlabs.org/patch/249430/
arch/arm/include/asm/arch-omap5/omap.h | 2 +- drivers/mmc/omap_hsmmc.c | 20 +++++++++----------- include/configs/omap5_common.h | 4 ++++ include/configs/omap5_uevm.h | 5 ----- 4 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 9010666..abf6837 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -106,9 +106,9 @@ /* CONTROL_EFUSE_2 */ #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
+#define SDCARD_BIAS_PWRDNZ (1 << 27) #define SDCARD_PWRDNZ (1 << 26) #define SDCARD_BIAS_HIZ_MODE (1 << 25) -#define SDCARD_BIAS_PWRDNZ (1 << 22) #define SDCARD_PBIASLITE_VMODE (1 << 21)
#ifndef __ASSEMBLY__ diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index afdfa88..975b2c5 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -113,23 +113,21 @@ static void omap5_pbias_config(struct mmc *mmc) u32 value = 0;
value = readl((*ctrl)->control_pbias); - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; + value &= ~SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(10); /* wait 10 us */ + value &= ~SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias);
palmas_mmc1_poweron_ldo();
value = readl((*ctrl)->control_pbias); - value &= ~SDCARD_BIAS_HIZ_MODE; - value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ; + value |= SDCARD_BIAS_PWRDNZ; writel(value, (*ctrl)->control_pbias); - - value = readl((*ctrl)->control_pbias); - if (value & (1 << 23)) { - value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ); - value |= SDCARD_BIAS_HIZ_MODE; - writel(value, (*ctrl)->control_pbias); - } + udelay(150); /* wait 150 us */ + value |= SDCARD_PWRDNZ; + writel(value, (*ctrl)->control_pbias); + udelay(150); /* wait 150 us */ } #endif
diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 83b91d1..ddf2ad4 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -238,6 +238,10 @@ #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS #endif
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_PALMAS_POWER +#endif + /* Defines for SPL */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index ba81e30..f4a2d31 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -39,11 +39,6 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200
-/* TWL6035 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PALMAS_POWER -#endif - /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
Updating pinmux data as specified in the latest DM
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Balaji T K balajitk@ti.com --- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 7 +++-- board/ti/dra7xx/mux_data.h | 38 ++++++++++++++++---------- 2 files changed, 29 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index 55e9de6..5f2b0f9 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -28,11 +28,14 @@
#include <asm/types.h>
+#define FSC (1 << 19) +#define SSC (0 << 19) + #define IEN (1 << 18) #define IDIS (0 << 18)
-#define PTU (3 << 16) -#define PTD (1 << 16) +#define PTU (1 << 17) +#define PTD (0 << 17) #define PEN (1 << 16) #define PDIS (0 << 16)
diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h index 04c95fd..338a241 100644 --- a/board/ti/dra7xx/mux_data.h +++ b/board/ti/dra7xx/mux_data.h @@ -29,19 +29,29 @@ #include <asm/arch/mux_dra7xx.h>
const struct pad_conf_entry core_padconf_array_essential[] = { - {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */ - {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */ - {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */ - {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */ - {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */ - {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */ - {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */ - {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */ - {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */ - {UART1_TXD, (M0)}, /* UART1_TXD */ - {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */ - {UART1_RTSN, (M0)}, /* UART1_RTSN */ - {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */ - {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */ + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ + {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ + {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ + {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ + {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ }; #endif /* _MUX_DATA_DRA7XX_H_ */
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Sricharan R r.sricharan@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 16 ++--- arch/arm/cpu/armv7/omap5/hw_data.c | 87 +++++++++++++++--------- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/include/asm/arch-omap4/clock.h | 2 +- arch/arm/include/asm/arch-omap5/clock.h | 8 ++- arch/arm/include/asm/omap_common.h | 3 +- include/configs/dra7xx_evm.h | 2 + 7 files changed, 73 insertions(+), 46 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 64fffd3..2e5a01e 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -50,13 +50,12 @@
const u32 sys_clk_array[8] = { 12000000, /* 12 MHz */ - 13000000, /* 13 MHz */ + 20000000, /* 20 MHz */ 16800000, /* 16.8 MHz */ 19200000, /* 19.2 MHz */ 26000000, /* 26 MHz */ 27000000, /* 27 MHz */ 38400000, /* 38.4 MHz */ - 20000000, /* 20 MHz */ };
static inline u32 __get_sys_clk_index(void) @@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void) /* SYS_CLKSEL - 1 to match the dpll param array indices */ ind = (readl((*prcm)->cm_sys_clksel) & CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; - /* - * SYS_CLKSEL value for 20MHz is 0. This is introduced newly - * in DRA7XX socs. SYS_CLKSEL -1 will be greater than - * NUM_SYS_CLK. So considering the last 3 bits as the index - * for the dpll param array. - */ - ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK; } return ind; } @@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void) params = get_abe_dpll_params(*dplls_data); #ifdef CONFIG_SYS_OMAP_ABE_SYSCK abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; + + if (omap_revision() == DRA752_ES1_0) + /* Select the sys clk for dpll_abe */ + clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel, + CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK, + CM_ABE_PLL_SYS_CLKSEL_SYSCLK2); #else abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index bddcaed..44552c3 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -100,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { };
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { - {250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ + {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ };
static const struct dpll_params @@ -133,15 +132,14 @@ static const struct dpll_params };
static const struct dpll_params - core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = { - {266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */ - {277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */ - {368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */ + core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { + {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ + {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ + {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ + {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ + {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */ - {266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */ + {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ };
static const struct dpll_params @@ -187,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { };
static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { - {32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ + {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */ + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ + {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ - {96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */ + {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */ };
static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { @@ -207,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };
+static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { + {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + /* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { @@ -224,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = { 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 };
+/* ABE M & N values with sysclk2(22.5792 MHz) as input */ +static const struct dpll_params + abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ +}; + static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ };
-static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = { - {533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ +static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { + {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ + {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ - {533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */ + {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ };
struct dplls omap5_dplls_es1 = { @@ -276,10 +293,12 @@ struct dplls omap5_dplls_es2 = {
struct dplls dra7xx_dplls = { .mpu = mpu_dpll_params_1ghz, - .core = core_dpll_params_2128mhz_ddr532_dra7xx, + .core = core_dpll_params_2128mhz_dra7xx, .per = per_dpll_params_768mhz_dra7xx, + .abe = abe_dpll_params_sysclk2_361267khz, + .iva = iva_dpll_params_2330mhz_dra7xx, .usb = usb_dpll_params_1920mhz, - .ddr = ddr_dpll_params_1066mhz, + .ddr = ddr_dpll_params_2128mhz, };
struct pmic_data palmas = { diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index db779f2..fdf204f 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -943,6 +943,7 @@ struct prcm_regs const dra7xx_prcm = { /* l4 wkup regs */ .cm_abe_pll_ref_clksel = 0x4ae0610c, .cm_sys_clksel = 0x4ae06110, + .cm_abe_pll_sys_clksel = 0x4ae06118, .cm_wkup_clkstctrl = 0x4ae07800, .cm_wkup_l4wkup_clkctrl = 0x4ae07820, .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index d7b61c2..d14d8fb 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -76,7 +76,7 @@ #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 86d4711..1affa4f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -81,7 +81,7 @@ #define CM_CLKSEL_DCC_EN_MASK (1 << 22)
/* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 @@ -98,6 +98,12 @@ #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
+/* CM_CLKSEL_ABE_PLL_SYS */ +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0 +#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0 +#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1 + /* CM_BYPCLK_DPLL_IVA */ #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 7007177..86ddd65 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -29,7 +29,7 @@
#include <common.h>
-#define NUM_SYS_CLKS 8 +#define NUM_SYS_CLKS 7
struct prcm_regs { /* cm1.ckgen */ @@ -301,6 +301,7 @@ struct prcm_regs { /* l4 wkup regs */ u32 cm_abe_pll_ref_clksel; u32 cm_sys_clksel; + u32 cm_abe_pll_sys_clksel; u32 cm_wkup_clkstctrl; u32 cm_wkup_l4wkup_clkctrl; u32 cm_wkup_wdtimer1_clkctrl; diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 35dec08..0eea28c 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -39,4 +39,6 @@ #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 UART1_BASE #define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_OMAP_ABE_SYSCK #endif /* __CONFIG_DRA7XX_EVM_H */
From: Sricharan R r.sricharan@ti.com
DRA7 EVM board has the below configuration. Adding the settings for the same here.
2Gb_1_35V_DDR3L part * 2 on EMIF1 2Gb_1_35V_DDR3L part * 4 on EMIF2
Signed-off-by: Sricharan R r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap5/hw_data.c | 21 +++- arch/arm/cpu/armv7/omap5/hwinit.c | 19 +-- arch/arm/cpu/armv7/omap5/prcm-regs.c | 1 + arch/arm/cpu/armv7/omap5/sdram.c | 170 ++++++++++++++++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 1 + arch/arm/include/asm/emif.h | 12 +- arch/arm/include/asm/omap_common.h | 1 + 8 files changed, 220 insertions(+), 31 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 8823967..652e5a7 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -209,7 +209,8 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() >= OMAP5430_ES1_0) { + if ((omap_revision() >= OMAP5430_ES1_0) || + (omap_revision() == DRA752_ES1_0)) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -263,6 +264,18 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs) __udelay(130); }
+static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + config_data_eye_leveling_samples(base); + + writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); + writel(regs->sdram_config, &emif->emif_sdram_config); +} + static void ddr3_init(u32 base, const struct emif_regs *regs) { struct emif_reg_struct *emif = (struct emif_reg_struct *)base; @@ -273,6 +286,7 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) * defined, contents of mode Registers must be fully initialized. * H/W takes care of this initialization */ + writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); @@ -290,7 +304,10 @@ static void ddr3_init(u32 base, const struct emif_regs *regs) /* enable leveling */ writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
- ddr3_leveling(base, regs); + if (omap_revision() == DRA752_ES1_0) + ddr3_sw_leveling(base, regs); + else + ddr3_leveling(base, regs); }
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS @@ -1078,7 +1095,10 @@ static void do_sdram_init(u32 base) if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) { set_lpmode_selfrefresh(base); emif_reset_phy(base); - ddr3_leveling(base, regs); + if (omap_revision() == DRA752_ES1_0) + ddr3_sw_leveling(base, regs); + else + ddr3_leveling(base, regs); }
/* Write to the shadow registers */ diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 44552c3..56cf1f8 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -602,6 +602,17 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = { .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, };
+const struct ctrl_ioregs ioregs_dra7xx_es1 = { + .ctrl_ddrch = 0x40404040, + .ctrl_lpddr2ch = 0x40404040, + .ctrl_ddr3ch = 0x80808080, + .ctrl_ddrio_0 = 0xbae8c631, + .ctrl_ddrio_1 = 0xb46318d8, + .ctrl_ddrio_2 = 0x84210000, + .ctrl_emif_sdram_config_ext = 0xb2c00000, + .ctrl_ddr_ctrl_ext_0 = 0xA2000000, +}; + void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -644,14 +655,16 @@ void get_ioregs(const struct ctrl_ioregs **regs) case OMAP5430_ES1_0: case OMAP5430_ES2_0: *regs = &ioregs_omap5430; - break; + break; case OMAP5432_ES1_0: *regs = &ioregs_omap5432_es1; - break; + break; case OMAP5432_ES2_0: - case DRA752_ES1_0: *regs = &ioregs_omap5432_es2; - break; + break; + case DRA752_ES1_0: + *regs = &ioregs_dra7xx_es1; + break;
default: printf("\n INVALID OMAP REVISION "); diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 40dbf45..daf124e 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -100,16 +100,21 @@ static void io_settings_ddr3(void) writel(ioregs->ctrl_emif_sdram_config_ext, (*ctrl)->control_emif2_sdram_config_ext);
- /* Disable DLL select */ - io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) + if (is_omap54xx()) { + /* Disable DLL select */ + io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif1_sdram_config); + writel(io_settings, + (*ctrl)->control_port_emif1_sdram_config);
- io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) + io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) & 0xFFEFFFFF); - writel(io_settings, - (*ctrl)->control_port_emif2_sdram_config); + writel(io_settings, + (*ctrl)->control_port_emif2_sdram_config); + } else { + writel(ioregs->ctrl_ddr_ctrl_ext_0, + (*ctrl)->control_ddr_control_ext_0); + } }
/* diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index fdf204f..331117c 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -436,6 +436,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_srcomp_east_side = 0x4A002E7C, .control_srcomp_west_side = 0x4A002E80, .control_srcomp_code_latch = 0x4A002E84, + .control_ddr_control_ext_0 = 0x4A002E88, .control_padconf_core_base = 0x4A003400, .control_port_emif1_sdram_config = 0x4AE0C110, .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 6b461e4..1b445a6 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -108,6 +108,7 @@ const struct emif_regs emif_regs_266_mhz_2cs = { const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, @@ -131,6 +132,7 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .sdram_config_init = 0x61851B32, .sdram_config = 0x61851B32, + .sdram_config2 = 0x0, .ref_ctrl = 0x00001035, .sdram_tim1 = 0xCCCF36B3, .sdram_tim2 = 0x308F7FDA, @@ -151,6 +153,54 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { .emif_rd_wr_exec_thresh = 0x40000305 };
+const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851ab2, + .sdram_config = 0x61851ab2, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0E20400A, + .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_3 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_4 = 0x009E009E, + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + +const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .sdram_config2 = 0x08000000, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020400A, + .emif_ddr_phy_ctlr_1 = 0x0E24400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_3 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_4 = 0x009D009D, + .emif_ddr_ext_phy_ctrl_5 = 0x009D009D, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -159,11 +209,39 @@ const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .is_ma_present = 0x1 };
-const struct dmm_lisa_map_regs lisa_map_512M_x_1 = { +/* + * DRA752 EVM board has 1.5 GB of memory + * EMIF1 --> 2Gb * 2 = 512MB + * EMIF2 --> 2Gb * 4 = 1GB + * so mapping 1GB interleaved and 512MB non-interleaved + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x80640300, + .dmm_lisa_map_2 = 0xC0500220, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +/* + * DRA752 EVM EMIF1 ONLY CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, - .dmm_lisa_map_2 = 0x0, - .dmm_lisa_map_3 = 0x80500100, + .dmm_lisa_map_2 = 0x80500100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + +/* + * DRA752 EVM EMIF2 ONLY CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600200, + .dmm_lisa_map_3 = 0xFF020100, .is_ma_present = 0x1 };
@@ -180,9 +258,20 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_532_mhz_2cs_es2; break; case OMAP5432_ES2_0: + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + break; case DRA752_ES1_0: + switch (emif_nr) { + case 1: + *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; + break; + case 2: + *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1; + break; + } + break; default: - *regs = &emif_regs_ddr3_532_mhz_1cs_es2; + *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } }
@@ -201,7 +290,7 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: default: - *dmm_lisa_regs = &lisa_map_512M_x_1; + *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; }
} @@ -252,7 +341,8 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000077 + 0x00000077, + 0x0 };
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -274,7 +364,8 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000057 + 0x00000057, + 0x0 };
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { @@ -296,7 +387,56 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000000, 0x00000000, 0x00000000, - 0x00000057 + 0x00000057, + 0x0 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x009E009E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x002E002E, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x004D004D, + 0x0, + 0x600020, + 0x40010080, + 0x8102040 +}; + +const u32 +dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x009D009D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x002D002D, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x00570057, + 0x0, + 0x600020, + 0x40010080, + 0x8102040 };
const struct lpddr2_mr_regs mr_regs = { @@ -307,7 +447,7 @@ const struct lpddr2_mr_regs mr_regs = { .mr16 = MR16_REF_FULL_ARRAY };
-static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) +static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs) { switch (omap_revision()) { case OMAP5430_ES1_0: @@ -318,7 +458,14 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) *regs = ddr3_ext_phy_ctrl_const_base_es1; break; case OMAP5432_ES2_0: + *regs = ddr3_ext_phy_ctrl_const_base_es2; + break; case DRA752_ES1_0: + if (emif_nr == 1) + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; + else + *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2; + break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2;
@@ -334,9 +481,12 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) { u32 *ext_phy_ctrl_base = 0; u32 *emif_ext_phy_ctrl_base = 0; + u32 emif_nr; const u32 *ext_phy_ctrl_const_regs; u32 i = 0;
+ emif_nr = (base == EMIF1_BASE) ? 1 : 2; + struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); @@ -353,7 +503,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs) * external phy 6-24 registers do not change with * ddr frequency */ - emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs); + emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs); for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 9abb663..4d82ad4 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -209,6 +209,7 @@ struct ctrl_ioregs { u32 ctrl_ddrio_1; u32 ctrl_ddrio_2; u32 ctrl_emif_sdram_config_ext; + u32 ctrl_ddr_ctrl_ext_0; }; #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5f11d7b..1b94a99 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -581,7 +581,7 @@ (0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5 -#define EMIF_EXT_PHY_CTRL_CONST_REG 0x13 +#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */ struct emif_reg_struct { @@ -855,13 +855,10 @@ struct dmm_lisa_map_regs { #define DPD_ENABLE 1
/* Maximum delay before Low Power Modes */ -#ifndef CONFIG_OMAP54XX -#define REG_CS_TIM 0xF -#else #define REG_CS_TIM 0x0 -#endif -#define REG_SR_TIM 0xF -#define REG_PD_TIM 0xF +#define REG_SR_TIM 0x0 +#define REG_PD_TIM 0x0 +
/* EMIF_PWR_MGMT_CTRL register */ #define EMIF_PWR_MGMT_CTRL (\ @@ -1113,6 +1110,7 @@ struct emif_regs { u32 freq; u32 sdram_config_init; u32 sdram_config; + u32 sdram_config2; u32 ref_ctrl; u32 sdram_tim1; u32 sdram_tim2; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 86ddd65..fa28358 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -396,6 +396,7 @@ struct omap_sys_ctrl_regs { u32 control_ddrio_0; u32 control_ddrio_1; u32 control_ddrio_2; + u32 control_ddr_control_ext_0; u32 control_lpddr2io1_0; u32 control_lpddr2io1_1; u32 control_lpddr2io1_2;
Hi Tom, On Thursday 30 May 2013 06:49 PM, Lokesh Vutla wrote:
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt1559...
Do you have any further comments on this series ?
Thanks and regards, Lokesh
Testing: Boot tested on DRA752 ES1.0, OMAP5432 ES2.0, OMAP4460 PANDA Verified MAKEALL for armv7 and omap boards.
Changes from v1:
- Addressed comments from Tom Rini
Balaji T K (1): mmc: omap_hsmmc: add mmc1 pbias, ldo1
Lokesh Vutla (6): ARM: DRA7xx: Add control id code for DRA7xx ARM: DRA7xx: power Add support for tps659038 PMIC ARM: DRA7xx: clocks: Fixing i2c_init for PMIC ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's ARM: DRA7xx: Update pinmux data ARM: DRA7xx: clocks: Update PLL values
Nishanth Menon (1): ARM: OMAP5: DRA7xx: support class 0 optimized voltages
Sricharan R (4): ARM: DRA7xx: Change the Debug UART to UART1 ARM: DRA7xx: Correct the SYS_CLK to 20MHZ ARM: DRA7xx: Correct SRAM END address ARM: DRA7xx: EMIF: Change settings required for EVM board
arch/arm/cpu/armv7/omap-common/clocks-common.c | 86 +++++++++--- arch/arm/cpu/armv7/omap-common/emif-common.c | 26 +++- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 2 - arch/arm/cpu/armv7/omap-common/timer.c | 1 + arch/arm/cpu/armv7/omap5/hw_data.c | 156 ++++++++++++++++------ arch/arm/cpu/armv7/omap5/hwinit.c | 22 ++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 2 + arch/arm/cpu/armv7/omap5/sdram.c | 170 ++++++++++++++++++++++-- arch/arm/include/asm/arch-omap4/clock.h | 6 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/clock.h | 61 ++++++++- arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 7 +- arch/arm/include/asm/arch-omap5/omap.h | 26 ++-- arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/emif.h | 12 +- arch/arm/include/asm/omap_common.h | 26 +++- board/ti/dra7xx/mux_data.h | 38 ++++-- drivers/mmc/omap_hsmmc.c | 26 ++-- drivers/power/palmas.c | 25 +++- include/configs/dra7xx_evm.h | 8 +- include/configs/omap4_common.h | 4 - include/configs/omap5_common.h | 12 +- include/configs/omap5_uevm.h | 7 +- include/palmas.h | 6 +- 24 files changed, 590 insertions(+), 141 deletions(-)
On Thu, Jun 06, 2013 at 04:58:44PM +0530, Lokesh Vutla wrote:
Hi Tom, On Thursday 30 May 2013 06:49 PM, Lokesh Vutla wrote:
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt1559...
Do you have any further comments on this series ?
Sorry, everything looks good, and I think Lubomir's patch for MMC stuff (which means we drop 9/12 here, right?) should settle everything else out.
Hi Tom,
On 06/06/13 16:26, Tom Rini wrote:
On Thu, Jun 06, 2013 at 04:58:44PM +0530, Lokesh Vutla wrote:
Hi Tom, On Thursday 30 May 2013 06:49 PM, Lokesh Vutla wrote:
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt1559...
Do you have any further comments on this series ?
Sorry, everything looks good, and I think Lubomir's patch for MMC stuff (which means we drop 9/12 here, right?) should settle everything else out.
Please be aware that my patch (latest in http://patchwork.ozlabs.org/patch/249405/) fixes the two palmas.* files only, while Lokesh's patch 9/12 affected 6 files in total (including these two).
Lokesh, unfortunately you shall have to repost 9/12 after rebasing over my stuff, if it is applied.
Regards, Lubo
Hi, On Thursday 06 June 2013 07:07 PM, Lubomir Popov wrote:
Hi Tom,
On 06/06/13 16:26, Tom Rini wrote:
On Thu, Jun 06, 2013 at 04:58:44PM +0530, Lokesh Vutla wrote:
Hi Tom, On Thursday 30 May 2013 06:49 PM, Lokesh Vutla wrote:
This series update support for DRA7xx family Socs and the data for DRA752 ES1.0 soc. This is on top of my recent Misc cleanup series: http://u-boot.10912.n7.nabble.com/PATCH-V2-0-4-ARM-OMAP2-Misc-Cleanup-tt1559...
Do you have any further comments on this series ?
Sorry, everything looks good, and I think Lubomir's patch for MMC stuff (which means we drop 9/12 here, right?) should settle everything else out.
Please be aware that my patch (latest in http://patchwork.ozlabs.org/patch/249405/) fixes the two palmas.* files only, while Lokesh's patch 9/12 affected 6 files in total (including these two).
Yes Lubomir, you are correct. The patch 9/12 from Balaji , also includes a programming sequence update for pbias for OMAP5 ES2.0+ Soc's. Ill have that sequence alone and send a patch. Thanks and regards, Lokesh
Lokesh, unfortunately you shall have to repost 9/12 after rebasing over my stuff, if it is applied.
Regards, Lubo
participants (4)
-
Lokesh Vutla -
Lubomir Popov -
Nishanth Menon -
Tom Rini