[PATCH v2 1/5] rockchip: rk3188-cru-common: sync clock dt-binding header from Linux
In order to update the DT for rk3066 and rk3188 sync the clock dt-binding header. This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker jbx6244@gmail.com Reviewed-by: Heiko Stuebner heiko@sntech.de --- include/dt-bindings/clock/rk3188-cru-common.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 1e7931da0c..afad90680f 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner heiko@sntech.de @@ -59,12 +59,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 -#define ACLK_CIF 199 +#define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 +#define ACLK_VEPU 205 +#define ACLK_VDPU 206
/* pclk gates */ #define PCLK_GRF 320 @@ -125,8 +127,12 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 +#define HCLK_CIF1 470 +#define HCLK_VEPU 471 +#define HCLK_VDPU 472 +#define HCLK_HDMI 473
-#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1)
/* soft-reset indices */ #define SRST_MCORE 2
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com ---
Changed V2: add vpu node changed u-boot include --- arch/arm/dts/rk3188-radxarock.dts | 4 + arch/arm/dts/rk3188.dtsi | 1 + arch/arm/dts/rk3xxx-u-boot.dtsi | 35 +++++++ arch/arm/dts/rk3xxx.dtsi | 215 +++++++++++++++++++++++++------------- 4 files changed, 181 insertions(+), 74 deletions(-) create mode 100644 arch/arm/dts/rk3xxx-u-boot.dtsi
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 61367126ba..10527a052d 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -12,6 +12,10 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188";
+ aliases { + mmc0 = &mmc0; + }; + chosen { /* stdout-path = &uart2; */ stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 7bcca6a02d..d872dac174 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3188-cru.h> #include "rk3xxx.dtsi" +#include "rk3xxx-u-boot.dtsi"
/ { compatible = "rockchip,rk3188"; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi new file mode 100644 index 0000000000..581594c35d --- /dev/null +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + noc: syscon@10128000 { + compatible = "rockchip,rk3188-noc", "syscon"; + reg = <0x10128000 0x2000>; + u-boot,dm-spl; + }; + + dmc: dmc@20020000 { + /* unreviewed u-boot-specific binding */ + compatible = "rockchip,rk3188-dmc", "syscon"; + reg = <0x20020000 0x3fc + 0x20040000 0x294>; + clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; + clock-names = "pclk_ddrupctl", "pclk_publ"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmu>; + rockchip,noc = <&noc>; + u-boot,dm-spl; + }; +}; + +&grf { + u-boot,dm-spl; +}; + +&pmu { + u-boot,dm-spl; +}; + +&uart2 { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi index 612ed44bd6..616a828e0c 100644 --- a/arch/arm/dts/rk3xxx.dtsi +++ b/arch/arm/dts/rk3xxx.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner heiko@sntech.de @@ -6,9 +6,12 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" +#include <dt-bindings/soc/rockchip,boot-mode.h>
/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>;
aliases { @@ -18,9 +21,6 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; - mshc0 = &emmc; - mshc1 = &mmc0; - mshc2 = &mmc1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -29,47 +29,6 @@ spi1 = &spi1; };
- amba { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dmac1_s: dma-controller@20018000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20018000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - }; - - dmac1_ns: dma-controller@2001c000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x2001c000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac2: dma-controller@20078000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x20078000 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - arm,pl330-broken-no-flushp; - clocks = <&cru ACLK_DMA2>; - clock-names = "apb_pclk"; - }; - }; - xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -77,7 +36,30 @@ clock-output-names = "xin24m"; };
- L2: l2-cache-controller@10138000 { + gpu: gpu@10090000 { + compatible = "arm,mali-400"; + reg = <0x10090000 0x10000>; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + assigned-clocks = <&cru ACLK_GPU>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_GPU>; + status = "disabled"; + }; + + vpu: video-codec@10104000 { + compatible = "rockchip,rk3066-vpu"; + reg = <0x10104000 0x800>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>, + <&cru ACLK_VEPU>, <&cru HCLK_VEPU>; + clock-names = "aclk_vdpu", "hclk_vdpu", + "aclk_vepu", "hclk_vepu"; + }; + + L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; cache-unified; @@ -92,14 +74,14 @@ global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>; - interrupts = <GIC_PPI 11 0x304>; + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&cru CORE_PERI>; };
local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>; - interrupts = <GIC_PPI 13 0x304>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&cru CORE_PERI>; };
@@ -133,10 +115,44 @@ status = "disabled"; };
- noc: syscon@10128000 { - u-boot,dm-spl; - compatible = "rockchip,rk3188-noc", "syscon"; - reg = <0x10128000 0x2000>; + qos_gpu: qos@1012d000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012d000 0x20>; + }; + + qos_vpu: qos@1012e000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012e000 0x20>; + }; + + qos_lcdc0: qos@1012f000 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f000 0x20>; + }; + + qos_cif0: qos@1012f080 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f080 0x20>; + }; + + qos_ipp: qos@1012f100 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f100 0x20>; + }; + + qos_lcdc1: qos@1012f180 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f180 0x20>; + }; + + qos_cif1: qos@1012f200 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f200 0x20>; + }; + + qos_rga: qos@1012f280 { + compatible = "rockchip,rk3066-qos", "syscon"; + reg = <0x1012f280 0x20>; };
usb_otg: usb@10180000 { @@ -149,7 +165,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>; - g-use-dma; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -184,60 +199,99 @@ status = "disabled"; };
- mmc0: dwmmc@10214000 { + mmc0: mmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; + dmas = <&dmac2 1>; + dma-names = "rx-tx"; fifo-depth = <256>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; status = "disabled"; };
- mmc1: dwmmc@10218000 { + mmc1: mmc@10218000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; + dmas = <&dmac2 3>; + dma-names = "rx-tx"; fifo-depth = <256>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; status = "disabled"; };
- emmc: dwmmc@1021c000 { + emmc: mmc@1021c000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x1021c000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu"; + dmas = <&dmac2 4>; + dma-names = "rx-tx"; fifo-depth = <256>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + nfc: nand-controller@10500000 { + compatible = "rockchip,rk2928-nfc"; + reg = <0x10500000 0x4000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_NANDC0>; + clock-names = "ahb"; status = "disabled"; };
pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; + compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; reg = <0x20004000 0x100>; - u-boot,dm-spl; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x40>; + mode-normal = <BOOT_NORMAL>; + mode-recovery = <BOOT_RECOVERY>; + mode-bootloader = <BOOT_FASTBOOT>; + mode-loader = <BOOT_BL_DOWNLOAD>; + }; };
grf: grf@20008000 { - compatible = "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x20008000 0x200>; - u-boot,dm-spl; };
- dmc: dmc@20020000 { - /* unreviewed u-boot-specific binding */ - compatible = "rockchip,rk3188-dmc", "syscon"; - rockchip,cru = <&cru>; - rockchip,grf = <&grf>; - rockchip,pmu = <&pmu>; - rockchip,noc = <&noc>; - reg = <0x20020000 0x3fc - 0x20040000 0x294>; - clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>; - clock-names = "pclk_ddrupctl", "pclk_publ"; - u-boot,dm-spl; + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; };
i2c0: i2c@2002d000 { @@ -361,7 +415,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <1>; - clock-frequency = <24000000>; clock-names = "baudclk", "apb_pclk"; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; status = "disabled"; @@ -385,6 +438,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; };
@@ -413,4 +468,16 @@ dma-names = "tx", "rx"; status = "disabled"; }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; };
Johan Jonker jbx6244@gmail.com 于2021年6月25日周五 下午9:31写道：
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
Changed V2: add vpu node changed u-boot include
arch/arm/dts/rk3188-radxarock.dts | 4 + arch/arm/dts/rk3188.dtsi | 1 + arch/arm/dts/rk3xxx-u-boot.dtsi | 35 +++++++ arch/arm/dts/rk3xxx.dtsi | 215 +++++++++++++++++++++++++------------- 4 files changed, 181 insertions(+), 74 deletions(-) create mode 100644 arch/arm/dts/rk3xxx-u-boot.dtsi
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 61367126ba..10527a052d 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -12,6 +12,10 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188";
aliases {mmc0 = &mmc0;};chosen {/* stdout-path = &uart2; */ stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 7bcca6a02d..d872dac174 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3188-cru.h> #include "rk3xxx.dtsi" +#include "rk3xxx-u-boot.dtsi"
/ { compatible = "rockchip,rk3188"; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi new file mode 100644 index 0000000000..581594c35d --- /dev/null +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/ {
noc: syscon@10128000 {compatible = "rockchip,rk3188-noc", "syscon";reg = <0x10128000 0x2000>;u-boot,dm-spl;};dmc: dmc@20020000 {/* unreviewed u-boot-specific binding */compatible = "rockchip,rk3188-dmc", "syscon";reg = <0x20020000 0x3fc0x20040000 0x294>;clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;clock-names = "pclk_ddrupctl", "pclk_publ";rockchip,cru = <&cru>;rockchip,grf = <&grf>;rockchip,pmu = <&pmu>;rockchip,noc = <&noc>;u-boot,dm-spl;};+};
+&grf {
u-boot,dm-spl;+};
+&pmu {
u-boot,dm-spl;+};
+&uart2 {
clock-frequency = <24000000>;+}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi index 612ed44bd6..616a828e0c 100644 --- a/arch/arm/dts/rk3xxx.dtsi +++ b/arch/arm/dts/rk3xxx.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /*
- Copyright (c) 2013 MundoReader S.L.
- Author: Heiko Stuebner heiko@sntech.de
@@ -6,9 +6,12 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" +#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
#address-cells = <1>;#size-cells = <1>;interrupt-parent = <&gic>; aliases {@@ -18,9 +21,6 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4;
mshc0 = &emmc;mshc1 = &mmc0;mshc2 = &mmc1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2;@@ -29,47 +29,6 @@ spi1 = &spi1; };
amba {compatible = "simple-bus";#address-cells = <1>;#size-cells = <1>;ranges;dmac1_s: dma-controller@20018000 {compatible = "arm,pl330", "arm,primecell";reg = <0x20018000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";};dmac1_ns: dma-controller@2001c000 {compatible = "arm,pl330", "arm,primecell";reg = <0x2001c000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";status = "disabled";};dmac2: dma-controller@20078000 {compatible = "arm,pl330", "arm,primecell";reg = <0x20078000 0x4000>;interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;clocks = <&cru ACLK_DMA2>;clock-names = "apb_pclk";};};xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>;@@ -77,7 +36,30 @@ clock-output-names = "xin24m"; };
L2: l2-cache-controller@10138000 {
gpu: gpu@10090000 {compatible = "arm,mali-400";reg = <0x10090000 0x10000>;clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;clock-names = "bus", "core";assigned-clocks = <&cru ACLK_GPU>;assigned-clock-rates = <100000000>;resets = <&cru SRST_GPU>;status = "disabled";};vpu: video-codec@10104000 {compatible = "rockchip,rk3066-vpu";reg = <0x10104000 0x800>;interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "vepu", "vdpu";clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,<&cru ACLK_VEPU>, <&cru HCLK_VEPU>;clock-names = "aclk_vdpu", "hclk_vdpu","aclk_vepu", "hclk_vepu";};L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; cache-unified;@@ -92,14 +74,14 @@ global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 0x304>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&cru CORE_PERI>; }; local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>;
interrupts = <GIC_PPI 13 0x304>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&cru CORE_PERI>; };@@ -133,10 +115,44 @@ status = "disabled"; };
noc: syscon@10128000 {u-boot,dm-spl;compatible = "rockchip,rk3188-noc", "syscon";reg = <0x10128000 0x2000>;
qos_gpu: qos@1012d000 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012d000 0x20>;};qos_vpu: qos@1012e000 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012e000 0x20>;};qos_lcdc0: qos@1012f000 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f000 0x20>;};qos_cif0: qos@1012f080 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f080 0x20>;};qos_ipp: qos@1012f100 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f100 0x20>;};qos_lcdc1: qos@1012f180 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f180 0x20>;};qos_cif1: qos@1012f200 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f200 0x20>;};qos_rga: qos@1012f280 {compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f280 0x20>; }; usb_otg: usb@10180000 {@@ -149,7 +165,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled";@@ -184,60 +199,99 @@ status = "disabled"; };
mmc0: dwmmc@10214000 {
mmc0: mmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu";dmas = <&dmac2 1>;dma-names = "rx-tx"; fifo-depth = <256>;resets = <&cru SRST_SDMMC>;reset-names = "reset"; status = "disabled"; };
mmc1: dwmmc@10218000 {
mmc1: mmc@10218000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu";dmas = <&dmac2 3>;dma-names = "rx-tx"; fifo-depth = <256>;resets = <&cru SRST_SDIO>;reset-names = "reset"; status = "disabled"; };
emmc: dwmmc@1021c000 {
emmc: mmc@1021c000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x1021c000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu";dmas = <&dmac2 4>;dma-names = "rx-tx"; fifo-depth = <256>;resets = <&cru SRST_EMMC>;reset-names = "reset";status = "disabled";};nfc: nand-controller@10500000 {compatible = "rockchip,rk2928-nfc";reg = <0x10500000 0x4000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_NANDC0>;clock-names = "ahb"; status = "disabled"; }; pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; reg = <0x20004000 0x100>;
u-boot,dm-spl;
reboot-mode {compatible = "syscon-reboot-mode";offset = <0x40>;mode-normal = <BOOT_NORMAL>;mode-recovery = <BOOT_RECOVERY>;mode-bootloader = <BOOT_FASTBOOT>;mode-loader = <BOOT_BL_DOWNLOAD>;}; }; grf: grf@20008000 {
compatible = "syscon";
compatible = "syscon", "simple-mfd"; reg = <0x20008000 0x200>;
u-boot,dm-spl; };dmc: dmc@20020000 {/* unreviewed u-boot-specific binding */compatible = "rockchip,rk3188-dmc", "syscon";rockchip,cru = <&cru>;rockchip,grf = <&grf>;rockchip,pmu = <&pmu>;rockchip,noc = <&noc>;reg = <0x20020000 0x3fc0x20040000 0x294>;clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;clock-names = "pclk_ddrupctl", "pclk_publ";u-boot,dm-spl;
dmac1_s: dma-controller@20018000 {compatible = "arm,pl330", "arm,primecell";reg = <0x20018000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;arm,pl330-periph-burst;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";};dmac1_ns: dma-controller@2001c000 {compatible = "arm,pl330", "arm,primecell";reg = <0x2001c000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;arm,pl330-periph-burst;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";status = "disabled"; }; i2c0: i2c@2002d000 {@@ -361,7 +415,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <1>;
clock-frequency = <24000000>; clock-names = "baudclk", "apb_pclk"; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; status = "disabled";@@ -385,6 +438,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;reset-names = "saradc-apb"; status = "disabled"; };@@ -413,4 +468,16 @@ dma-names = "tx", "rx"; status = "disabled"; };
dmac2: dma-controller@20078000 {compatible = "arm,pl330", "arm,primecell";reg = <0x20078000 0x4000>;interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;arm,pl330-periph-burst;clocks = <&cru ACLK_DMA2>;clock-names = "apb_pclk";};};
2.11.0
Hi all,
I understand that copying dts'es from upstream kernel seems an easy thing to do, but we should be careful:
Now that mmc-indexes are defined in board level device trees in kernel , mmc boot order (which I just fixed some month ago [1]) is different per board.
This is now broken again - at least for rk3188 and rk3399 (from what I've seen) and it is not fixable with an extra <board>-u-boot.dtsi.
Any idea (without having to define an extra config include/configs per board?)
[1] https://github.com/u-boot/u-boot/commit/b212ad24a604b00b240add35516b7381965d...
Alex
Am 25.06.21 um 15:26 schrieb Johan Jonker:
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. This file has recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3xxx-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com Reviewed-by: Kever Yang kever.yang@rock-chips.com
Changed V2: add vpu node changed u-boot include
arch/arm/dts/rk3188-radxarock.dts | 4 + arch/arm/dts/rk3188.dtsi | 1 + arch/arm/dts/rk3xxx-u-boot.dtsi | 35 +++++++ arch/arm/dts/rk3xxx.dtsi | 215 +++++++++++++++++++++++++------------- 4 files changed, 181 insertions(+), 74 deletions(-) create mode 100644 arch/arm/dts/rk3xxx-u-boot.dtsi
diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 61367126ba..10527a052d 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -12,6 +12,10 @@ model = "Radxa Rock"; compatible = "radxa,rock", "rockchip,rk3188";
- aliases {
mmc0 = &mmc0;- };
- chosen {
/* stdout-path = &uart2; */ stdout-path = "serial2:115200n8"; diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index 7bcca6a02d..d872dac174 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3188-cru.h> #include "rk3xxx.dtsi" +#include "rk3xxx-u-boot.dtsi"
/ { compatible = "rockchip,rk3188"; diff --git a/arch/arm/dts/rk3xxx-u-boot.dtsi b/arch/arm/dts/rk3xxx-u-boot.dtsi new file mode 100644 index 0000000000..581594c35d --- /dev/null +++ b/arch/arm/dts/rk3xxx-u-boot.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/ {
- noc: syscon@10128000 {
compatible = "rockchip,rk3188-noc", "syscon";reg = <0x10128000 0x2000>;u-boot,dm-spl;- };
- dmc: dmc@20020000 {
/* unreviewed u-boot-specific binding */compatible = "rockchip,rk3188-dmc", "syscon";reg = <0x20020000 0x3fc0x20040000 0x294>;clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;clock-names = "pclk_ddrupctl", "pclk_publ";rockchip,cru = <&cru>;rockchip,grf = <&grf>;rockchip,pmu = <&pmu>;rockchip,noc = <&noc>;u-boot,dm-spl;- };
+};
+&grf {
- u-boot,dm-spl;
+};
+&pmu {
- u-boot,dm-spl;
+};
+&uart2 {
- clock-frequency = <24000000>;
+}; diff --git a/arch/arm/dts/rk3xxx.dtsi b/arch/arm/dts/rk3xxx.dtsi index 612ed44bd6..616a828e0c 100644 --- a/arch/arm/dts/rk3xxx.dtsi +++ b/arch/arm/dts/rk3xxx.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /*
- Copyright (c) 2013 MundoReader S.L.
- Author: Heiko Stuebner heiko@sntech.de
@@ -6,9 +6,12 @@
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include "skeleton.dtsi" +#include <dt-bindings/soc/rockchip,boot-mode.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
@@ -18,9 +21,6 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4;
mshc0 = &emmc;mshc1 = &mmc0;mshc2 = &mmc1;@@ -29,47 +29,6 @@ spi1 = &spi1; };
- amba {
compatible = "simple-bus";#address-cells = <1>;#size-cells = <1>;ranges;dmac1_s: dma-controller@20018000 {compatible = "arm,pl330", "arm,primecell";reg = <0x20018000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";};dmac1_ns: dma-controller@2001c000 {compatible = "arm,pl330", "arm,primecell";reg = <0x2001c000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";status = "disabled";};dmac2: dma-controller@20078000 {compatible = "arm,pl330", "arm,primecell";reg = <0x20078000 0x4000>;interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;clocks = <&cru ACLK_DMA2>;clock-names = "apb_pclk";};- };
- xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>;
@@ -77,7 +36,30 @@ clock-output-names = "xin24m"; };
- L2: l2-cache-controller@10138000 {
- gpu: gpu@10090000 {
compatible = "arm,mali-400";reg = <0x10090000 0x10000>;clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;clock-names = "bus", "core";assigned-clocks = <&cru ACLK_GPU>;assigned-clock-rates = <100000000>;resets = <&cru SRST_GPU>;status = "disabled";- };
- vpu: video-codec@10104000 {
compatible = "rockchip,rk3066-vpu";reg = <0x10104000 0x800>;interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "vepu", "vdpu";clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,<&cru ACLK_VEPU>, <&cru HCLK_VEPU>;clock-names = "aclk_vdpu", "hclk_vdpu","aclk_vepu", "hclk_vepu";- };
- L2: cache-controller@10138000 { compatible = "arm,pl310-cache"; reg = <0x10138000 0x1000>; cache-unified;
@@ -92,14 +74,14 @@ global_timer: global-timer@1013c200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 0x304>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;clocks = <&cru CORE_PERI>; };
local_timer: local-timer@1013c600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x1013c600 0x20>;
interrupts = <GIC_PPI 13 0x304>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;@@ -133,10 +115,44 @@ status = "disabled"; };
- noc: syscon@10128000 {
u-boot,dm-spl;compatible = "rockchip,rk3188-noc", "syscon";reg = <0x10128000 0x2000>;
qos_gpu: qos@1012d000 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012d000 0x20>;};
qos_vpu: qos@1012e000 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012e000 0x20>;};
qos_lcdc0: qos@1012f000 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f000 0x20>;};
qos_cif0: qos@1012f080 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f080 0x20>;};
qos_ipp: qos@1012f100 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f100 0x20>;};
qos_lcdc1: qos@1012f180 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f180 0x20>;};
qos_cif1: qos@1012f200 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f200 0x20>;};
qos_rga: qos@1012f280 {
compatible = "rockchip,rk3066-qos", "syscon";reg = <0x1012f280 0x20>;};
usb_otg: usb@10180000 {
@@ -149,7 +165,6 @@ g-np-tx-fifo-size = <16>; g-rx-fifo-size = <275>; g-tx-fifo-size = <256 128 128 64 64 32>;
g-use-dma;@@ -184,60 +199,99 @@ status = "disabled"; };
- mmc0: dwmmc@10214000 {
- mmc0: mmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu";
dmas = <&dmac2 1>;dma-names = "rx-tx";resets = <&cru SRST_SDMMC>;reset-names = "reset";
- mmc1: dwmmc@10218000 {
- mmc1: mmc@10218000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu";
dmas = <&dmac2 3>;dma-names = "rx-tx";resets = <&cru SRST_SDIO>;reset-names = "reset";
- emmc: dwmmc@1021c000 {
emmc: mmc@1021c000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x1021c000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; clock-names = "biu", "ciu";
dmas = <&dmac2 4>;dma-names = "rx-tx";fifo-depth = <256>;
resets = <&cru SRST_EMMC>;reset-names = "reset";status = "disabled";};
nfc: nand-controller@10500000 {
compatible = "rockchip,rk2928-nfc";reg = <0x10500000 0x4000>;interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru HCLK_NANDC0>;clock-names = "ahb";status = "disabled"; };
pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
u-boot,dm-spl;
reboot-mode {compatible = "syscon-reboot-mode";offset = <0x40>;mode-normal = <BOOT_NORMAL>;mode-recovery = <BOOT_RECOVERY>;mode-bootloader = <BOOT_FASTBOOT>;mode-loader = <BOOT_BL_DOWNLOAD>;};};
grf: grf@20008000 {
compatible = "syscon";
compatible = "syscon", "simple-mfd";
u-boot,dm-spl;};
dmc: dmc@20020000 {
/* unreviewed u-boot-specific binding */compatible = "rockchip,rk3188-dmc", "syscon";rockchip,cru = <&cru>;rockchip,grf = <&grf>;rockchip,pmu = <&pmu>;rockchip,noc = <&noc>;reg = <0x20020000 0x3fc0x20040000 0x294>;clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;clock-names = "pclk_ddrupctl", "pclk_publ";u-boot,dm-spl;
dmac1_s: dma-controller@20018000 {
compatible = "arm,pl330", "arm,primecell";reg = <0x20018000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;arm,pl330-periph-burst;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";};
dmac1_ns: dma-controller@2001c000 {
compatible = "arm,pl330", "arm,primecell";reg = <0x2001c000 0x4000>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;arm,pl330-periph-burst;clocks = <&cru ACLK_DMA1>;clock-names = "apb_pclk";status = "disabled";};
i2c0: i2c@2002d000 {
@@ -361,7 +415,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <1>;
clock-frequency = <24000000>;@@ -385,6 +438,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_SARADC>;reset-names = "saradc-apb";@@ -413,4 +468,16 @@ dma-names = "tx", "rx"; status = "disabled"; };
- dmac2: dma-controller@20078000 {
compatible = "arm,pl330", "arm,primecell";reg = <0x20078000 0x4000>;interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;#dma-cells = <1>;arm,pl330-broken-no-flushp;arm,pl330-periph-burst;clocks = <&cru ACLK_DMA2>;clock-names = "apb_pclk";- };
};
In order to update the DT for rk3188 sync the power domain dt-binding header. This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker jbx6244@gmail.com --- include/dt-bindings/power/rk3188-power.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/dt-bindings/power/rk3188-power.h
diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h new file mode 100644 index 0000000000..93d23dfba3 --- /dev/null +++ b/include/dt-bindings/power/rk3188-power.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +#define __DT_BINDINGS_POWER_RK3188_POWER_H__ + +/* VD_CORE */ +#define RK3188_PD_A9_0 0 +#define RK3188_PD_A9_1 1 +#define RK3188_PD_A9_2 2 +#define RK3188_PD_A9_3 3 +#define RK3188_PD_DBG 4 +#define RK3188_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3188_PD_VIDEO 6 +#define RK3188_PD_VIO 7 +#define RK3188_PD_GPU 8 +#define RK3188_PD_PERI 9 +#define RK3188_PD_CPU 10 +#define RK3188_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3188_PD_RTC 12 + +#endif
Johan Jonker jbx6244@gmail.com 于2021年6月25日周五 下午9:31写道：
In order to update the DT for rk3188 sync the power domain dt-binding header. This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker jbx6244@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
include/dt-bindings/power/rk3188-power.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/dt-bindings/power/rk3188-power.h
diff --git a/include/dt-bindings/power/rk3188-power.h b/include/dt-bindings/power/rk3188-power.h new file mode 100644 index 0000000000..93d23dfba3 --- /dev/null +++ b/include/dt-bindings/power/rk3188-power.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__ +#define __DT_BINDINGS_POWER_RK3188_POWER_H__
+/* VD_CORE */ +#define RK3188_PD_A9_0 0 +#define RK3188_PD_A9_1 1 +#define RK3188_PD_A9_2 2 +#define RK3188_PD_A9_3 3 +#define RK3188_PD_DBG 4 +#define RK3188_PD_SCU 5
+/* VD_LOGIC */ +#define RK3188_PD_VIDEO 6 +#define RK3188_PD_VIO 7 +#define RK3188_PD_GPU 8 +#define RK3188_PD_PERI 9 +#define RK3188_PD_CPU 10 +#define RK3188_PD_ALIVE 11
+/* VD_PMU */ +#define RK3188_PD_RTC 12
+#endif
2.11.0
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com --- arch/arm/dts/rk3188-u-boot.dtsi | 13 ++ arch/arm/dts/rk3188.dtsi | 479 ++++++++++++++++++++++++++++------------ 2 files changed, 356 insertions(+), 136 deletions(-)
diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 41ac054b81..43f05b9876 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -4,3 +4,16 @@ */
#include "rockchip-u-boot.dtsi" + +&global_timer { + status = "okay"; +}; + +&gpio0 { + compatible = "rockchip,gpio-bank"; +}; + +&pmu { + compatible = "rockchip,rk3188-pmu", "syscon", "simple-mfd"; +}; + diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index d872dac174..6c1c2ff533 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 MundoReader S.L. * Author: Heiko Stuebner heiko@sntech.de @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3188-cru.h> +#include <dt-bindings/power/rk3188-power.h> #include "rk3xxx.dtsi" #include "rk3xxx-u-boot.dtsi"
@@ -23,40 +24,82 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; - operating-points = < - /* kHz uV */ - 1608000 1350000 - 1416000 1250000 - 1200000 1150000 - 1008000 1075000 - 816000 975000 - 600000 950000 - 504000 925000 - 312000 875000 - >; clock-latency = <40000>; clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x1>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x2>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x3>; + operating-points-v2 = <&cpu0_opp_table>; + resets = <&cru SRST_CORE3>; }; };
+ cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <875000>; + clock-latency-ns = <40000>; + }; + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <925000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000>; + opp-suspend; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <975000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1075000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1150000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1250000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; + }; + }; + + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop0_out>, <&vop1_out>; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>; @@ -70,20 +113,69 @@ }; };
+ vop0: vop@1010c000 { + compatible = "rockchip,rk3188-vop"; + reg = <0x1010c000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop0_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + vop1: vop@1010e000 { + compatible = "rockchip,rk3188-vop"; + reg = <0x1010e000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3188_PD_VIO>; + resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vop1_out: port { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + timer3: timer@2000e000 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x2000e000 0x20>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; + clock-names = "pclk", "timer"; + }; + + timer6: timer@200380a0 { + compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; + reg = <0x200380a0 0x20>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; + clock-names = "pclk", "timer"; + }; + i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 6>, <&dmac1_s 7>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; status = "disabled"; };
@@ -91,8 +183,8 @@ compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; reg = <0x1011e000 0x2000>; #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; dmas = <&dmac1_s 8>; dma-names = "tx"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; @@ -111,7 +203,7 @@ };
efuse: efuse@20010000 { - compatible = "rockchip,rockchip-efuse"; + compatible = "rockchip,rk3188-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>; @@ -123,36 +215,6 @@ }; };
- timer3: timer@2000e000 { - compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; - reg = <0x2000e000 0x20>; - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - }; - - usbphy: phy { - compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@10c { - #phy-cells = <0>; - reg = <0x10c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@11c { - #phy-cells = <0>; - reg = <0x11c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>; @@ -163,7 +225,7 @@ ranges;
gpio0: gpio0@2000a000 { - compatible = "rockchip,gpio-bank"; + compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>; @@ -228,15 +290,15 @@
emmc { emmc_clk: emmc-clk { - rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; };
emmc_cmd: emmc-cmd { - rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; };
emmc_rst: emmc-rst { - rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; };
/* @@ -249,246 +311,291 @@
emac { emac_xfer: emac-xfer { - rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ - <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ - <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ - <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */ - <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ - <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ - <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ - <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */ + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ + <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ + <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ + <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ + <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ + <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ + <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ + <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ };
emac_mdio: emac-mdio { - rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>, - <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, + <3 RK_PD1 2 &pcfg_pull_none>; }; };
i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>; }; };
i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; }; };
i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>; }; };
i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>, - <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, + <3 RK_PB7 2 &pcfg_pull_none>; }; };
i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + lcdc1 { + lcdc1_dclk: lcdc1-dclk { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; + }; + + lcdc1_den: lcdc1-den { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; + }; + + lcdc1_hsync: lcdc1-hsync { + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; + }; + + lcdc1_vsync: lcdc1-vsync { + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; + }; + + lcdc1_rgb24: ldcd1-rgb24 { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, + <2 RK_PA1 1 &pcfg_pull_none>, + <2 RK_PA2 1 &pcfg_pull_none>, + <2 RK_PA3 1 &pcfg_pull_none>, + <2 RK_PA4 1 &pcfg_pull_none>, + <2 RK_PA5 1 &pcfg_pull_none>, + <2 RK_PA6 1 &pcfg_pull_none>, + <2 RK_PA7 1 &pcfg_pull_none>, + <2 RK_PB0 1 &pcfg_pull_none>, + <2 RK_PB1 1 &pcfg_pull_none>, + <2 RK_PB2 1 &pcfg_pull_none>, + <2 RK_PB3 1 &pcfg_pull_none>, + <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; };
pwm0 { pwm0_out: pwm0-out { - rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; }; };
pwm1 { pwm1_out: pwm1-out { - rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; }; };
pwm2 { pwm2_out: pwm2-out { - rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; }; };
pwm3 { pwm3_out: pwm3-out { - rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; }; };
spi0 { spi0_clk: spi0-clk { - rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; }; };
spi1 { spi1_clk: spi1-clk { - rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 { - rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; }; };
uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, + <1 RK_PA1 1 &pcfg_pull_none>; };
uart0_cts: uart0-cts { - rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; };
uart0_rts: uart0-rts { - rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; }; };
uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, + <1 RK_PA5 1 &pcfg_pull_none>; };
uart1_cts: uart1-cts { - rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; };
uart1_rts: uart1-rts { - rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; }; };
uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, + <1 RK_PB1 1 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ };
uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, - <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, + <1 RK_PB3 1 &pcfg_pull_none>; };
uart3_cts: uart3-cts { - rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; };
uart3_rts: uart3-rts { - rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; }; };
sd0 { sd0_clk: sd0-clk { - rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; };
sd0_cmd: sd0-cmd { - rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; };
sd0_cd: sd0-cd { - rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; };
sd0_wp: sd0-wp { - rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; };
sd0_pwr: sd0-pwr { - rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; };
sd0_bus1: sd0-bus-width1 { - rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; };
sd0_bus4: sd0-bus-width4 { - rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, + <3 RK_PA5 1 &pcfg_pull_none>, + <3 RK_PA6 1 &pcfg_pull_none>, + <3 RK_PA7 1 &pcfg_pull_none>; }; };
sd1 { sd1_clk: sd1-clk { - rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; };
sd1_cmd: sd1-cmd { - rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; };
sd1_cd: sd1-cd { - rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; };
sd1_wp: sd1-wp { - rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; };
sd1_bus1: sd1-bus-width1 { - rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; };
sd1_bus4: sd1-bus-width4 { - rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, + <3 RK_PC2 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>; }; };
i2s0 { i2s0_bus: i2s0-bus { - rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>, - <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, + <1 RK_PC1 1 &pcfg_pull_none>, + <1 RK_PC2 1 &pcfg_pull_none>, + <1 RK_PC3 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>, + <1 RK_PC5 1 &pcfg_pull_none>; }; };
spdif { spdif_tx: spdif-tx { - rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; }; }; }; @@ -499,15 +606,65 @@ };
&global_timer { - interrupts = <GIC_PPI 11 0xf04>; + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + status = "disabled"; };
-&grf { - compatible = "rockchip,rk3188-grf", "syscon"; +&local_timer { + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; };
-&local_timer { - interrupts = <GIC_PPI 13 0xf04>; +&gpu { + compatible = "rockchip,rk3188-mali", "arm,mali-400"; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + power-domains = <&power RK3188_PD_GPU>; +}; + +&grf { + compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; + + usbphy: usbphy { + compatible = "rockchip,rk3188-usb-phy", + "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@10c { + reg = <0x10c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + + usbphy1: usb-phy@11c { + reg = <0x11c>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + #phy-cells = <0>; + }; + }; };
&i2c0 { @@ -541,7 +698,52 @@ };
&pmu { - compatible = "rockchip,rk3188-pmu", "syscon"; + power: power-controller { + compatible = "rockchip,rk3188-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3188_PD_VIO { + reg = <RK3188_PD_VIO>; + clocks = <&cru ACLK_LCDC0>, + <&cru ACLK_LCDC1>, + <&cru DCLK_LCDC0>, + <&cru DCLK_LCDC1>, + <&cru HCLK_LCDC0>, + <&cru HCLK_LCDC1>, + <&cru SCLK_CIF0>, + <&cru ACLK_CIF0>, + <&cru HCLK_CIF0>, + <&cru ACLK_IPP>, + <&cru HCLK_IPP>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_lcdc0>, + <&qos_lcdc1>, + <&qos_cif0>, + <&qos_ipp>, + <&qos_rga>; + #power-domain-cells = <0>; + }; + + power-domain@RK3188_PD_VIDEO { + reg = <RK3188_PD_VIDEO>; + clocks = <&cru ACLK_VDPU>, + <&cru ACLK_VEPU>, + <&cru HCLK_VDPU>, + <&cru HCLK_VEPU>; + pm_qos = <&qos_vpu>; + #power-domain-cells = <0>; + }; + + power-domain@RK3188_PD_GPU { + reg = <RK3188_PD_GPU>; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + #power-domain-cells = <0>; + }; + }; };
&pwm0 { @@ -600,6 +802,11 @@ pinctrl-0 = <&uart3_xfer>; };
+&vpu { + compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; + power-domains = <&power RK3188_PD_VIDEO>; +}; + &wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; };
Johan Jonker jbx6244@gmail.com 于2021年6月25日周五 下午9:31写道：
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3188-u-boot.dtsi | 13 ++ arch/arm/dts/rk3188.dtsi | 479 ++++++++++++++++++++++++++++------------ 2 files changed, 356 insertions(+), 136 deletions(-)
diff --git a/arch/arm/dts/rk3188-u-boot.dtsi b/arch/arm/dts/rk3188-u-boot.dtsi index 41ac054b81..43f05b9876 100644 --- a/arch/arm/dts/rk3188-u-boot.dtsi +++ b/arch/arm/dts/rk3188-u-boot.dtsi @@ -4,3 +4,16 @@ */
#include "rockchip-u-boot.dtsi"
+&global_timer {
status = "okay";+};
+&gpio0 {
compatible = "rockchip,gpio-bank";+};
+&pmu {
compatible = "rockchip,rk3188-pmu", "syscon", "simple-mfd";+};
diff --git a/arch/arm/dts/rk3188.dtsi b/arch/arm/dts/rk3188.dtsi index d872dac174..6c1c2ff533 100644 --- a/arch/arm/dts/rk3188.dtsi +++ b/arch/arm/dts/rk3188.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /*
- Copyright (c) 2013 MundoReader S.L.
- Author: Heiko Stuebner heiko@sntech.de
@@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3188-cru.h> +#include <dt-bindings/power/rk3188-power.h> #include "rk3xxx.dtsi" #include "rk3xxx-u-boot.dtsi"
@@ -23,40 +24,82 @@ compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>;
operating-points = </* kHz uV */1608000 13500001416000 12500001200000 11500001008000 1075000816000 975000600000 950000504000 925000312000 875000>; clock-latency = <40000>; clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;resets = <&cru SRST_CORE0>; };
cpu@1 {
cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x1>;operating-points-v2 = <&cpu0_opp_table>;resets = <&cru SRST_CORE1>; };
cpu@2 {
cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x2>;operating-points-v2 = <&cpu0_opp_table>;resets = <&cru SRST_CORE2>; };
cpu@3 {
cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x3>;operating-points-v2 = <&cpu0_opp_table>;resets = <&cru SRST_CORE3>; }; };cpu0_opp_table: opp_table0 {compatible = "operating-points-v2";opp-shared;opp-312000000 {opp-hz = /bits/ 64 <312000000>;opp-microvolt = <875000>;clock-latency-ns = <40000>;};opp-504000000 {opp-hz = /bits/ 64 <504000000>;opp-microvolt = <925000>;};opp-600000000 {opp-hz = /bits/ 64 <600000000>;opp-microvolt = <950000>;opp-suspend;};opp-816000000 {opp-hz = /bits/ 64 <816000000>;opp-microvolt = <975000>;};opp-1008000000 {opp-hz = /bits/ 64 <1008000000>;opp-microvolt = <1075000>;};opp-1200000000 {opp-hz = /bits/ 64 <1200000000>;opp-microvolt = <1150000>;};opp-1416000000 {opp-hz = /bits/ 64 <1416000000>;opp-microvolt = <1250000>;};opp-1608000000 {opp-hz = /bits/ 64 <1608000000>;opp-microvolt = <1350000>;};};display-subsystem {compatible = "rockchip,display-subsystem";ports = <&vop0_out>, <&vop1_out>;};sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x8000>;@@ -70,20 +113,69 @@ }; };
vop0: vop@1010c000 {compatible = "rockchip,rk3188-vop";reg = <0x1010c000 0x1000>;interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;clock-names = "aclk_vop", "dclk_vop", "hclk_vop";power-domains = <&power RK3188_PD_VIO>;resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;reset-names = "axi", "ahb", "dclk";status = "disabled";vop0_out: port {#address-cells = <1>;#size-cells = <0>;};};vop1: vop@1010e000 {compatible = "rockchip,rk3188-vop";reg = <0x1010e000 0x1000>;interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;clock-names = "aclk_vop", "dclk_vop", "hclk_vop";power-domains = <&power RK3188_PD_VIO>;resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;reset-names = "axi", "ahb", "dclk";status = "disabled";vop1_out: port {#address-cells = <1>;#size-cells = <0>;};};timer3: timer@2000e000 {compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";reg = <0x2000e000 0x20>;interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;clock-names = "pclk", "timer";};timer6: timer@200380a0 {compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";reg = <0x200380a0 0x20>;interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;clock-names = "pclk", "timer";};i2s0: i2s@1011a000 { compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; reg = <0x1011a000 0x2000>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;#size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>;
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>;clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac1_s 6>, <&dmac1_s 7>; dma-names = "tx", "rx";
clock-names = "i2s_hclk", "i2s_clk";clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>;
#sound-dai-cells = <0>; status = "disabled"; };@@ -91,8 +183,8 @@ compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; reg = <0x1011e000 0x2000>; #sound-dai-cells = <0>;
clock-names = "hclk", "mclk";clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;clock-names = "mclk", "hclk"; dmas = <&dmac1_s 8>; dma-names = "tx"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;@@ -111,7 +203,7 @@ };
efuse: efuse@20010000 {
compatible = "rockchip,rockchip-efuse";
compatible = "rockchip,rk3188-efuse"; reg = <0x20010000 0x4000>; #address-cells = <1>; #size-cells = <1>;@@ -123,36 +215,6 @@ }; };
timer3: timer@2000e000 {compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";reg = <0x2000e000 0x20>;interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;};usbphy: phy {compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";rockchip,grf = <&grf>;#address-cells = <1>;#size-cells = <0>;status = "disabled";usbphy0: usb-phy@10c {#phy-cells = <0>;reg = <0x10c>;clocks = <&cru SCLK_OTGPHY0>;clock-names = "phyclk";#clock-cells = <0>;};usbphy1: usb-phy@11c {#phy-cells = <0>;reg = <0x11c>;clocks = <&cru SCLK_OTGPHY1>;clock-names = "phyclk";#clock-cells = <0>;};};pinctrl: pinctrl { compatible = "rockchip,rk3188-pinctrl"; rockchip,grf = <&grf>;@@ -163,7 +225,7 @@ ranges;
gpio0: gpio0@2000a000 {
compatible = "rockchip,gpio-bank";
compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>;@@ -228,15 +290,15 @@
emmc { emmc_clk: emmc-clk {
rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd {
rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; }; emmc_rst: emmc-rst {
rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; }; /*@@ -249,246 +311,291 @@
emac { emac_xfer: emac-xfer {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */<3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */<3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */<3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */<3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */<3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */<3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */<3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ }; emac_mdio: emac-mdio {
rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,<3 RK_PD1 2 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer {
rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,<1 RK_PD1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer {
rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>,<1 RK_PD3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer {
rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>,<1 RK_PD5 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer {
rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>,<3 RK_PB7 2 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer {
rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,<1 RK_PD7 1 &pcfg_pull_none>;};};lcdc1 {lcdc1_dclk: lcdc1-dclk {rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;};lcdc1_den: lcdc1-den {rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;};lcdc1_hsync: lcdc1-hsync {rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;};lcdc1_vsync: lcdc1-vsync {rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;};lcdc1_rgb24: ldcd1-rgb24 {rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,<2 RK_PA1 1 &pcfg_pull_none>,<2 RK_PA2 1 &pcfg_pull_none>,<2 RK_PA3 1 &pcfg_pull_none>,<2 RK_PA4 1 &pcfg_pull_none>,<2 RK_PA5 1 &pcfg_pull_none>,<2 RK_PA6 1 &pcfg_pull_none>,<2 RK_PA7 1 &pcfg_pull_none>,<2 RK_PB0 1 &pcfg_pull_none>,<2 RK_PB1 1 &pcfg_pull_none>,<2 RK_PB2 1 &pcfg_pull_none>,<2 RK_PB3 1 &pcfg_pull_none>,<2 RK_PB4 1 &pcfg_pull_none>,<2 RK_PB5 1 &pcfg_pull_none>,<2 RK_PB6 1 &pcfg_pull_none>,<2 RK_PB7 1 &pcfg_pull_none>,<2 RK_PC0 1 &pcfg_pull_none>,<2 RK_PC1 1 &pcfg_pull_none>,<2 RK_PC2 1 &pcfg_pull_none>,<2 RK_PC3 1 &pcfg_pull_none>,<2 RK_PC4 1 &pcfg_pull_none>,<2 RK_PC5 1 &pcfg_pull_none>,<2 RK_PC6 1 &pcfg_pull_none>,<2 RK_PC7 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_out: pwm0-out {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_out: pwm1-out {
rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_out: pwm2-out {
rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; }; }; pwm3 { pwm3_out: pwm3-out {
rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; }; }; spi0 { spi0_clk: spi0-clk {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; }; spi0_tx: spi0-tx {
rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; }; spi0_rx: spi0-rx {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 {
rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk {
rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 {
rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; }; spi1_rx: spi1-rx {
rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; }; spi1_tx: spi1-tx {
rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; }; spi1_cs1: spi1-cs1 {
rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; }; }; uart0 { uart0_xfer: uart0-xfer {
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>,<1 RK_PA1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts {
rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts {
rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer {
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>,<1 RK_PA5 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts {
rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts {
rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer {
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>,<1 RK_PB1 1 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer {
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>,<1 RK_PB3 1 &pcfg_pull_none>; }; uart3_cts: uart3-cts {
rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; }; uart3_rts: uart3-rts {
rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; }; }; sd0 { sd0_clk: sd0-clk {
rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; }; sd0_cmd: sd0-cmd {
rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; }; sd0_cd: sd0-cd {
rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; }; sd0_wp: sd0-wp {
rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; }; sd0_pwr: sd0-pwr {
rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; }; sd0_bus1: sd0-bus-width1 {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; }; sd0_bus4: sd0-bus-width4 {
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>,<3 RK_PA5 1 &pcfg_pull_none>,<3 RK_PA6 1 &pcfg_pull_none>,<3 RK_PA7 1 &pcfg_pull_none>; }; }; sd1 { sd1_clk: sd1-clk {
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; }; sd1_cmd: sd1-cmd {
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; }; sd1_cd: sd1-cd {
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; }; sd1_wp: sd1-wp {
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; }; sd1_bus1: sd1-bus-width1 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; }; sd1_bus4: sd1-bus-width4 {
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>,<3 RK_PC2 1 &pcfg_pull_none>,<3 RK_PC3 1 &pcfg_pull_none>,<3 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { i2s0_bus: i2s0-bus {
rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,<1 RK_PC1 1 &pcfg_pull_none>,<1 RK_PC2 1 &pcfg_pull_none>,<1 RK_PC3 1 &pcfg_pull_none>,<1 RK_PC4 1 &pcfg_pull_none>,<1 RK_PC5 1 &pcfg_pull_none>; }; }; spdif { spdif_tx: spdif-tx {
rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; }; }; };@@ -499,15 +606,65 @@ };
&global_timer {
interrupts = <GIC_PPI 11 0xf04>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;status = "disabled";};
-&grf {
compatible = "rockchip,rk3188-grf", "syscon";+&local_timer {
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;};
-&local_timer {
interrupts = <GIC_PPI 13 0xf04>;+&gpu {
compatible = "rockchip,rk3188-mali", "arm,mali-400";interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "gp","gpmmu","pp0","ppmmu0","pp1","ppmmu1","pp2","ppmmu2","pp3","ppmmu3";power-domains = <&power RK3188_PD_GPU>;+};
+&grf {
compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";usbphy: usbphy {compatible = "rockchip,rk3188-usb-phy","rockchip,rk3288-usb-phy";#address-cells = <1>;#size-cells = <0>;status = "disabled";usbphy0: usb-phy@10c {reg = <0x10c>;clocks = <&cru SCLK_OTGPHY0>;clock-names = "phyclk";#clock-cells = <0>;#phy-cells = <0>;};usbphy1: usb-phy@11c {reg = <0x11c>;clocks = <&cru SCLK_OTGPHY1>;clock-names = "phyclk";#clock-cells = <0>;#phy-cells = <0>;};};};
&i2c0 { @@ -541,7 +698,52 @@ };
&pmu {
compatible = "rockchip,rk3188-pmu", "syscon";
power: power-controller {compatible = "rockchip,rk3188-power-controller";#power-domain-cells = <1>;#address-cells = <1>;#size-cells = <0>;power-domain@RK3188_PD_VIO {reg = <RK3188_PD_VIO>;clocks = <&cru ACLK_LCDC0>,<&cru ACLK_LCDC1>,<&cru DCLK_LCDC0>,<&cru DCLK_LCDC1>,<&cru HCLK_LCDC0>,<&cru HCLK_LCDC1>,<&cru SCLK_CIF0>,<&cru ACLK_CIF0>,<&cru HCLK_CIF0>,<&cru ACLK_IPP>,<&cru HCLK_IPP>,<&cru ACLK_RGA>,<&cru HCLK_RGA>;pm_qos = <&qos_lcdc0>,<&qos_lcdc1>,<&qos_cif0>,<&qos_ipp>,<&qos_rga>;#power-domain-cells = <0>;};power-domain@RK3188_PD_VIDEO {reg = <RK3188_PD_VIDEO>;clocks = <&cru ACLK_VDPU>,<&cru ACLK_VEPU>,<&cru HCLK_VDPU>,<&cru HCLK_VEPU>;pm_qos = <&qos_vpu>;#power-domain-cells = <0>;};power-domain@RK3188_PD_GPU {reg = <RK3188_PD_GPU>;clocks = <&cru ACLK_GPU>;pm_qos = <&qos_gpu>;#power-domain-cells = <0>;};};};
&pwm0 { @@ -600,6 +802,11 @@ pinctrl-0 = <&uart3_xfer>; };
+&vpu {
compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";power-domains = <&power RK3188_PD_VIDEO>;+};
&wdt { compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; }; -- 2.11.0
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com --- arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 38 ++++++++++--- arch/arm/dts/rk3188-radxarock.dts | 88 +++++++++++++++---------------- 2 files changed, 73 insertions(+), 53 deletions(-)
diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index 204bb3a90e..9c9016de1b 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -5,36 +5,58 @@
#include "rk3188-u-boot.dtsi"
+/ { + chosen { +/* stdout-path = &uart2; */ + stdout-path = "serial2:115200n8"; + }; + + config { + u-boot,boot-led = "rock:red:power"; + u-boot,dm-pre-reloc; + }; +}; + &cru { u-boot,dm-spl; };
-&pinctrl { - u-boot,dm-spl; +&dmc { + rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 + 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 + 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 + 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 + 0x4 0x0>; + rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 + 0x220 0x40 0x0 0x0>; + rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; };
-&mmc0 { +&emmc { fifo-mode; max-frequency = <16000000>; };
-&mmc1 { +&mmc0 { fifo-mode; max-frequency = <16000000>; };
-&emmc { +&mmc1 { fifo-mode; max-frequency = <16000000>; };
-&uart2 { - status = "okay"; +&pinctrl { u-boot,dm-spl; };
&timer3 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; - u-boot,dm-spl; clock-frequency = <24000000>; + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 10527a052d..e7138a4ae0 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2013 Heiko Stuebner heiko@sntech.de */ @@ -16,17 +16,7 @@ mmc0 = &mmc0; };
- chosen { -/* stdout-path = &uart2; */ - stdout-path = "serial2:115200n8"; - }; - - config { - u-boot,dm-pre-reloc; - u-boot,boot-led = "rock:red:power"; - }; - - memory { + memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; }; @@ -36,7 +26,7 @@ autorepeat;
power { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; @@ -48,21 +38,21 @@ gpio-leds { compatible = "gpio-leds";
- green { + green_led: led-0 { label = "rock:green:user1"; - gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; default-state = "off"; };
- blue { + blue_led: led-1 { label = "rock:blue:user2"; - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; default-state = "off"; };
- sleep { + sleep_led: led-2 { label = "rock:red:power"; - gpios = <&gpio0 15 0>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; @@ -84,7 +74,7 @@
ir_recv: gpio-ir-receiver { compatible = "gpio-ir-receiver"; - gpios = <&gpio0 10 1>; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_recv_pin>; }; @@ -92,7 +82,7 @@ vcc_otg: usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&otg_vbus_drv>; regulator-name = "otg-vbus"; @@ -107,7 +97,7 @@ regulator-name = "sdmmc-supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio3 1 GPIO_ACTIVE_LOW>; + gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_pwr>; startup-delay-us = <100000>; @@ -117,7 +107,7 @@ vcc_host: usb-host-regulator { compatible = "regulator-fixed"; enable-active-high; - gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "host-pwr"; @@ -136,17 +126,6 @@ }; };
-&dmc { - rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 - 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 - 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 - 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 - 0x4 0x0>; - rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 - 0x220 0x40 0x0 0x0>; - rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; -}; - &emac { status = "okay";
@@ -159,12 +138,28 @@ phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; }; };
&cpu0 { - cpu0-supply = <&vdd_arm>; + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&gpu { + status = "okay"; };
&i2c1 { @@ -175,7 +170,7 @@ compatible = "haoyu,hym8563"; reg = <0x51>; interrupt-parent = <&gpio0>; - interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&rtc_int>; #clock-cells = <0>; @@ -287,7 +282,6 @@ };
&mmc0 { - num-slots = <1>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; @@ -318,40 +312,40 @@
act8846 { act8846_dvs0_ctl: act8846-dvs0-ctl { - rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>; + rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; }; };
hym8563 { rtc_int: rtc-int { - rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; };
lan8720a { phy_int: phy-int { - rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>; + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; };
ir-receiver { ir_recv_pin: ir-recv-pin { - rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; };
sd0 { sdmmc_pwr: sdmmc-pwr { - rockchip,pins = <RK_GPIO3 1 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; };
usb { host_vbus_drv: host-vbus-drv { - rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; otg_vbus_drv: otg-vbus-drv { - rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; @@ -368,6 +362,10 @@ status = "okay"; };
+&uart2 { + status = "okay"; +}; + &uart3 { status = "okay"; };
Johan Jonker jbx6244@gmail.com 于2021年6月25日周五 下午9:31写道：
In the Linux DT the file rk3xxx.dtsi is shared between rk3066 and rk3188. Both rk3xxx.dtsi and rk3188.dtsi have recently had some updates. For a future rk3066 support in U-boot this file must also update. Move U-boot specific things in a rk3188-radxarock-u-boot.dtsi file.
Signed-off-by: Johan Jonker jbx6244@gmail.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/dts/rk3188-radxarock-u-boot.dtsi | 38 ++++++++++--- arch/arm/dts/rk3188-radxarock.dts | 88 +++++++++++++++---------------- 2 files changed, 73 insertions(+), 53 deletions(-)
diff --git a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi index 204bb3a90e..9c9016de1b 100644 --- a/arch/arm/dts/rk3188-radxarock-u-boot.dtsi +++ b/arch/arm/dts/rk3188-radxarock-u-boot.dtsi @@ -5,36 +5,58 @@
#include "rk3188-u-boot.dtsi"
+/ {
chosen {+/* stdout-path = &uart2; */
stdout-path = "serial2:115200n8";};config {u-boot,boot-led = "rock:red:power";u-boot,dm-pre-reloc;};+};
&cru { u-boot,dm-spl; };
-&pinctrl {
u-boot,dm-spl;+&dmc {
rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x60x3 0x0 0x6 0x5 0xc 0x10 0x6 0x40x4 0x5 0x4 0x200 0x3 0xa 0x40 0x00x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x00x4 0x0>;rockchip,phy-timing = <0x208c6690 0x690878 0x10022a000x220 0x40 0x0 0x0>;rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;};
-&mmc0 { +&emmc { fifo-mode; max-frequency = <16000000>; };
-&mmc1 { +&mmc0 { fifo-mode; max-frequency = <16000000>; };
-&emmc { +&mmc1 { fifo-mode; max-frequency = <16000000>; };
-&uart2 {
status = "okay";+&pinctrl { u-boot,dm-spl; };
&timer3 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
u-boot,dm-spl; clock-frequency = <24000000>;
u-boot,dm-spl;+};
+&uart2 {
u-boot,dm-spl;}; diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts index 10527a052d..e7138a4ae0 100644 --- a/arch/arm/dts/rk3188-radxarock.dts +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /*
- Copyright (c) 2013 Heiko Stuebner heiko@sntech.de
*/ @@ -16,17 +16,7 @@ mmc0 = &mmc0; };
chosen {-/* stdout-path = &uart2; */
stdout-path = "serial2:115200n8";};config {u-boot,dm-pre-reloc;u-boot,boot-led = "rock:red:power";};memory {
memory@60000000 { device_type = "memory"; reg = <0x60000000 0x80000000>; };@@ -36,7 +26,7 @@ autorepeat;
power {
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>;@@ -48,21 +38,21 @@ gpio-leds { compatible = "gpio-leds";
green {
green_led: led-0 { label = "rock:green:user1";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_LOW>; default-state = "off"; };
blue {
blue_led: led-1 { label = "rock:blue:user2";
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; default-state = "off"; };
sleep {
sleep_led: led-2 { label = "rock:red:power";
gpios = <&gpio0 15 0>;
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; };@@ -84,7 +74,7 @@
ir_recv: gpio-ir-receiver { compatible = "gpio-ir-receiver";
gpios = <&gpio0 10 1>;
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&ir_recv_pin>; };@@ -92,7 +82,7 @@ vcc_otg: usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high;
gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
gpio = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&otg_vbus_drv>; regulator-name = "otg-vbus";@@ -107,7 +97,7 @@ regulator-name = "sdmmc-supply"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_pwr>; startup-delay-us = <100000>;@@ -117,7 +107,7 @@ vcc_host: usb-host-regulator { compatible = "regulator-fixed"; enable-active-high;
gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "host-pwr";@@ -136,17 +126,6 @@ }; };
-&dmc {
rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x60x3 0x0 0x6 0x5 0xc 0x10 0x6 0x40x4 0x5 0x4 0x200 0x3 0xa 0x40 0x00x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x00x4 0x0>;rockchip,phy-timing = <0x208c6690 0x690878 0x10022a000x220 0x40 0x0 0x0>;rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>;-};
&emac { status = "okay";
@@ -159,12 +138,28 @@ phy0: ethernet-phy@0 { reg = <0>; interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
interrupts = <RK_PD2 IRQ_TYPE_LEVEL_LOW>; };};
&cpu0 {
cpu0-supply = <&vdd_arm>;
cpu-supply = <&vdd_arm>;+};
+&cpu1 {
cpu-supply = <&vdd_arm>;+};
+&cpu2 {
cpu-supply = <&vdd_arm>;+};
+&cpu3 {
cpu-supply = <&vdd_arm>;+};
+&gpu {
status = "okay";};
&i2c1 { @@ -175,7 +170,7 @@ compatible = "haoyu,hym8563"; reg = <0x51>; interrupt-parent = <&gpio0>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
interrupts = <RK_PB5 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&rtc_int>; #clock-cells = <0>;@@ -287,7 +282,6 @@ };
&mmc0 {
num-slots = <1>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>;@@ -318,40 +312,40 @@
act8846 { act8846_dvs0_ctl: act8846-dvs0-ctl {
rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
rockchip,pins = <3 RK_PD3 RK_FUNC_GPIO &pcfg_output_low>; }; }; hym8563 { rtc_int: rtc-int {
rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; lan8720a { phy_int: phy-int {
rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; }; }; ir-receiver { ir_recv_pin: ir-recv-pin {
rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; sd0 { sdmmc_pwr: sdmmc-pwr {
rockchip,pins = <RK_GPIO3 1 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb { host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; otg_vbus_drv: otg-vbus-drv {
rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>;
rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; }; };}; @@ -368,6 +362,10 @@ status = "okay"; };
+&uart2 {
status = "okay";+};
&uart3 { status = "okay"; }; -- 2.11.0
Johan Jonker jbx6244@gmail.com 于2021年6月25日周五 下午9:30写道：
In order to update the DT for rk3066 and rk3188 sync the clock dt-binding header. This is the state as of v5.12 in Linux.
Signed-off-by: Johan Jonker jbx6244@gmail.com Reviewed-by: Heiko Stuebner heiko@sntech.de
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
include/dt-bindings/clock/rk3188-cru-common.h | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 1e7931da0c..afad90680f 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /*
- Copyright (c) 2014 MundoReader S.L.
- Author: Heiko Stuebner heiko@sntech.de
@@ -59,12 +59,14 @@ #define ACLK_LCDC1 196 #define ACLK_GPU 197 #define ACLK_SMC 198 -#define ACLK_CIF 199 +#define ACLK_CIF1 199 #define ACLK_IPP 200 #define ACLK_RGA 201 #define ACLK_CIF0 202 #define ACLK_CPU 203 #define ACLK_PERI 204 +#define ACLK_VEPU 205 +#define ACLK_VDPU 206
/* pclk gates */ #define PCLK_GRF 320 @@ -125,8 +127,12 @@ #define HCLK_NANDC0 467 #define HCLK_CPU 468 #define HCLK_PERI 469 +#define HCLK_CIF1 470 +#define HCLK_VEPU 471 +#define HCLK_VDPU 472 +#define HCLK_HDMI 473
-#define CLK_NR_CLKS (HCLK_PERI + 1) +#define CLK_NR_CLKS (HCLK_HDMI + 1)
/* soft-reset indices */
#define SRST_MCORE 2
2.11.0
participants (3)
-
Alex Bee -
Johan Jonker -
Kever Yang