Modified the mmc_set_clock for exynos4. The goal of this patch is that fsys-div register should be reset. And restore the div-value, not using the value of lowlevel_init. (For using SDMMC4, this patch is needs)

Signed-off-by: Jaehoon Chung jh80.chung@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 2c2029a..5ebdda0 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) { struct exynos4_clock *clk = (struct exynos4_clock *)samsung_get_base_clock(); - unsigned int addr; + unsigned int addr, clear_bit, set_bit;

/* * CLK_DIV_FSYS1 @@ -877,20 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) * CLK_DIV_FSYS2 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] * CLK_DIV_FSYS3 - * MMC4_PRE_RATIO [15:8] + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] */ if (dev_index < 2) { addr = (unsigned int)&clk->div_fsys1; - } else if (dev_index == 4) { + clear_bit = 0xff << ((dev_index << 4) + 8); + set_bit = (div & 0xff) << ((dev_index << 4) + 8); + } else if (dev_index == 4) { addr = (unsigned int)&clk->div_fsys3; dev_index -= 4; + /* Clear all bit, and restore the MMC4_PRE_RATIO value wit div */ + clear_bit = 0xffff << dev_index; + set_bit = (div & 0xff) << (dev_index + 8); } else { addr = (unsigned int)&clk->div_fsys2; dev_index -= 2; + clear_bit = 0xff << ((dev_index << 4) + 8); + set_bit = (div & 0xff) << ((dev_index << 4) + 8); }

- clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8), - (div & 0xff) << ((dev_index << 4) + 8)); + clrsetbits_le32(addr, clear_bit, set_bit); }

/* exynos5: set the mmc clock */