[U-Boot] [PATCHv3 0/3] dm: pcie_fsl: Fix some issues
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The current driver is not working on some PowerPC T-series, P-series and MPC85xx platforms due to the difference in PCIe IP revisions and the various integration on different platforms. This patch set fixes these issues.
Hou Zhiqiang (3): dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef dm: pcie_fsl: Fix the Class Code fixup function dm: pcie_fsl: Fix the calculation of controller index
drivers/pci/pcie_fsl.c | 100 +++++++++++++++++++++++++---------------- drivers/pci/pcie_fsl.h | 10 +++++ 2 files changed, 71 insertions(+), 39 deletions(-)
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - New patch, also fix the build error which the #1 of v2 fixed.
drivers/pci/pcie_fsl.c | 69 ++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 33 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4d61a46cef..1879d8104c 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -299,8 +299,9 @@ static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx, out_be32(&pi->piwbear, 0); #endif
- if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A005434)) - flag = 0; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + flag = 0; +#endif
flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; if (pf) @@ -401,47 +402,47 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie)
fsl_pcie_init_atmu(pcie);
- if (IS_ENABLED(CONFIG_FSL_PCIE_DISABLE_ASPM)) { - val_32 = 0; - fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); - val_32 &= ~0x03; - fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); - udelay(1); - } +#ifdef CONFIG_FSL_PCIE_DISABLE_ASPM + val_32 = 0; + fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32); + val_32 &= ~0x03; + fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32); + udelay(1); +#endif
- if (IS_ENABLED(CONFIG_FSL_PCIE_RESET)) { - u16 ltssm; - int i; +#ifdef CONFIG_FSL_PCIE_RESET + u16 ltssm; + int i;
- if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + /* assert PCIe reset */ + setbits_be32(®s->pdb_stat, 0x08000000); + (void)in_be32(®s->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(®s->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + udelay(1000); + } else { + fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); + if (ltssm == 1) { /* assert PCIe reset */ setbits_be32(®s->pdb_stat, 0x08000000); (void)in_be32(®s->pdb_stat); - udelay(1000); + udelay(100); /* clear PCIe reset */ clrbits_be32(®s->pdb_stat, 0x08000000); asm("sync;isync"); - for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++) + for (i = 0; i < 100 && + !fsl_pcie_link_up(pcie); i++) udelay(1000); - } else { - fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, <ssm); - if (ltssm == 1) { - /* assert PCIe reset */ - setbits_be32(®s->pdb_stat, 0x08000000); - (void)in_be32(®s->pdb_stat); - udelay(100); - /* clear PCIe reset */ - clrbits_be32(®s->pdb_stat, 0x08000000); - asm("sync;isync"); - for (i = 0; i < 100 && - !fsl_pcie_link_up(pcie); i++) - udelay(1000); - } } } +#endif
- if (IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003) && - !fsl_pcie_link_up(pcie)) { +#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 + if (!fsl_pcie_link_up(pcie)) { serdes_corenet_t *srds_regs;
srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; @@ -460,13 +461,15 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) udelay(1000); } } +#endif
/* * The Read-Only Write Enable bit defaults to 1 instead of 0. * Set to 0 to protect the read-only registers. */ - if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A007815)) - clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815 + clrbits_be32(®s->dbi_ro_wr_en, 0x01); +#endif
/* * Enable All Error Interrupts except
On Tue, Aug 27, 2019 at 6:13 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- New patch, also fix the build error which the #1 of v2 fixed.
drivers/pci/pcie_fsl.c | 69 ++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 33 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Hi Bin,
Thanks a lot for your review!
Thanks, Zhiqiang
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月27日 20:55 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv3 1/3] dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef
On Tue, Aug 27, 2019 at 6:13 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
This can avoid build error: The macro in brackets of the IS_ENABLED(CONFIG_FOO) is only defined on the platforms that select the CONFIG_FOO, while it's not defined on platforms that do not select the CONFIG_FOO.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- New patch, also fix the build error which the #1 of v2 fixed.
drivers/pci/pcie_fsl.c | 69 ++++++++++++++++++++++-------------------- 1 file changed, 36 insertions(+), 33 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones.
This patch is to add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V3: - Refactor the classcode fixup function.
drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 1879d8104c..1be5063467 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -503,14 +503,23 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) { ccsr_fsl_pci_t *regs = pcie->regs; + u32 classcode_reg; u32 val;
- setbits_be32(®s->dbi_ro_wr_en, 0x01); - fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + classcode_reg = PCI_CLASS_REVISION; + setbits_be32(®s->dbi_ro_wr_en, 0x01); + } else { + classcode_reg = CSR_CLASSCODE; + } + + fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16; - fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); + + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) + clrbits_be32(®s->dbi_ro_wr_en, 0x01);
return 0; } diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 5eefc31fa9..032775ca05 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_
+/* GPEX CSR */ +#define CSR_CLASSCODE 0x474 + #ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70 #else
On Tue, Aug 27, 2019 at 6:13 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones.
This patch is to add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V3:
- Refactor the classcode fixup function.
drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index.
Fix it by adding the related info to the driver data structure.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V3: - No change.
drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | 7 +++++++ 2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 1be5063467..d3d2c191e5 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -582,6 +582,7 @@ static int fsl_pcie_probe(struct udevice *dev) static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) { struct fsl_pcie *pcie = dev_get_priv(dev); + struct fsl_pcie_data *info; int ret;
pcie->regs = dev_remap_addr(dev); @@ -596,7 +597,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) return ret; }
- pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + info = (struct fsl_pcie_data *)dev_get_driver_data(dev); + pcie->info = info; + pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) - + info->block_offset) / info->stride;
return 0; } @@ -606,8 +610,14 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, };
+static struct fsl_pcie_data t2080_data = { + .block_offset = 0x240000, + .block_offset_mask = 0x3fffff, + .stride = 0x10000, +}; + static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-t2080" }, + { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { } };
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 032775ca05..dc8368d559 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -43,6 +43,12 @@ #define LTSSM_L0_REV3 0x11 #define LTSSM_L0 0x16
+struct fsl_pcie_data { + u32 block_offset; /* Offset from CCSR of 1st controller */ + u32 block_offset_mask; /* Mask out the CCSR base */ + u32 stride; /* Offset stride between controllers */ +}; + struct fsl_pcie { int idx; struct udevice *bus; @@ -52,6 +58,7 @@ struct fsl_pcie { bool mode; /* RC&EP mode flag */ bool enabled; /* Enable status */ struct list_head list; + struct fsl_pcie_data *info; };
extern struct list_head fsl_pcie_list;
-----Original Message----- From: Z.q. Hou Sent: Tuesday, August 27, 2019 3:44 PM To: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; bmeng.cn@gmail.com Cc: Z.q. Hou zhiqiang.hou@nxp.com Subject: [PATCHv3 0/3] dm: pcie_fsl: Fix some issues
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The current driver is not working on some PowerPC T-series, P-series and MPC85xx platforms due to the difference in PCIe IP revisions and the various integration on different platforms. This patch set fixes these issues.
Hou Zhiqiang (3): dm: pcie_fsl: Convert IS_ENABLED() run-time checking to #ifdef dm: pcie_fsl: Fix the Class Code fixup function dm: pcie_fsl: Fix the calculation of controller index
This patch series has been applied to u-boot-mpc85xx, awaiting upstream.
--pk
participants (3)
-
Bin Meng -
Prabhakar Kushwaha -
Z.q. Hou