[U-Boot] [PATCH 1/3] stm32f429: pass the device unique ID in DTB
Read device unique ID and set environment variable "serial#". Value would then be passed to kernel through DTB.
To read ID from DTB, kernel is required to have commit: 3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo) This commit is already mainline since v4.1-rc1.
Signed-off-by: Antonio Borneo borneo.antonio@gmail.com To: Albert Aribaud albert.u.boot@aribaud.net To: Tom Rini trini@konsulko.com To: Kamil Lulko rev13@wp.pl Cc: u-boot@lists.denx.de --- arch/arm/include/asm/arch-stm32f4/stm32.h | 10 ++++++++++ board/st/stm32f429-discovery/stm32f429-discovery.c | 19 +++++++++++++++++++ include/configs/stm32f429-discovery.h | 1 + 3 files changed, 30 insertions(+)
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index a9f88db..3ed3801 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -14,6 +14,7 @@ /* * Peripheral memory map */ +#define STM32_SYSMEM_BASE 0x1FFF0000 #define STM32_PERIPH_BASE 0x40000000 #define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) @@ -25,6 +26,12 @@ /* * Register maps */ +struct stm32_u_id_regs { + u32 u_id_low; + u32 u_id_mid; + u32 u_id_high; +}; + struct stm32_rcc_regs { u32 cr; /* RCC clock control */ u32 pllcfgr; /* RCC PLL configuration */ @@ -78,6 +85,9 @@ struct stm32_flash_regs { /* * Registers access macros */ +#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) +#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) + #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) #define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 2dd5d93..f418186 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -285,3 +285,22 @@ int board_init(void)
return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char serialno[25]; + uint32_t u_id_low, u_id_mid, u_id_high; + + if (!getenv("serial#")) { + u_id_low = readl(&STM32_U_ID->u_id_low); + u_id_mid = readl(&STM32_U_ID->u_id_mid); + u_id_high = readl(&STM32_U_ID->u_id_high); + sprintf(serialno, "%08x%08x%08x", + u_id_high, u_id_mid, u_id_low); + setenv("serial#", serialno); + } + + return 0; +} +#endif diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 1b4fd21..4cc7324 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -15,6 +15,7 @@ #define CONFIG_OF_LIBFDT
#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_FLASH_BASE 0x08000000
While most stm32f4 run at 168 MHz, stm32f429 can work till 180 MHz. Add option to select 180 MHz through macro CONFIG_SYS_CLK_FREQ.
Signed-off-by: Antonio Borneo borneo.antonio@gmail.com To: Albert Aribaud albert.u.boot@aribaud.net To: Tom Rini trini@konsulko.com To: Kamil Lulko rev13@wp.pl Cc: u-boot@lists.denx.de --- arch/arm/cpu/armv7m/stm32f4/clock.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c index 2eded1f..d520a13 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/cpu/armv7m/stm32f4/clock.c @@ -92,7 +92,20 @@ struct pll_psc { #error "CONFIG_STM32_HSE_HZ not defined!" #else #if (CONFIG_STM32_HSE_HZ == 8000000) -struct pll_psc pll_psc_168 = { +#if (CONFIG_SYS_CLK_FREQ == 180000000) +/* 180 MHz */ +struct pll_psc sys_pll_psc = { + .pll_m = 8, + .pll_n = 360, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2 +}; +#else +/* default 168 MHz */ +struct pll_psc sys_pll_psc = { .pll_m = 8, .pll_n = 336, .pll_p = 2, @@ -101,6 +114,7 @@ struct pll_psc pll_psc_168 = { .apb1_psc = APB_PSC_4, .apb2_psc = APB_PSC_2 }; +#endif #else #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" #endif @@ -122,19 +136,19 @@ int configure_clocks(void) while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) ;
- /* Enable high performance mode, System frequency up to 168 MHz */ + /* Enable high performance mode, System frequency up to 180 MHz */ setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
setbits_le32(&STM32_RCC->cfgr, (( - pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT) - | (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT) - | (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); - - writel(pll_psc_168.pll_m - | (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT) - | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) - | (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), + sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) + | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) + | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); + + writel(sys_pll_psc.pll_m + | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT) + | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) + | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), &STM32_RCC->pllcfgr); setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
On Sun, Jul 19, 2015 at 10:19:47PM +0800, Antonio Borneo wrote:
While most stm32f4 run at 168 MHz, stm32f429 can work till 180 MHz. Add option to select 180 MHz through macro CONFIG_SYS_CLK_FREQ.
Signed-off-by: Antonio Borneo borneo.antonio@gmail.com To: Albert Aribaud albert.u.boot@aribaud.net To: Tom Rini trini@konsulko.com To: Kamil Lulko rev13@wp.pl Cc: u-boot@lists.denx.de
Applied to u-boot/master, thanks!
Mainline Linux kernel commit 338a6aaabc02fa63b70441dd0e1b70aea64673c6 (ARM: dts: Introduce STM32F429 MCU) in arch/arm/boot/dts/stm32f429.dtsi requires U-Boot to set system clock to 180 MHz.
Signed-off-by: Antonio Borneo borneo.antonio@gmail.com To: Albert Aribaud albert.u.boot@aribaud.net To: Tom Rini trini@konsulko.com To: Kamil Lulko rev13@wp.pl Cc: u-boot@lists.denx.de --- include/configs/stm32f429-discovery.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 4cc7324..5f1f453 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -62,6 +62,8 @@
#define CONFIG_STM32_HSE_HZ 8000000
+#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */ + #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
#define CONFIG_CMDLINE_TAG
On Sun, Jul 19, 2015 at 10:19:48PM +0800, Antonio Borneo wrote:
Mainline Linux kernel commit 338a6aaabc02fa63b70441dd0e1b70aea64673c6 (ARM: dts: Introduce STM32F429 MCU) in arch/arm/boot/dts/stm32f429.dtsi requires U-Boot to set system clock to 180 MHz.
Signed-off-by: Antonio Borneo borneo.antonio@gmail.com To: Albert Aribaud albert.u.boot@aribaud.net To: Tom Rini trini@konsulko.com To: Kamil Lulko rev13@wp.pl Cc: u-boot@lists.denx.de
Applied to u-boot/master, thanks!
On Sun, Jul 19, 2015 at 10:19:46PM +0800, Antonio Borneo wrote:
Read device unique ID and set environment variable "serial#". Value would then be passed to kernel through DTB.
To read ID from DTB, kernel is required to have commit: 3f599875e5202986b350618a617527ab441bf206 (ARM: 8355/1: arch: Show the serial number from devicetree in cpuinfo) This commit is already mainline since v4.1-rc1.
Signed-off-by: Antonio Borneo borneo.antonio@gmail.com To: Albert Aribaud albert.u.boot@aribaud.net To: Tom Rini trini@konsulko.com To: Kamil Lulko rev13@wp.pl Cc: u-boot@lists.denx.de
Applied to u-boot/master, thanks!
participants (2)
-
Antonio Borneo -
Tom Rini