On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:

The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

arch/riscv/lib/bootm.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6662aff..754bbff 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob)

int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) {

• bd_t *bd = gd->bd;
• char *s;
• int machid = bd->bi_arch_number;
• void (*theKernel)(int arch, uint params);

• void (*kernel)(int hart, uint dtb);

This probably does not cause any issues in u-boot, but the second parameter should be 32 bit or 64 bit depending on the architecture. Since you are already changing the kernel arguments it would make sense to also change dtb from uint to ulong or void *.

/* * allow the PREP bootm subcommand, it is required for bootm to work @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1;

• theKernel = (void (*)(int, uint))images->ep;
• s = env_get("machid");
• if (s) {

• machid = simple_strtoul(s, NULL, 16);
  

• printf("Using machid 0x%x from environment\n", machid);
  

• }

• kernel = (void (*)(int, uint))images->ep;

  bootstage_mark(BOOTSTAGE_ID_RUN_OS);

  debug("## Transferring control to Linux (at address %08lx)

...\n",

•       (ulong)theKernel);
  

•       (ulong)kernel);
  
  

  if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {

#ifdef CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) printf("\nStarting kernel ...\n\n");

cleanup_before_linux();

• /* TODO: hardcode the hart id to zero for now */ if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)

• theKernel(machid, (unsigned long)images->ft_addr);
  

• kernel(0, (unsigned long)images->ft_addr);
  
  

You can use the mhartid CSR to get the hart id. This will limit u-boot to running in machine mode however. Alternatively you can also use the hart id, which is passed in a0 by the bootloader.

Thanks, Lukas

/* does not return */

Hi Bin,

On Thu, 2018-09-06 at 10:57 +0800, Bin Meng wrote:

Hi Lukas,

On Tue, Sep 4, 2018 at 5:41 AM Auer, Lukas lukas.auer@aisec.fraunhofer.de wrote:

...

On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:

...

The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

arch/riscv/lib/bootm.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 6662aff..754bbff 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -25,10 +25,7 @@ int arch_fixup_fdt(void *blob)

int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) {

• bd_t    *bd = gd->bd;
  

• char    *s;
  

• int     machid = bd->bi_arch_number;
  

• void    (*theKernel)(int arch, uint params);
  

• void    (*kernel)(int hart, uint dtb);
  

This probably does not cause any issues in u-boot, but the second parameter should be 32 bit or 64 bit depending on the architecture. Since you are already changing the kernel arguments it would make sense to also change dtb from uint to ulong or void *.

Yes. Will address this in v2.

...

...

  /*
   * allow the PREP bootm subcommand, it is required for

bootm to work @@ -39,18 +36,12 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1;

• theKernel = (void (*)(int, uint))images->ep;
  

• s = env_get("machid");
  

• if (s) {
  

•         machid = simple_strtoul(s, NULL, 16);
  

•         printf("Using machid 0x%x from environment\n",
  

machid);

• }
  

• kernel = (void (*)(int, uint))images->ep;
  
  bootstage_mark(BOOTSTAGE_ID_RUN_OS);
  
  debug("## Transferring control to Linux (at address %08lx)
  

...\n",

•        (ulong)theKernel);
  

•        (ulong)kernel);
  
  if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) {
  

#ifdef CONFIG_OF_LIBFDT @@ -66,8 +57,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) printf("\nStarting kernel ...\n\n");

  cleanup_before_linux();

• /* TODO: hardcode the hart id to zero for now */
  if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len)
  

•         theKernel(machid, (unsigned long)images->ft_addr);
  

•         kernel(0, (unsigned long)images->ft_addr);
  
  

You can use the mhartid CSR to get the hart id. This will limit u- boot to running in machine mode however. Alternatively you can also use the hart id, which is passed in a0 by the bootloader.

If the goal is to use U-Boot to directly boot Linux, I think we need more changes. I believe we should allow only one hart to execute this function. For other harts, they should be waked up and jump to kernel directly.

Yes, that's true. We should be able to pick which hart executes it though. This is useful for chips like SiFive's U54, where hart 0 is a smaller hart for monitoring tasks. Here it would make sense to run u-boot on one of the other harts.

Thanks, Lukas

On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:

This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

arch/riscv/Makefile | 1 + arch/riscv/cpu/Makefile | 5 ++ arch/riscv/cpu/cpu.c | 49 +++++++++++++++++ arch/riscv/include/asm/csr.h | 124 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 179 insertions(+) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/include/asm/csr.h

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 084888a..af432e1 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,5 +5,6 @@

head-y := arch/riscv/cpu/$(CPU)/start.o

+libs-y += arch/riscv/cpu/ libs-y += arch/riscv/cpu/$(CPU)/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile new file mode 100644 index 0000000..63de163 --- /dev/null +++ b/arch/riscv/cpu/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com

+obj-y += cpu.o diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c new file mode 100644 index 0000000..ae57fb8 --- /dev/null +++ b/arch/riscv/cpu/cpu.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
• */

+#include <common.h> +#include <asm/csr.h>

+enum {

• ISA_INVALID = 0,
• ISA_32BIT,
• ISA_64BIT,
• ISA_128BIT

+};

+static const char * const isa_bits[] = {

• [ISA_INVALID] = NULL,
• [ISA_32BIT] = "32",
• [ISA_64BIT] = "64",
• [ISA_128BIT] = "128"

+};

+static inline bool supports_extension(char ext) +{

• return csr_read(misa) & (1 << (ext - 'a'));

+}

+int print_cpuinfo(void) +{

• char name[32];
• char *s = name;
• int bit;
• s += sprintf(name, "rv");
• bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
• s += sprintf(s, isa_bits[bit]);
• supports_extension('i') ? *s++ = 'i' : 'r';
• supports_extension('m') ? *s++ = 'm' : 'i';
• supports_extension('a') ? *s++ = 'a' : 's';
• supports_extension('f') ? *s++ = 'f' : 'c';
• supports_extension('d') ? *s++ = 'd' : '-';
• supports_extension('c') ? *s++ = 'c' : 'v';
• *s++ = '\0';
• printf("CPU: %s\n", name);
• return 0;

+} diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index 0000000..50fccea --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (C) 2015 Regents of the University of California
• • Taken from Linux arch/riscv/include/asm/csr.h
• */

+#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H

+/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */

+#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL)

+#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL)

+#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif

+/* SATP flags */ +#if __riscv_xlen == 32 +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#endif

+/* Interrupt Enable and Interrupt Pending flags */ +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */

+#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15

+#ifndef __ASSEMBLY__

+#define csr_swap(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val); \
• __asm__ __volatile__ ("csrrw %0, " #csr ", %1" \

• 	      : "=r" (__v) : "rK" (__v)		\
  

• 	      : "memory");			\
  

• __v; \

+})

+#define csr_read(csr) \ +({ \

• register unsigned long __v; \
• __asm__ __volatile__ ("csrr %0, " #csr \

• 	      : "=r" (__v) :			\
  

• 	      : "memory");			\
  

• __v; \

+})

+#define csr_write(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val); \
• __asm__ __volatile__ ("csrw " #csr ", %0" \

• 	      : : "rK" (__v)			\
  

• 	      : "memory");			\
  

+})

+#define csr_read_set(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val); \
• __asm__ __volatile__ ("csrrs %0, " #csr ", %1" \

• 	      : "=r" (__v) : "rK" (__v)		\
  

• 	      : "memory");			\
  

• __v; \

+})

+#define csr_set(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val); \
• __asm__ __volatile__ ("csrs " #csr ", %0" \

• 	      : : "rK" (__v)			\
  

• 	      : "memory");			\
  

+})

+#define csr_read_clear(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val); \
• __asm__ __volatile__ ("csrrc %0, " #csr ", %1" \

• 	      : "=r" (__v) : "rK" (__v)		\
  

• 	      : "memory");			\
  

• __v; \

+})

+#define csr_clear(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val); \
• __asm__ __volatile__ ("csrc " #csr ", %0" \

• 	      : : "rK" (__v)			\
  

• 	      : "memory");			\
  

+})

+#endif /* __ASSEMBLY__ */

+#endif /* _ASM_RISCV_CSR_H */

The RISC-V arch already has functions for accessing CSRs in encoding.h. I don't think it makes sense to keep both versions. I would tend towards keeping this version since this allows us to just sync with the Linux kernel if there are any changes.

Thanks, Lukas

Hi Bin,

On Thu, 2018-09-06 at 11:03 +0800, Bin Meng wrote:

Hi Lukas,

On Tue, Sep 4, 2018 at 5:42 AM Auer, Lukas lukas.auer@aisec.fraunhofer.de wrote:

...

On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:

...

This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

arch/riscv/Makefile | 1 + arch/riscv/cpu/Makefile | 5 ++ arch/riscv/cpu/cpu.c | 49 +++++++++++++++++ arch/riscv/include/asm/csr.h | 124 +++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 179 insertions(+) create mode 100644 arch/riscv/cpu/Makefile create mode 100644 arch/riscv/cpu/cpu.c create mode 100644 arch/riscv/include/asm/csr.h

diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 084888a..af432e1 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -5,5 +5,6 @@

head-y := arch/riscv/cpu/$(CPU)/start.o

+libs-y += arch/riscv/cpu/ libs-y += arch/riscv/cpu/$(CPU)/ libs-y += arch/riscv/lib/ diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile new file mode 100644 index 0000000..63de163 --- /dev/null +++ b/arch/riscv/cpu/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com

+obj-y += cpu.o diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c new file mode 100644 index 0000000..ae57fb8 --- /dev/null +++ b/arch/riscv/cpu/cpu.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
• */

+#include <common.h> +#include <asm/csr.h>

+enum {

• ISA_INVALID = 0,
  

• ISA_32BIT,
  

• ISA_64BIT,
  

• ISA_128BIT
  

+};

+static const char * const isa_bits[] = {

• [ISA_INVALID] = NULL,
  

• [ISA_32BIT]   = "32",
  

• [ISA_64BIT]   = "64",
  

• [ISA_128BIT]  = "128"
  

+};

+static inline bool supports_extension(char ext) +{

• return csr_read(misa) & (1 << (ext - 'a'));
  

+}

+int print_cpuinfo(void) +{

• char name[32];
  

• char *s = name;
  

• int bit;
  

• s += sprintf(name, "rv");
  

• bit = csr_read(misa) >> (sizeof(long) * 8 - 2);
  

• s += sprintf(s, isa_bits[bit]);
  

• supports_extension('i') ? *s++ = 'i' : 'r';
  

• supports_extension('m') ? *s++ = 'm' : 'i';
  

• supports_extension('a') ? *s++ = 'a' : 's';
  

• supports_extension('f') ? *s++ = 'f' : 'c';
  

• supports_extension('d') ? *s++ = 'd' : '-';
  

• supports_extension('c') ? *s++ = 'c' : 'v';
  

• *s++ = '\0';
  

• printf("CPU:   %s\n", name);
  

• return 0;
  

+} diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h new file mode 100644 index 0000000..50fccea --- /dev/null +++ b/arch/riscv/include/asm/csr.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (C) 2015 Regents of the University of California
• • Taken from Linux arch/riscv/include/asm/csr.h
• */

+#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H

+/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor access User Memory */

+#define SR_FS _AC(0x00006000, UL) /* Floating- point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL)

+#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL)

+#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif

+/* SATP flags */ +#if __riscv_xlen == 32 +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#endif

+/* Interrupt Enable and Interrupt Pending flags */ +#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */ +#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */

+#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15

+#ifndef __ASSEMBLY__

+#define csr_swap(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val);               \
  

• __asm__ __volatile__ ("csrrw %0, " #csr ", %1"          \
  

•                       : "=r" (__v) : "rK" (__v)         \
  

•                       : "memory");                      \
  

• __v;                                                    \
  

+})

+#define csr_read(csr) \ +({ \

• register unsigned long __v;                             \
  

• __asm__ __volatile__ ("csrr %0, " #csr                  \
  

•                       : "=r" (__v) :                    \
  

•                       : "memory");                      \
  

• __v;                                                    \
  

+})

+#define csr_write(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val);               \
  

• __asm__ __volatile__ ("csrw " #csr ", %0"               \
  

•                       : : "rK" (__v)                    \
  

•                       : "memory");                      \
  

+})

+#define csr_read_set(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val);               \
  

• __asm__ __volatile__ ("csrrs %0, " #csr ", %1"          \
  

•                       : "=r" (__v) : "rK" (__v)         \
  

•                       : "memory");                      \
  

• __v;                                                    \
  

+})

+#define csr_set(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val);               \
  

• __asm__ __volatile__ ("csrs " #csr ", %0"               \
  

•                       : : "rK" (__v)                    \
  

•                       : "memory");                      \
  

+})

+#define csr_read_clear(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val);               \
  

• __asm__ __volatile__ ("csrrc %0, " #csr ", %1"          \
  

•                       : "=r" (__v) : "rK" (__v)         \
  

•                       : "memory");                      \
  

• __v;                                                    \
  

+})

+#define csr_clear(csr, val) \ +({ \

• unsigned long __v = (unsigned long)(val);               \
  

• __asm__ __volatile__ ("csrc " #csr ", %0"               \
  

•                       : : "rK" (__v)                    \
  

•                       : "memory");                      \
  

+})

+#endif /* __ASSEMBLY__ */

+#endif /* _ASM_RISCV_CSR_H */

The RISC-V arch already has functions for accessing CSRs in encoding.h. I don't think it makes sense to keep both versions. I would tend towards keeping this version since this allows us to just sync with the Linux kernel if there are any changes.

Thanks for pointing out. But I checked current Linux tree, and there is no encoding.h. Maybe encoding.h was from some old kernel tree? I can clean this up and leaving only csr.h in v2.

Regards, Bin

Sorry, I meant that encoding.h is in the u-boot RISC-V arch ( arch/riscv/include/asm/encoding.h). I think it's from bbl.

Thanks, Lukas

On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:

This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet.

For your information and to avoid duplicate work, I am working on a patch set that improves RISC-V support in u-boot. I am currently able to boot Linux on a multi-core setup in QEMU, but they are not quite ready to submit yet.

Thank you for your patches, it's great to see better support for RISC-V in u-boot! I will add a few comments based on what I have learned so far from working with u-boot on RISC-V.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

---

arch/riscv/Kconfig | 4 +++ arch/riscv/cpu/qemu/Makefile | 6 +++++ arch/riscv/cpu/qemu/cpu.c | 29 +++++++++++++++++++++ arch/riscv/cpu/qemu/dram.c | 17 ++++++++++++ board/emulation/qemu-riscv/Kconfig | 21 +++++++++++++++ board/emulation/qemu-riscv/MAINTAINERS | 7 +++++ board/emulation/qemu-riscv/Makefile | 5 ++++ board/emulation/qemu-riscv/qemu-riscv.c | 23 +++++++++++++++++ configs/qemu-riscv32_defconfig | 10 +++++++ configs/qemu-riscv64_defconfig | 11 ++++++++ doc/README.qemu-riscv | 46 +++++++++++++++++++++++++++++++++ include/configs/qemu-riscv.h | 21 +++++++++++++++ 12 files changed, 200 insertions(+) create mode 100644 arch/riscv/cpu/qemu/Makefile create mode 100644 arch/riscv/cpu/qemu/cpu.c create mode 100644 arch/riscv/cpu/qemu/dram.c create mode 100644 board/emulation/qemu-riscv/Kconfig create mode 100644 board/emulation/qemu-riscv/MAINTAINERS create mode 100644 board/emulation/qemu-riscv/Makefile create mode 100644 board/emulation/qemu-riscv/qemu-riscv.c create mode 100644 configs/qemu-riscv32_defconfig create mode 100644 configs/qemu-riscv64_defconfig create mode 100644 doc/README.qemu-riscv create mode 100644 include/configs/qemu-riscv.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 49f87de..168ca3d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,9 +11,13 @@ choice config TARGET_AX25_AE350 bool "Support ax25-ae350"

+config TARGET_QEMU_VIRT

• bool "Support QEMU Virt Board"

endchoice

source "board/AndesTech/ax25-ae350/Kconfig" +source "board/emulation/qemu-riscv/Kconfig"

choice prompt "CPU selection" diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/qemu/Makefile new file mode 100644 index 0000000..258e462 --- /dev/null +++ b/arch/riscv/cpu/qemu/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com

+obj-y += dram.o +obj-y += cpu.o diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/qemu/cpu.c new file mode 100644 index 0000000..a064639 --- /dev/null +++ b/arch/riscv/cpu/qemu/cpu.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
• */

+#include <common.h> +#include <command.h>

+/*

• • cleanup_before_linux() is called just before we call linux
• • it prepares the processor for linux
• • we disable interrupt and caches.
• */

+int cleanup_before_linux(void) +{

• disable_interrupts();
• /* turn off I/D-cache */
• return 0;

+}

+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{

• printf("reset unsupported yet\n");
• return 0;

+}

We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).

diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/qemu/dram.c new file mode 100644 index 0000000..84d87d2 --- /dev/null +++ b/arch/riscv/cpu/qemu/dram.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
• */

+#include <common.h> +#include <fdtdec.h>

+int dram_init(void) +{

• return fdtdec_setup_mem_size_base();

+}

+int dram_init_banksize(void) +{

• return fdtdec_setup_memory_banksize();

+} diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig new file mode 100644 index 0000000..029f5efb --- /dev/null +++ b/board/emulation/qemu-riscv/Kconfig @@ -0,0 +1,21 @@ +if TARGET_QEMU_VIRT

+config SYS_BOARD

• default "qemu-riscv"

+config SYS_VENDOR

• default "emulation"

+config SYS_CPU

• default "qemu"

+config SYS_CONFIG_NAME

• default "qemu-riscv"

+config SYS_TEXT_BASE

• default 0x80000000

+config BOARD_SPECIFIC_OPTIONS # dummy

• def_bool y

+endif diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS new file mode 100644 index 0000000..3c6eb4f --- /dev/null +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -0,0 +1,7 @@ +QEMU RISC-V 'VIRT' BOARD +M: Bin Meng bmeng.cn@gmail.com +S: Maintained +F: board/emulation/qemu-riscv/ +F: include/configs/qemu-riscv.h +F: configs/qemu-riscv32_defconfig +F: configs/qemu-riscv64_defconfig diff --git a/board/emulation/qemu-riscv/Makefile b/board/emulation/qemu-riscv/Makefile new file mode 100644 index 0000000..3f29b90 --- /dev/null +++ b/board/emulation/qemu-riscv/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com

+obj-y += qemu-riscv.o diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c new file mode 100644 index 0000000..041e716 --- /dev/null +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
• */

+#include <common.h> +#include <fdtdec.h>

+#define MROM_FDT_ADDR 0x1020

This value is not specified anywhere, so it could change without prior warning. The value is also passed in a1 by ROM. If you want I can update the code to use this value when I submit my patches.

Thanks, Lukas

+int board_init(void) +{

• return 0;

+}

+void *board_fdt_blob_setup(void) +{

• /*

• * QEMU loads a generated DTB for us immediately
  

• * after the reset vectors in the MROM
  

• */
  

• return (void *)MROM_FDT_ADDR;

+} diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu- riscv32_defconfig new file mode 100644 index 0000000..cbd2c91 --- /dev/null +++ b/configs/qemu-riscv32_defconfig @@ -0,0 +1,10 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_OF_BOARD=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_TIMER=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu- riscv64_defconfig new file mode 100644 index 0000000..af8b307 --- /dev/null +++ b/configs/qemu-riscv64_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_CPU_RISCV_64=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_OF_BOARD=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_TIMER=y diff --git a/doc/README.qemu-riscv b/doc/README.qemu-riscv new file mode 100644 index 0000000..e2e4804 --- /dev/null +++ b/doc/README.qemu-riscv @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com

+U-Boot on QEMU's 'virt' machine on RISC-V +=========================================

+QEMU for RISC-V supports a special 'virt' machine designed for emulation and +virtualization purposes. This document describes how to run U-Boot under it. +Both 32-bit 64-bit targets are supported.

+The QEMU virt machine models a generic RISC-V virtual machine with support for +the VirtIO standard networking and block storage devices. It has CLINT, PLIC, +16550A UART devices in addition to VirtIO and it also uses device- tree to pass +configuration information to guest software. It implements RISC-V privileged +architecture spec v1.10.

+Building U-Boot +--------------- +Set the CROSS_COMPILE environment variable as usual, and run:

+- For 32-bit RISC-V:

• make qemu-riscv32_defconfig
• make

+- For 64-bit RISC-V:

• make qemu-riscv64_defconfig
• make

+Running U-Boot +-------------- +The minimal QEMU command line to get U-Boot up and running is:

+- For 32-bit RISC-V:

• qemu-system-riscv32 -nographic -machine virt -kernel u-boot

+- For 64-bit RISC-V:

• qemu-system-riscv64 -nographic -machine virt -kernel u-boot

+The commands above create targets with 128MiB memory by default. +A freely configurable amount of RAM can be created via the '-m' +parameter. For example, '-m 2G' creates 2GiB memory for the target, +and the memory node in the embedded DTB created by QEMU reflects +the new setting.

+These have been tested in QEMU 3.0.0. diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu- riscv.h new file mode 100644 index 0000000..d279c23 --- /dev/null +++ b/include/configs/qemu-riscv.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright (C) 2018, Bin Meng bmeng.cn@gmail.com
• */

+#ifndef __CONFIG_H +#define __CONFIG_H

+#include <linux/sizes.h>

+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE

• SZ_2M)

+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)

+#define CONFIG_SYS_MALLOC_LEN SZ_8M

+/* Environment options */ +#define CONFIG_ENV_SIZE SZ_4K

+#endif /* __CONFIG_H */