This patch adds support for Odroid-XU3.

Change-Id: Ia45d119a62b126f2328684485b8c372ba6acbe00 Signed-off-by: Hyungwon Hwang human.hwang@samsung.com --- arch/arm/cpu/armv7/exynos/Kconfig | 4 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 72 ++++++++++ board/samsung/odroid-xu3/Kconfig | 12 ++ board/samsung/odroid-xu3/MAINTAINERS | 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 132 ++++++++++++++++++ board/samsung/odroid-xu3/setup.h | 123 +++++++++++++++++ configs/odroid-xu3_defconfig | 4 + include/configs/odroid_xu3.h | 243 ++++++++++++++++++++++++++++++++++ 10 files changed, 605 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h

diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 3a25fee..a47cb34 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -22,6 +22,9 @@ config TARGET_TRATS2 config TARGET_ODROID bool "Exynos4412 Odroid board"

+config TARGET_ODROID_XU3 + bool "Exynos5422 Odroid board" + config TARGET_ARNDALE bool "Exynos5250 Arndale board" select OF_CONTROL if !SPL_BUILD @@ -60,6 +63,7 @@ source "board/samsung/universal_c210/Kconfig" source "board/samsung/origen/Kconfig" source "board/samsung/trats2/Kconfig" source "board/samsung/odroid/Kconfig" +source "board/samsung/odroid-xu3/Kconfig" source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 2dcfcc0..66191f9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5420-smdk5420.dtb \ exynos5420-peach-pit.dtb \ - exynos5800-peach-pi.dtb + exynos5800-peach-pi.dtb \ + exynos5422-odroidxu3.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ tegra20-paz00.dtb \ diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644 index 0000000..34f52c6 --- /dev/null +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -0,0 +1,72 @@ +/* + * Odroid XU3 device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos54xx.dtsi" + +/ { + model = "Odroid XU3 based on EXYNOS5422"; + compatible = "samsung,odroidxu3", "samsung,exynos5"; + + config { + hwid = "smdk5420 TEST A-A 9382"; + }; + + aliases { + serial0 = "/serial@12C00000"; + console = "/serial@12C20000"; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000 + 0x80000000 0x10000000 + 0x90000000 0x10000000 + 0xa0000000 0x10000000 + 0xb0000000 0xea00000>; + }; + + serial@12C20000 { + status="okay"; + }; + + /* s2mps11 is on i2c bus 4 */ + i2c@12ca0000 { + #address-cells = <1>; + #size-cells = <0>; + pmic@66 { + reg = <0x66>; + compatible = "samsung,s2mps11-pmic"; + }; + }; + + mmc@12200000 { + samsung,bus-width = <8>; + samsung,timing = <1 3 3>; + samsung,removable = <0>; + samsung,pre-init; + }; + + mmc@12210000 { + status = "disabled"; + }; + + mmc@12220000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + samsung,removable = <1>; + }; + + mmc@12230000 { + status = "disabled"; + }; +}; diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig new file mode 100644 index 0000000..6159692 --- /dev/null +++ b/board/samsung/odroid-xu3/Kconfig @@ -0,0 +1,12 @@ +if TARGET_ODROID_XU3 + +config SYS_BOARD + default "odroid-xu3" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "odroid_xu3" + +endif diff --git a/board/samsung/odroid-xu3/MAINTAINERS b/board/samsung/odroid-xu3/MAINTAINERS new file mode 100644 index 0000000..50cf928 --- /dev/null +++ b/board/samsung/odroid-xu3/MAINTAINERS @@ -0,0 +1,6 @@ +ODROID-XU3 BOARD +M: Hyungwon Hwang human.hwang@samsung.com +S: Maintained +F: board/samsung/odroid-xu3/ +F: include/configs/odroid_xu3.h +F: configs/odroid-xu3_defconfig diff --git a/board/samsung/odroid-xu3/Makefile b/board/samsung/odroid-xu3/Makefile new file mode 100644 index 0000000..85ae5c5 --- /dev/null +++ b/board/samsung/odroid-xu3/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid-xu3.o diff --git a/board/samsung/odroid-xu3/odroid-xu3.c b/board/samsung/odroid-xu3/odroid-xu3.c new file mode 100644 index 0000000..f054e4e --- /dev/null +++ b/board/samsung/odroid-xu3/odroid-xu3.c @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/power.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sromc.h> + +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int get_board_rev(void) +{ + unsigned int rev = 0; + return rev; +} + +int exynos_init(void) +{ + return 0; +} + +static int board_clock_init(void) +{ + unsigned int set, clr, clr_src_cpu, clr_pll_con0; + struct exynos5420_clock *clk = (struct exynos5420_clock *) + samsung_get_base_clock(); + /* + * CMU_CPU clocks src to MPLL + * Bit values: 0 ; 1 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL + */ + + /* Set CMU_CPU clocks src to OSCCLK */ + clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1); + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1); + + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + /* Set APLL to 1200MHz */ + clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1) | + PLL_ENABLE(1); + set = SDIV(0) | PDIV(2) | MDIV(100) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); + + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CMU_CPU clocks src to APLL */ + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0); + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + while (MUX_STAT_CPU_CHANGING(readl(&clk->mux_stat_cpu))) + continue; + + clr = ARM_RATIO(7) | CPUD_RATIO(7) | ATB_RATIO(7) | + PCLK_DBG_RATIO(7) | APLL_RATIO(7) | ARM2_RATIO(7); + set = ARM_RATIO(0) | CPUD_RATIO(2) | ATB_RATIO(5) | + PCLK_DBG_RATIO(5) | APLL_RATIO(0) | ARM2_RATIO(0); + + clrsetbits_le32(&clk->div_cpu0, clr, set); + + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) + continue; + + /* Set MPLL to 800MHz */ + set = SDIV(1) | PDIV(3) | MDIV(200) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); + + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CLKMUX_UART src to MPLL */ + clr = UART0_SEL(7) | UART1_SEL(7) | UART2_SEL(7) | UART3_SEL(7); + set = UART0_SEL(3) | UART1_SEL(3) | UART2_SEL(3) | UART3_SEL(3); + + clrsetbits_le32(&clk->src_peric0, clr, set); + + /* Set SCLK_UART to 400 MHz (MPLL / 2) */ + clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | + UART3_RATIO(15); + set = UART0_RATIO(1) | UART1_RATIO(1) | UART2_RATIO(1) | + UART3_RATIO(1); + + clrsetbits_le32(&clk->div_peric0, clr, set); + + while (readl(&clk->div_stat_peric0) & DIV_STAT_PERIC0_CHANGING) + continue; + + /* Set CLKMUX_MMC src to MPLL */ + clr = MUX_MMC0_SEL(7) | MUX_MMC1_SEL(7) | MUX_MMC2_SEL(7); + set = MUX_MMC0_SEL(3) | MUX_MMC1_SEL(3) | MUX_MMC2_SEL(3); + + clrsetbits_le32(&clk->src_fsys, clr, set); + + clr = MMC0_RATIO(0x3ff) | MMC1_RATIO(0x3ff) | MMC2_RATIO(0x3ff); + set = MMC0_RATIO(0) | MMC1_RATIO(0) | MMC2_RATIO(0); + + clrsetbits_le32(&clk->div_fsys1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) + continue; + + return 0; +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int exynos_early_init_f(void) +{ + return board_clock_init(); +} +#endif diff --git a/board/samsung/odroid-xu3/setup.h b/board/samsung/odroid-xu3/setup.h new file mode 100644 index 0000000..481adb9 --- /dev/null +++ b/board/samsung/odroid-xu3/setup.h @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Minkyu Kang mk7.kang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ODROID_XU3_SETUP__ +#define __ODROID_XU3_SETUP__ + +#define SDIV(x) ((x) & 0x7) +#define PDIV(x) ((x & 0x3f) << 8) +#define MDIV(x) ((x & 0x3ff) << 16) +#define FSEL(x) ((x & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) ((x & 0x1) << 31) + +#define DIV_STAT_CHANGING 0x1 + +/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) ((x) & 0x1) +#define MUX_CORE_SEL(x) (((x) & 0x1) << 16) + +/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) ((x) & 0x7) +#define CORE_SEL(x) (((x) & 0x7) << 16) +#define MUX_STAT_CPU_CHANGING(x) !(((x) & APLL_SEL(0)) || \ + (x) & APLL_SEL(1) || \ + (x) & CORE_SEL(0) || \ + (x) & CORE_SEL(1)) + +/* CLK_DIV_CPU0 */ +#define ARM_RATIO(x) ((x) & 0x7) +#define CPUD_RATIO(x) (((x) & 0x7) << 4) +#define ATB_RATIO(x) (((x) & 0x7) << 16) +#define PCLK_DBG_RATIO(x) (((x) & 0x7) << 20) +#define APLL_RATIO(x) (((x) & 0x7) << 24) +#define ARM2_RATIO(x) (((x) & 0x7) << 28) + +/* CLK_DIV_STAT_CPU0 */ +#define DIV_CPUD(x) (((x) & 0x1) << 4) +#define DIV_ATB(x) (((x) & 0x1) << 16) +#define DIV_PCLK_DBG(x) (((x) & 0x1) << 20) +#define DIV_APLL(x) (((x) & 0x1) << 24) +#define DIV_ARM2(x) (((x) & 0x1) << 28) + +#define DIV_STAT_CPU0_CHANGING (DIV_CPUD(DIV_STAT_CHANGING) | \ + DIV_ATB(DIV_STAT_CHANGING) | \ + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ + DIV_APLL(DIV_STAT_CHANGING) | \ + DIV_ARM2(DIV_STAT_CHANGING)) + +/* Set CLK_SRC_PERIC0 */ +#define UART0_SEL(x) (((x) & 0xf) << 4) +#define UART1_SEL(x) (((x) & 0xf) << 8) +#define UART2_SEL(x) (((x) & 0xf) << 12) +#define UART3_SEL(x) (((x) & 0xf) << 16) + +/* Set CLK_DIV_PERIL0 */ +#define UART0_RATIO(x) (((x) & 0xf) << 8) +#define UART1_RATIO(x) (((x) & 0xf) << 12) +#define UART2_RATIO(x) (((x) & 0xf) << 16) +#define UART3_RATIO(x) (((x) & 0xf) << 20) + +/* Set CLK_DIV_STAT_PERIL0 */ +#define DIV_UART0(x) ((x) & 0x1) +#define DIV_UART1(x) (((x) & 0x1) << 4) +#define DIV_UART2(x) (((x) & 0x1) << 8) +#define DIV_UART3(x) (((x) & 0x1) << 12) +#define DIV_UART4(x) (((x) & 0x1) << 16) + +#define DIV_STAT_PERIC0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ + DIV_UART3(DIV_STAT_CHANGING) | \ + DIV_UART2(DIV_STAT_CHANGING) | \ + DIV_UART1(DIV_STAT_CHANGING) | \ + DIV_UART0(DIV_STAT_CHANGING)) + +/* CLK_SRC_FSYS */ +#define MUX_MMC0_SEL(x) (((x) & 0x7) << 8) +#define MUX_MMC1_SEL(x) (((x) & 0x7) << 12) +#define MUX_MMC2_SEL(x) (((x) & 0x7) << 16) + +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0x3ff) +#define MMC1_RATIO(x) (((x) & 0x3ff) << 10) +#define MMC2_RATIO(x) (((x) & 0x3ff) << 20) + +#define DIV_MMC0(x) (((x) & 1) << 20) +#define DIV_MMC1(x) (((x) & 1) << 24) +#define DIV_MMC2(x) (((x) & 1) << 28) + +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ + DIV_MMC1(DIV_STAT_CHANGING) | \ + DIV_MMC2(DIV_STAT_CHANGING)) + +#define MPLL_FOUT_SEL_SHIFT 4 +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ +#define TIMEOUT_EPLL_LOCK 1000 + +#define AUDIO_0_RATIO_MASK 0x0f +#define AUDIO_1_RATIO_MASK 0x0f + +#define AUDIO0_SEL_MASK 0xf +#define AUDIO1_SEL_MASK 0xf + +#define CLK_SRC_SCLK_EPLL 0x7 +#define CLK_SRC_MOUT_EPLL (1<<12) +#define AUDIO_CLKMUX_ASS (1<<0) + +/* CON0 bit-fields */ +#define EPLL_CON0_MDIV_MASK 0x1ff +#define EPLL_CON0_PDIV_MASK 0x3f +#define EPLL_CON0_SDIV_MASK 0x7 +#define EPLL_CON0_MDIV_SHIFT 16 +#define EPLL_CON0_PDIV_SHIFT 8 +#define EPLL_CON0_SDIV_SHIFT 0 +#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 +#define EPLL_CON0_LOCK_DET_EN_MASK 1 + +#define MPLL_FOUT_SEL_MASK 0x1 +#define BPLL_FOUT_SEL_SHIFT 0 +#define BPLL_FOUT_SEL_MASK 0x1 +#endif diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig new file mode 100644 index 0000000..74aa0cf --- /dev/null +++ b/configs/odroid-xu3_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TARGET_ODROID_XU3=y +CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h new file mode 100644 index 0000000..f0d5646 --- /dev/null +++ b/include/configs/odroid_xu3.h @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Hyungwon Hwang human.hwang@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_XU3_H +#define __CONFIG_ODROID_XU3_H + +#include "exynos5-common.h" + +#define CONFIG_SYS_PROMPT "ODROID-XU3 # " + +/* High Level Configuration Options */ +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE +#define CONFIG_BOARD_COMMON + +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Power Management is enabled */ +#define CONFIG_PM +#define CONFIG_PM_VDD_ARM 1.00 +#define CONFIG_PM_VDD_KFC 1.0250 +#define CONFIG_PM_VDD_INT 1.00 +#define CONFIG_PM_VDD_G3D 1.00 +#define CONFIG_PM_VDD_MIF 1.10 + +/* Keep L2 Cache Disabled */ +#define CONFIG_SYS_DCACHE_OFF + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_TEXT_BASE 0x43E00000 +#define CONFIG_SPL_TEXT_BASE 0x02027000 + +/* input clock of PLL: SMDK5422 has 24MHz input clock */ +#define CONFIG_SYS_CLK_FREQ 24000000 + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG +#define CONFIG_CMDLINE_EDITING + +/* iRAM information */ +#define CONFIG_PHY_IRAM_BASE (0x02020000) +#define CONFIG_PHY_IRAM_NS_BASE (CONFIG_PHY_IRAM_BASE + 0x53000) + +/* Power Down Modes */ +#define S5P_CHECK_SLEEP 0x00000BAD +#define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000 + +/* Offset for OM status registers */ +#define OM_STATUS_OFFSET 0x0 + +/* select serial console configuration */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SERIAL2 /* use SERIAL 2 */ +#define CONFIG_BAUDRATE 115200 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 + +#define TZPC_BASE_OFFSET 0x10000 + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_S5P_MSHC +#define CONFIG_S5P_SDHCI +#define CONFIG_MMC_64BIT_BUS + +#if defined(CONFIG_S5P_MSHC) +#define CONFIG_MMC_EARLY_INIT +#define MMC_MAX_CHANNEL 4 +#define USE_MMC0 +#define USE_MMC2 + +#define PHASE_DEVIDER 4 + +#define SDR_CH0 0x03030002 +#define DDR_CH0 0x03020001 + +#define SDR_CH2 0x03020001 +#define DDR_CH2 0x03030002 + +#define SDR_CH4 0x0 +#define DDR_CH4 0x0 +#endif + +/* + * Boot configuration + */ +#define BOOT_MMCSD 0x3 +#define BOOT_EMMC 0x6 +#define BOOT_EMMC_4_4 0x7 + +/* + * Boot device + */ +#define SDMMC_CH2 0x0 +#define SDMMC_CH0 0x4 +#define EMMC 0x14 + +#define CONFIG_BOARD_EARLY_INIT_F + +/* PWM */ +#define CONFIG_PWM + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command definition*/ +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_BOOTZ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +/* USB */ +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_EXYNOS +#define CONFIG_USB_STORAGE + +/* OHCI : Host 1.0 */ +#define CONFIG_USB_OHCI + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_RD_LVL + +/* Stack sizes */ +#define CONFIG_STACKSIZE (256 << 10) /* 256KB */ + +/* + * FIXME: The number of bank is actually 8. But there is no way to reserver the + * last 16 Mib in the last bank now. So I just excluded the last bank + * temporally. + */ +#define CONFIG_NR_DRAM_BANKS 7 + +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_IDENT_STRING " for ODROID-XU3" + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +/* Configuration of ENV size on mmc */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ + +/* Configuration of ROOTFS_ATAGS */ +#define CONFIG_ROOTFS_ATAGS +#ifdef CONFIG_ROOTFS_ATAGS +#ifdef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_EXTRA_ENV_SETTINGS +#endif +#define CONFIG_EXTRA_ENV_SETTINGS "rootfslen= 100000" +#endif + +/* U-boot copy size from boot Media to DRAM.*/ +#define CONFIG_DOS_PARTITION +#define CFG_PARTITION_START 0x4000000 +#define CONFIG_IRAM_STACK 0x02074000 + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) + +/* Base address for secondary boot information */ +#define CONFIG_SECONDARY_BOOT_INFORM_BASE (CONFIG_SYS_TEXT_BASE - 0x8) + +/* Offset for pmu reset status */ +#define RST_STAT_OFFSET 0x404 + +/* RST_STAT */ +#define WRESET (1 << 10) +#define SYS_WDTRESET (1 << 9) +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ +#undef CONFIG_EXYNOS_TMU +#undef CONFIG_TMU_CMD_DTT + +#define CONFIG_FDTDEC_MEMORY + +#undef CONFIG_ARCH_EARLY_INIT_R +#undef CONFIG_EXYNOS_SPL +#undef CONFIG_SILENT_CONSOLE +#undef CONFIG_CROS_EC +#undef CONFIG_CROS_EC_SPI +#undef CONFIG_CROS_EC_I2C +#undef CONFIG_CROS_EC_KEYB +#undef CONFIG_CMD_CROS_EC +#undef CONFIG_KEYBOARD +#undef CONFIG_SPI_BOOTING +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_SPI_FLASH +#undef CONFIG_EXYNOS_SPI +#undef CONFIG_CMD_SF +#undef CONFIG_CMD_SPI +#undef CONFIG_SPI_FLASH_WINBOND +#undef CONFIG_SPI_FLASH_GIGADEVICE +#undef CONFIG_OF_SPI +#undef CONFIG_FIT_BEST_MATCH +#undef CONFIG_USB_BOOTING +#undef CONFIG_CMD_NET +#undef CONFIG_SMC911X +#undef CONFIG_CMD_PXE +#undef CONFIG_MENU +#undef CONFIG_ENV_IS_IN_SPI_FLASH + + +#endif /* __CONFIG_H */