On 2023/1/30 22:57, Jagan Teki wrote:

Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3588.c | 1996 +++++++++++++++++++++++++++++ 2 files changed, 1997 insertions(+) create mode 100644 drivers/clk/rockchip/clk_rk3588.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index f719f4e379..9e379cc2e3 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c new file mode 100644 index 0000000000..b87b023bd7 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
• • Author: Elaine Zhang zhangqing@rock-chips.com
• */

+#include <common.h> +#include <bitfield.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch-rockchip/cru_rk3588.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rk3588-cru.h>

+DECLARE_GLOBAL_DATA_PTR;

+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))

+static struct rockchip_pll_rate_table rk3588_pll_rates[] = {

• /* _mhz, _p, _m, _s, _k */
• RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
• RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
• RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
• RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
• RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
• RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
• RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
• RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
• RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
• RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
• RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
• RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
• RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
• RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
• RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
• RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
• { /* sentinel */ },

+};

+static struct rockchip_pll_clock rk3588_pll_clks[] = {

• [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0),

•       RK3588_B0_PLL_MODE_CON, 0, 15, 0,
  

•       rk3588_pll_rates),
  

• [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8),

•       RK3588_B1_PLL_MODE_CON, 0, 15, 0,
  

•       rk3588_pll_rates),
  

• [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16),

•      RK3588_LPLL_MODE_CON, 0, 15, 0, rk3588_pll_rates),
  

• [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),

•       RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
  

• [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),

•       RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
  

• [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),

•      RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
  

• [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),

•      RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
  

• [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),

•      RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
  

• [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),

•      RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
  

+};

+#ifndef CONFIG_SPL_BUILD +/*

• • rational_best_approximation(31415, 10000,

• • (1 << 8) - 1, (1 << 5) - 1, &n, &d);
    

• • you may look at given_numerator as a fixed point number,
• • with the fractional part size described in given_denominator.
• • for theoretical background, see:
• • http://en.wikipedia.org/wiki/Continued_fraction
• */

+static void rational_best_approximation(unsigned long given_numerator,

• 			unsigned long given_denominator,
  

• 			unsigned long max_numerator,
  

• 			unsigned long max_denominator,
  

• 			unsigned long *best_numerator,
  

• 			unsigned long *best_denominator)
  

+{

• unsigned long n, d, n0, d0, n1, d1;
• n = given_numerator;
• d = given_denominator;
• n0 = 0;
• d1 = 0;
• n1 = 1;
• d0 = 1;
• for (;;) {

• unsigned long t, a;
  

• if (n1 > max_numerator || d1 > max_denominator) {
  

• 	n1 = n0;
  

• 	d1 = d0;
  

• 	break;
  

• }
  

• if (d == 0)
  

• 	break;
  

• t = d;
  

• a = n / d;
  

• d = n % d;
  

• n = t;
  

• t = n0 + a * n1;
  

• n0 = n1;
  

• n1 = t;
  

• t = d0 + a * d1;
  

• d0 = d1;
  

• d1 = t;
  

• }
• *best_numerator = n1;
• *best_denominator = d1;

+} +#endif

+static ulong rk3588_center_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 con, sel, rate;
• switch (clk_id) {
• case ACLK_CENTER_ROOT:

• con = readl(&cru->clksel_con[165]);
  

• sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >>
  

•       ACLK_CENTER_ROOT_SEL_SHIFT;
  

• if (sel == ACLK_CENTER_ROOT_SEL_700M)
  

• 	rate = 702 * MHz;
  

• else if (sel == ACLK_CENTER_ROOT_SEL_400M)
  

• 	rate = 396 * MHz;
  

• else if (sel == ACLK_CENTER_ROOT_SEL_200M)
  

• 	rate = 200 * MHz;
  

• else
  

• 	rate = OSC_HZ;
  

• break;
  

• case ACLK_CENTER_LOW_ROOT:

• con = readl(&cru->clksel_con[165]);
  

• sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >>
  

•       ACLK_CENTER_LOW_ROOT_SEL_SHIFT;
  

• if (sel == ACLK_CENTER_LOW_ROOT_SEL_500M)
  

• 	rate = 500 * MHz;
  

• else if (sel == ACLK_CENTER_LOW_ROOT_SEL_250M)
  

• 	rate = 250 * MHz;
  

• else if (sel == ACLK_CENTER_LOW_ROOT_SEL_100M)
  

• 	rate = 100 * MHz;
  

• else
  

• 	rate = OSC_HZ;
  

• break;
  

• case HCLK_CENTER_ROOT:

• con = readl(&cru->clksel_con[165]);
  

• sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >>
  

•       HCLK_CENTER_ROOT_SEL_SHIFT;
  

• if (sel == HCLK_CENTER_ROOT_SEL_400M)
  

• 	rate = 396 * MHz;
  

• else if (sel == HCLK_CENTER_ROOT_SEL_200M)
  

• 	rate = 200 * MHz;
  

• else if (sel == HCLK_CENTER_ROOT_SEL_100M)
  

• 	rate = 100 * MHz;
  

• else
  

• 	rate = OSC_HZ;
  

• break;
  

• case PCLK_CENTER_ROOT:

• con = readl(&cru->clksel_con[165]);
  

• sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >>
  

•       PCLK_CENTER_ROOT_SEL_SHIFT;
  

• if (sel == PCLK_CENTER_ROOT_SEL_200M)
  

• 	rate = 200 * MHz;
  

• else if (sel == PCLK_CENTER_ROOT_SEL_100M)
  

• 	rate = 100 * MHz;
  

• else if (sel == PCLK_CENTER_ROOT_SEL_50M)
  

• 	rate = 50 * MHz;
  

• else
  

• 	rate = OSC_HZ;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rate;

+}

+static ulong rk3588_center_set_clk(struct rk3588_clk_priv *priv,

• 		   ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk;
• switch (clk_id) {
• case ACLK_CENTER_ROOT:

• if (rate >= 700 * MHz)
  

• 	src_clk = ACLK_CENTER_ROOT_SEL_700M;
  

• else if (rate >= 396 * MHz)
  

• 	src_clk = ACLK_CENTER_ROOT_SEL_400M;
  

• else if (rate >= 200 * MHz)
  

• 	src_clk = ACLK_CENTER_ROOT_SEL_200M;
  

• else
  

• 	src_clk = ACLK_CENTER_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[165],
  

• 	     ACLK_CENTER_ROOT_SEL_MASK,
  

• 	     src_clk << ACLK_CENTER_ROOT_SEL_SHIFT);
  

• break;
  

• case ACLK_CENTER_LOW_ROOT:

• if (rate >= 500 * MHz)
  

• 	src_clk = ACLK_CENTER_LOW_ROOT_SEL_500M;
  

• else if (rate >= 250 * MHz)
  

• 	src_clk = ACLK_CENTER_LOW_ROOT_SEL_250M;
  

• else if (rate >= 99 * MHz)
  

• 	src_clk = ACLK_CENTER_LOW_ROOT_SEL_100M;
  

• else
  

• 	src_clk = ACLK_CENTER_LOW_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[165],
  

• 	     ACLK_CENTER_LOW_ROOT_SEL_MASK,
  

• 	     src_clk << ACLK_CENTER_LOW_ROOT_SEL_SHIFT);
  

• break;
  

• case HCLK_CENTER_ROOT:

• if (rate >= 396 * MHz)
  

• 	src_clk = HCLK_CENTER_ROOT_SEL_400M;
  

• else if (rate >= 198 * MHz)
  

• 	src_clk = HCLK_CENTER_ROOT_SEL_200M;
  

• else if (rate >= 99 * MHz)
  

• 	src_clk = HCLK_CENTER_ROOT_SEL_100M;
  

• else
  

• 	src_clk = HCLK_CENTER_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[165],
  

• 	     HCLK_CENTER_ROOT_SEL_MASK,
  

• 	     src_clk << HCLK_CENTER_ROOT_SEL_SHIFT);
  

• break;
  

• case PCLK_CENTER_ROOT:

• if (rate >= 198 * MHz)
  

• 	src_clk = PCLK_CENTER_ROOT_SEL_200M;
  

• else if (rate >= 99 * MHz)
  

• 	src_clk = PCLK_CENTER_ROOT_SEL_100M;
  

• else if (rate >= 50 * MHz)
  

• 	src_clk = PCLK_CENTER_ROOT_SEL_50M;
  

• else
  

• 	src_clk = PCLK_CENTER_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[165],
  

• 	     PCLK_CENTER_ROOT_SEL_MASK,
  

• 	     src_clk << PCLK_CENTER_ROOT_SEL_SHIFT);
  

• break;
  

• default:

• printf("do not support this center freq\n");
  

• return -EINVAL;
  

• }
• return rk3588_center_get_clk(priv, clk_id);

+}

+static ulong rk3588_top_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 con, sel, div, rate, prate;
• switch (clk_id) {
• case ACLK_TOP_ROOT:

• con = readl(&cru->clksel_con[8]);
  

• div = (con & ACLK_TOP_ROOT_DIV_MASK) >>
  

•       ACLK_TOP_ROOT_DIV_SHIFT;
  

• sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >>
  

•       ACLK_TOP_ROOT_SRC_SEL_SHIFT;
  

• if (sel == ACLK_TOP_ROOT_SRC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = priv->cpll_hz;
  

• return DIV_TO_RATE(prate, div);
  

• case ACLK_LOW_TOP_ROOT:

• con = readl(&cru->clksel_con[8]);
  

• div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >>
  

•       ACLK_LOW_TOP_ROOT_DIV_SHIFT;
  

• sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >>
  

•       ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT;
  

• if (sel == ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = priv->gpll_hz;
  

• return DIV_TO_RATE(prate, div);
  

• case PCLK_TOP_ROOT:

• con = readl(&cru->clksel_con[8]);
  

• sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT;
  

• if (sel == PCLK_TOP_ROOT_SEL_100M)
  

• 	rate = 100 * MHz;
  

• else if (sel == PCLK_TOP_ROOT_SEL_50M)
  

• 	rate = 50 * MHz;
  

• else
  

• 	rate = OSC_HZ;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rate;

+}

+static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv,

• 		ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk, src_clk_div;
• switch (clk_id) {
• case ACLK_TOP_ROOT:

• src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• assert(src_clk_div - 1 <= 31);
  

• rk_clrsetreg(&cru->clksel_con[8],
  

• 	     ACLK_TOP_ROOT_DIV_MASK |
  

• 	     ACLK_TOP_ROOT_SRC_SEL_MASK,
  

• 	     (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
  

• 	      ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
  

• 	     (src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
  

• break;
  

• case ACLK_LOW_TOP_ROOT:

• src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• assert(src_clk_div - 1 <= 31);
  

• rk_clrsetreg(&cru->clksel_con[8],
  

• 	     ACLK_LOW_TOP_ROOT_DIV_MASK |
  

• 	     ACLK_LOW_TOP_ROOT_SRC_SEL_MASK,
  

• 	     (ACLK_LOW_TOP_ROOT_SRC_SEL_GPLL <<
  

• 	      ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT) |
  

• 	     (src_clk_div - 1) << ACLK_LOW_TOP_ROOT_DIV_SHIFT);
  

• break;
  

• case PCLK_TOP_ROOT:

• if (rate == 100 * MHz)
  

• 	src_clk = PCLK_TOP_ROOT_SEL_100M;
  

• else if (rate == 50 * MHz)
  

• 	src_clk = PCLK_TOP_ROOT_SEL_50M;
  

• else
  

• 	src_clk = PCLK_TOP_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[8],
  

• 	     PCLK_TOP_ROOT_SEL_MASK,
  

• 	     src_clk << PCLK_TOP_ROOT_SEL_SHIFT);
  

• break;
  

• default:

• printf("do not support this top freq\n");
  

• return -EINVAL;
  

• }
• return rk3588_top_get_clk(priv, clk_id);

+}

+static ulong rk3588_i2c_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 sel, con;
• ulong rate;
• switch (clk_id) {
• case CLK_I2C0:

• con = readl(&cru->pmuclksel_con[3]);
  

• sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;
  

• break;
  

• case CLK_I2C1:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;
  

• break;
  

• case CLK_I2C2:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;
  

• break;
  

• case CLK_I2C3:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;
  

• break;
  

• case CLK_I2C4:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;
  

• break;
  

• case CLK_I2C5:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;
  

• break;
  

• case CLK_I2C6:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;
  

• break;
  

• case CLK_I2C7:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;
  

• break;
  

• case CLK_I2C8:

• con = readl(&cru->clksel_con[38]);
  

• sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• if (sel == CLK_I2C_SEL_200M)

• rate = 200 * MHz;
  

• else

• rate = 100 * MHz;
  

• return rate;

+}

+static ulong rk3588_i2c_set_clk(struct rk3588_clk_priv *priv, ulong clk_id,

• 		ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk;
• if (rate >= 198 * MHz)

• src_clk = CLK_I2C_SEL_200M;
  

• else

• src_clk = CLK_I2C_SEL_100M;
  

• switch (clk_id) {
• case CLK_I2C0:

• rk_clrsetreg(&cru->pmuclksel_con[3], CLK_I2C0_SEL_MASK,
  

• 	     src_clk << CLK_I2C0_SEL_SHIFT);
  

• break;
  

• case CLK_I2C1:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C1_SEL_MASK,
  

• 	     src_clk << CLK_I2C1_SEL_SHIFT);
  

• break;
  

• case CLK_I2C2:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C2_SEL_MASK,
  

• 	     src_clk << CLK_I2C2_SEL_SHIFT);
  

• break;
  

• case CLK_I2C3:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C3_SEL_MASK,
  

• 	     src_clk << CLK_I2C3_SEL_SHIFT);
  

• break;
  

• case CLK_I2C4:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C4_SEL_MASK,
  

• 	     src_clk << CLK_I2C4_SEL_SHIFT);
  

• break;
  

• case CLK_I2C5:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C5_SEL_MASK,
  

• 	     src_clk << CLK_I2C5_SEL_SHIFT);
  

• break;
  

• case CLK_I2C6:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C6_SEL_MASK,
  

• 	     src_clk << CLK_I2C6_SEL_SHIFT);
  

• break;
  

• case CLK_I2C7:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C7_SEL_MASK,
  

• 	     src_clk << CLK_I2C7_SEL_SHIFT);
  

• break;
  

• case CLK_I2C8:

• rk_clrsetreg(&cru->clksel_con[38], CLK_I2C8_SEL_MASK,
  

• 	     src_clk << CLK_I2C8_SEL_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_i2c_get_clk(priv, clk_id);

+}

+static ulong rk3588_spi_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 sel, con;
• con = readl(&cru->clksel_con[59]);
• switch (clk_id) {
• case CLK_SPI0:

• sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
  

• break;
  

• case CLK_SPI1:

• sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
  

• break;
  

• case CLK_SPI2:

• sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
  

• break;
  

• case CLK_SPI3:

• sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
  

• break;
  

• case CLK_SPI4:

• sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• switch (sel) {
• case CLK_SPI_SEL_200M:

• return 200 * MHz;
  

• case CLK_SPI_SEL_150M:

• return 150 * MHz;
  

• case CLK_SPI_SEL_24M:

• return OSC_HZ;
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_spi_set_clk(struct rk3588_clk_priv *priv,

• 		ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk;
• if (rate >= 198 * MHz)

• src_clk = CLK_SPI_SEL_200M;
  

• else if (rate >= 140 * MHz)

• src_clk = CLK_SPI_SEL_150M;
  

• else

• src_clk = CLK_SPI_SEL_24M;
  

• switch (clk_id) {
• case CLK_SPI0:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_SPI0_SEL_MASK,
  

• 	     src_clk << CLK_SPI0_SEL_SHIFT);
  

• break;
  

• case CLK_SPI1:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_SPI1_SEL_MASK,
  

• 	     src_clk << CLK_SPI1_SEL_SHIFT);
  

• break;
  

• case CLK_SPI2:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_SPI2_SEL_MASK,
  

• 	     src_clk << CLK_SPI2_SEL_SHIFT);
  

• break;
  

• case CLK_SPI3:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_SPI3_SEL_MASK,
  

• 	     src_clk << CLK_SPI3_SEL_SHIFT);
  

• break;
  

• case CLK_SPI4:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_SPI4_SEL_MASK,
  

• 	     src_clk << CLK_SPI4_SEL_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_spi_get_clk(priv, clk_id);

+}

+static ulong rk3588_pwm_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 sel, con;
• switch (clk_id) {
• case CLK_PWM1:

• con = readl(&cru->clksel_con[59]);
  

• sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
  

• break;
  

• case CLK_PWM2:

• con = readl(&cru->clksel_con[59]);
  

• sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
  

• break;
  

• case CLK_PWM3:

• con = readl(&cru->clksel_con[60]);
  

• sel = (con & CLK_PWM3_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
  

• break;
  

• case CLK_PMU1PWM:

• con = readl(&cru->pmuclksel_con[2]);
  

• sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• switch (sel) {
• case CLK_PWM_SEL_100M:

• return 100 * MHz;
  

• case CLK_PWM_SEL_50M:

• return 50 * MHz;
  

• case CLK_PWM_SEL_24M:

• return OSC_HZ;
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_pwm_set_clk(struct rk3588_clk_priv *priv,

• 		ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk;
• if (rate >= 99 * MHz)

• src_clk = CLK_PWM_SEL_100M;
  

• else if (rate >= 50 * MHz)

• src_clk = CLK_PWM_SEL_50M;
  

• else

• src_clk = CLK_PWM_SEL_24M;
  

• switch (clk_id) {
• case CLK_PWM1:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_PWM1_SEL_MASK,
  

• 	     src_clk << CLK_PWM1_SEL_SHIFT);
  

• break;
  

• case CLK_PWM2:

• rk_clrsetreg(&cru->clksel_con[59],
  

• 	     CLK_PWM2_SEL_MASK,
  

• 	     src_clk << CLK_PWM2_SEL_SHIFT);
  

• break;
  

• case CLK_PWM3:

• rk_clrsetreg(&cru->clksel_con[60],
  

• 	     CLK_PWM3_SEL_MASK,
  

• 	     src_clk << CLK_PWM3_SEL_SHIFT);
  

• break;
  

• case CLK_PMU1PWM:

• rk_clrsetreg(&cru->pmuclksel_con[2],
  

• 	     CLK_PMU1PWM_SEL_MASK,
  

• 	     src_clk << CLK_PMU1PWM_SEL_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_pwm_get_clk(priv, clk_id);

+}

+static ulong rk3588_adc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 div, sel, con, prate;
• switch (clk_id) {
• case CLK_SARADC:

• con = readl(&cru->clksel_con[40]);
  

• div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
  

• sel = (con & CLK_SARADC_SEL_MASK) >>
  

•       CLK_SARADC_SEL_SHIFT;
  

• if (sel == CLK_SARADC_SEL_24M)
  

• 	prate = OSC_HZ;
  

• else
  

• 	prate = priv->gpll_hz;
  

• return DIV_TO_RATE(prate, div);
  

• case CLK_TSADC:

• con = readl(&cru->clksel_con[41]);
  

• div = (con & CLK_TSADC_DIV_MASK) >>
  

•       CLK_TSADC_DIV_SHIFT;
  

• sel = (con & CLK_TSADC_SEL_MASK) >>
  

•       CLK_TSADC_SEL_SHIFT;
  

• if (sel == CLK_TSADC_SEL_24M)
  

• 	prate = OSC_HZ;
  

• else
  

• 	prate = 100 * MHz;
  

• return DIV_TO_RATE(prate, div);
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_adc_set_clk(struct rk3588_clk_priv *priv,

• 		ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk_div;
• switch (clk_id) {
• case CLK_SARADC:

• if (!(OSC_HZ % rate)) {
  

• 	src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
  

• 	assert(src_clk_div - 1 <= 255);
  

• 	rk_clrsetreg(&cru->clksel_con[40],
  

• 		     CLK_SARADC_SEL_MASK |
  

• 		     CLK_SARADC_DIV_MASK,
  

• 		     (CLK_SARADC_SEL_24M <<
  

• 		      CLK_SARADC_SEL_SHIFT) |
  

• 		     (src_clk_div - 1) <<
  

• 		     CLK_SARADC_DIV_SHIFT);
  

• } else {
  

• 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• 	assert(src_clk_div - 1 <= 255);
  

• 	rk_clrsetreg(&cru->clksel_con[40],
  

• 		     CLK_SARADC_SEL_MASK |
  

• 		     CLK_SARADC_DIV_MASK,
  

• 		     (CLK_SARADC_SEL_GPLL <<
  

• 		      CLK_SARADC_SEL_SHIFT) |
  

• 		     (src_clk_div - 1) <<
  

• 		     CLK_SARADC_DIV_SHIFT);
  

• }
  

• break;
  

• case CLK_TSADC:

• if (!(OSC_HZ % rate)) {
  

• 	src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
  

• 	assert(src_clk_div - 1 <= 255);
  

• 	rk_clrsetreg(&cru->clksel_con[41],
  

• 		     CLK_TSADC_SEL_MASK |
  

• 		     CLK_TSADC_DIV_MASK,
  

• 		     (CLK_TSADC_SEL_24M <<
  

• 		      CLK_TSADC_SEL_SHIFT) |
  

• 		     (src_clk_div - 1) <<
  

• 		     CLK_TSADC_DIV_SHIFT);
  

• } else {
  

• 	src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• 	assert(src_clk_div - 1 <= 7);
  

• 	rk_clrsetreg(&cru->clksel_con[41],
  

• 		     CLK_TSADC_SEL_MASK |
  

• 		     CLK_TSADC_DIV_MASK,
  

• 		     (CLK_TSADC_SEL_GPLL <<
  

• 		      CLK_TSADC_SEL_SHIFT) |
  

• 		     (src_clk_div - 1) <<
  

• 		     CLK_TSADC_DIV_SHIFT);
  

• }
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_adc_get_clk(priv, clk_id);

+}

+static ulong rk3588_mmc_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 sel, con, div, prate;
• switch (clk_id) {
• case CCLK_SRC_SDIO:

• con = readl(&cru->clksel_con[172]);
  

• div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;
  

• sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>
  

•       CCLK_SDIO_SRC_SEL_SHIFT;
  

• if (sel == CCLK_SDIO_SRC_SEL_GPLL)
  

• 	prate = priv->gpll_hz;
  

• else if (sel == CCLK_SDIO_SRC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = OSC_HZ;
  

• return DIV_TO_RATE(prate, div);
  

• case CCLK_EMMC:

• con = readl(&cru->clksel_con[77]);
  

• div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
  

• sel = (con & CCLK_EMMC_SEL_MASK) >>
  

•       CCLK_EMMC_SEL_SHIFT;
  

• if (sel == CCLK_EMMC_SEL_GPLL)
  

• 	prate = priv->gpll_hz;
  

• else if (sel == CCLK_EMMC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = OSC_HZ;
  

• return DIV_TO_RATE(prate, div);
  

• case BCLK_EMMC:

• con = readl(&cru->clksel_con[78]);
  

• div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;
  

• sel = (con & BCLK_EMMC_SEL_MASK) >>
  

•       BCLK_EMMC_SEL_SHIFT;
  

• if (sel == CCLK_EMMC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = priv->gpll_hz;
  

• return DIV_TO_RATE(prate, div);
  

• case SCLK_SFC:

• con = readl(&cru->clksel_con[78]);
  

• div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;
  

• sel = (con & SCLK_SFC_SEL_MASK) >>
  

•       SCLK_SFC_SEL_SHIFT;
  

• if (sel == SCLK_SFC_SEL_GPLL)
  

• 	prate = priv->gpll_hz;
  

• else if (sel == SCLK_SFC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = OSC_HZ;
  

• return DIV_TO_RATE(prate, div);
  

• case DCLK_DECOM:

• con = readl(&cru->clksel_con[62]);
  

• div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;
  

• sel = (con & DCLK_DECOM_SEL_MASK) >>
  

•       DCLK_DECOM_SEL_SHIFT;
  

• if (sel == DCLK_DECOM_SEL_SPLL)
  

• 	prate = 702 * MHz;
  

• else
  

• 	prate = priv->gpll_hz;
  

• return DIV_TO_RATE(prate, div);
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_mmc_set_clk(struct rk3588_clk_priv *priv,

• 		ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk, div;
• switch (clk_id) {
• case CCLK_SRC_SDIO:
• case CCLK_EMMC:
• case SCLK_SFC:

• if (!(OSC_HZ % rate)) {
  

• 	src_clk = SCLK_SFC_SEL_24M;
  

• 	div = DIV_ROUND_UP(OSC_HZ, rate);
  

• } else if (!(priv->cpll_hz % rate)) {
  

• 	src_clk = SCLK_SFC_SEL_CPLL;
  

• 	div = DIV_ROUND_UP(priv->cpll_hz, rate);
  

• } else {
  

• 	src_clk = SCLK_SFC_SEL_GPLL;
  

• 	div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• }
  

• break;
  

• case BCLK_EMMC:

• if (!(priv->cpll_hz % rate)) {
  

• 	src_clk = CCLK_EMMC_SEL_CPLL;
  

• 	div = DIV_ROUND_UP(priv->cpll_hz, rate);
  

• } else {
  

• 	src_clk = CCLK_EMMC_SEL_GPLL;
  

• 	div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• }
  

• break;
  

• case DCLK_DECOM:

• if (!(702 * MHz % rate)) {
  

• 	src_clk = DCLK_DECOM_SEL_SPLL;
  

• 	div = DIV_ROUND_UP(702 * MHz, rate);
  

• } else {
  

• 	src_clk = DCLK_DECOM_SEL_GPLL;
  

• 	div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• }
  

• break;
  

• default:

• return -ENOENT;
  

• }
• switch (clk_id) {
• case CCLK_SRC_SDIO:

• rk_clrsetreg(&cru->clksel_con[172],
  

• 	     CCLK_SDIO_SRC_SEL_MASK |
  

• 	     CCLK_SDIO_SRC_DIV_MASK,
  

• 	     (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) |
  

• 	     (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);
  

• break;
  

• case CCLK_EMMC:

• rk_clrsetreg(&cru->clksel_con[77],
  

• 	     CCLK_EMMC_SEL_MASK |
  

• 	     CCLK_EMMC_DIV_MASK,
  

• 	     (src_clk << CCLK_EMMC_SEL_SHIFT) |
  

• 	     (div - 1) << CCLK_EMMC_DIV_SHIFT);
  

• break;
  

• case BCLK_EMMC:

• rk_clrsetreg(&cru->clksel_con[78],
  

• 	     BCLK_EMMC_DIV_MASK |
  

• 	     BCLK_EMMC_SEL_MASK,
  

• 	     (src_clk << BCLK_EMMC_SEL_SHIFT) |
  

• 	     (div - 1) << BCLK_EMMC_DIV_SHIFT);
  

• break;
  

• case SCLK_SFC:

• rk_clrsetreg(&cru->clksel_con[78],
  

• 	     SCLK_SFC_DIV_MASK |
  

• 	     SCLK_SFC_SEL_MASK,
  

• 	     (src_clk << SCLK_SFC_SEL_SHIFT) |
  

• 	     (div - 1) << SCLK_SFC_DIV_SHIFT);
  

• break;
  

• case DCLK_DECOM:

• rk_clrsetreg(&cru->clksel_con[62],
  

• 	     DCLK_DECOM_DIV_MASK |
  

• 	     DCLK_DECOM_SEL_MASK,
  

• 	     (src_clk << DCLK_DECOM_SEL_SHIFT) |
  

• 	     (div - 1) << DCLK_DECOM_DIV_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_mmc_get_clk(priv, clk_id);

+}

+#ifndef CONFIG_SPL_BUILD +static ulong rk3588_aux16m_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 div, con, parent;
• parent = priv->gpll_hz;
• con = readl(&cru->clksel_con[117]);
• switch (clk_id) {
• case CLK_AUX16M_0:

• div = (con & CLK_AUX16MHZ_0_DIV_MASK) >> CLK_AUX16MHZ_0_DIV_SHIFT;
  

• return DIV_TO_RATE(parent, div);
  

• case CLK_AUX16M_1:

• div = (con & CLK_AUX16MHZ_1_DIV_MASK) >> CLK_AUX16MHZ_1_DIV_SHIFT;
  

• return DIV_TO_RATE(parent, div);
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_aux16m_set_clk(struct rk3588_clk_priv *priv,

• 		   ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• u32 div;
• if (!priv->gpll_hz) {

• printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  

• return -ENOENT;
  

• }
• div = DIV_ROUND_UP(priv->gpll_hz, rate);
• switch (clk_id) {
• case CLK_AUX16M_0:

• rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_0_DIV_MASK,
  

• 	     (div - 1) << CLK_AUX16MHZ_0_DIV_SHIFT);
  

• break;
  

• case CLK_AUX16M_1:

• rk_clrsetreg(&cru->clksel_con[117], CLK_AUX16MHZ_1_DIV_MASK,
  

• 	     (div - 1) << CLK_AUX16MHZ_1_DIV_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_aux16m_get_clk(priv, clk_id);

+}

+static ulong rk3588_aclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 div, sel, con, parent;
• switch (clk_id) {
• case ACLK_VOP_ROOT:
• case ACLK_VOP:

• con = readl(&cru->clksel_con[110]);
  

• div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;
  

• sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;
  

• if (sel == ACLK_VOP_ROOT_SEL_GPLL)
  

• 	parent = priv->gpll_hz;
  

• else if (sel == ACLK_VOP_ROOT_SEL_CPLL)
  

• 	parent = priv->cpll_hz;
  

• else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)
  

• 	parent = priv->aupll_hz;
  

• else if (sel == ACLK_VOP_ROOT_SEL_NPLL)
  

• 	parent = priv->npll_hz;
  

• else
  

• 	parent = 702 * MHz;
  

• return DIV_TO_RATE(parent, div);
  

• case ACLK_VOP_LOW_ROOT:

• con = readl(&cru->clksel_con[110]);
  

• sel = (con & ACLK_VOP_LOW_ROOT_SEL_MASK) >>
  

•       ACLK_VOP_LOW_ROOT_SEL_SHIFT;
  

• if (sel == ACLK_VOP_LOW_ROOT_SEL_400M)
  

• 	return 396 * MHz;
  

• else if (sel == ACLK_VOP_LOW_ROOT_SEL_200M)
  

• 	return 200 * MHz;
  

• else if (sel == ACLK_VOP_LOW_ROOT_SEL_100M)
  

• 	return 100 * MHz;
  

• else
  

• 	return OSC_HZ;
  

• case HCLK_VOP_ROOT:

• con = readl(&cru->clksel_con[110]);
  

• sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;
  

• if (sel == HCLK_VOP_ROOT_SEL_200M)
  

• 	return 200 * MHz;
  

• else if (sel == HCLK_VOP_ROOT_SEL_100M)
  

• 	return 100 * MHz;
  

• else if (sel == HCLK_VOP_ROOT_SEL_50M)
  

• 	return 50 * MHz;
  

• else
  

• 	return OSC_HZ;
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_aclk_vop_set_clk(struct rk3588_clk_priv *priv,

• 		     ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int src_clk, div;
• switch (clk_id) {
• case ACLK_VOP_ROOT:
• case ACLK_VOP:

• if (rate >= 850 * MHz) {
  

• 	src_clk = ACLK_VOP_ROOT_SEL_NPLL;
  

• 	div = 1;
  

• } else if (rate >= 750 * MHz) {
  

• 	src_clk = ACLK_VOP_ROOT_SEL_CPLL;
  

• 	div = 2;
  

• } else if (rate >= 700 * MHz) {
  

• 	src_clk = ACLK_VOP_ROOT_SEL_SPLL;
  

• 	div = 1;
  

• } else if (!(priv->cpll_hz % rate)) {
  

• 	src_clk = ACLK_VOP_ROOT_SEL_CPLL;
  

• 	div = DIV_ROUND_UP(priv->cpll_hz, rate);
  

• } else {
  

• 	src_clk = ACLK_VOP_ROOT_SEL_GPLL;
  

• 	div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• }
  

• rk_clrsetreg(&cru->clksel_con[110],
  

• 	     ACLK_VOP_ROOT_DIV_MASK |
  

• 	     ACLK_VOP_ROOT_SEL_MASK,
  

• 	     (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) |
  

• 	     (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);
  

• break;
  

• case ACLK_VOP_LOW_ROOT:

• if (rate == 400 * MHz || rate == 396 * MHz)
  

• 	src_clk = ACLK_VOP_LOW_ROOT_SEL_400M;
  

• else if (rate == 200 * MHz)
  

• 	src_clk = ACLK_VOP_LOW_ROOT_SEL_200M;
  

• else if (rate == 100 * MHz)
  

• 	src_clk = ACLK_VOP_LOW_ROOT_SEL_100M;
  

• else
  

• 	src_clk = ACLK_VOP_LOW_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[110],
  

• 	     ACLK_VOP_LOW_ROOT_SEL_MASK,
  

• 	     src_clk << ACLK_VOP_LOW_ROOT_SEL_SHIFT);
  

• break;
  

• case HCLK_VOP_ROOT:

• if (rate == 200 * MHz)
  

• 	src_clk = HCLK_VOP_ROOT_SEL_200M;
  

• else if (rate == 100 * MHz)
  

• 	src_clk = HCLK_VOP_ROOT_SEL_100M;
  

• else if (rate == 50 * MHz)
  

• 	src_clk = HCLK_VOP_ROOT_SEL_50M;
  

• else
  

• 	src_clk = HCLK_VOP_ROOT_SEL_24M;
  

• rk_clrsetreg(&cru->clksel_con[110],
  

• 	     HCLK_VOP_ROOT_SEL_MASK,
  

• 	     src_clk << HCLK_VOP_ROOT_SEL_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_aclk_vop_get_clk(priv, clk_id);

+}

+static ulong rk3588_dclk_vop_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 div, sel, con, parent;
• switch (clk_id) {
• case DCLK_VOP0:
• case DCLK_VOP0_SRC:

• con = readl(&cru->clksel_con[111]);
  

• div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
  

• sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
  

• break;
  

• case DCLK_VOP1:
• case DCLK_VOP1_SRC:

• con = readl(&cru->clksel_con[111]);
  

• div = (con & DCLK1_VOP_SRC_DIV_MASK) >> DCLK1_VOP_SRC_DIV_SHIFT;
  

• sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;
  

• break;
  

• case DCLK_VOP2:
• case DCLK_VOP2_SRC:

• con = readl(&cru->clksel_con[112]);
  

• div = (con & DCLK2_VOP_SRC_DIV_MASK) >> DCLK2_VOP_SRC_DIV_SHIFT;
  

• sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;
  

• break;
  

• case DCLK_VOP3:

• con = readl(&cru->clksel_con[113]);
  

• div = (con & DCLK3_VOP_SRC_DIV_MASK) >> DCLK3_VOP_SRC_DIV_SHIFT;
  

• sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• if (sel == DCLK_VOP_SRC_SEL_AUPLL)

• parent = priv->aupll_hz;
  

• else if (sel == DCLK_VOP_SRC_SEL_V0PLL)

• parent = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
  

• 			       priv->cru, V0PLL);
  

• else if (sel == DCLK_VOP_SRC_SEL_GPLL)

• parent = priv->gpll_hz;
  

• else if (sel == DCLK_VOP_SRC_SEL_CPLL)

• parent = priv->cpll_hz;
  

• else

• return -ENOENT;
  

• return DIV_TO_RATE(parent, div);

+}

+#define RK3588_VOP_PLL_LIMIT_FREQ 600000000

+static ulong rk3588_dclk_vop_set_clk(struct rk3588_clk_priv *priv,

• 		     ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• ulong pll_rate, now, best_rate = 0;
• u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
• u32 mask, div_shift, sel_shift;
• switch (clk_id) {
• case DCLK_VOP0:
• case DCLK_VOP0_SRC:

• conid = 111;
  

• con = readl(&cru->clksel_con[111]);
  

• sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
  

• mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
  

• div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
  

• sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
  

• break;
  

• case DCLK_VOP1:
• case DCLK_VOP1_SRC:

• conid = 111;
  

• con = readl(&cru->clksel_con[111]);
  

• sel = (con & DCLK1_VOP_SRC_SEL_MASK) >> DCLK1_VOP_SRC_SEL_SHIFT;
  

• mask = DCLK1_VOP_SRC_SEL_MASK | DCLK1_VOP_SRC_DIV_MASK;
  

• div_shift = DCLK1_VOP_SRC_DIV_SHIFT;
  

• sel_shift = DCLK1_VOP_SRC_SEL_SHIFT;
  

• break;
  

• case DCLK_VOP2:
• case DCLK_VOP2_SRC:

• conid = 112;
  

• con = readl(&cru->clksel_con[112]);
  

• sel = (con & DCLK2_VOP_SRC_SEL_MASK) >> DCLK2_VOP_SRC_SEL_SHIFT;
  

• mask = DCLK2_VOP_SRC_SEL_MASK | DCLK2_VOP_SRC_DIV_MASK;
  

• div_shift = DCLK2_VOP_SRC_DIV_SHIFT;
  

• sel_shift = DCLK2_VOP_SRC_SEL_SHIFT;
  

• break;
  

• case DCLK_VOP3:

• conid = 113;
  

• con = readl(&cru->clksel_con[113]);
  

• sel = (con & DCLK3_VOP_SRC_SEL_MASK) >> DCLK3_VOP_SRC_SEL_SHIFT;
  

• mask = DCLK3_VOP_SRC_SEL_MASK | DCLK3_VOP_SRC_DIV_MASK;
  

• div_shift = DCLK3_VOP_SRC_DIV_SHIFT;
  

• sel_shift = DCLK3_VOP_SRC_SEL_SHIFT;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• if (sel == DCLK_VOP_SRC_SEL_V0PLL) {

• div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
  

• rk_clrsetreg(&cru->clksel_con[conid],
  

• 	     mask,
  

• 	     DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
  

• 	     ((div - 1) << div_shift));
  

• rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
  

• 		      priv->cru, V0PLL, div * rate);
  

• } else {

• for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
  

• 	switch (i) {
  

• 	case DCLK_VOP_SRC_SEL_GPLL:
  

• 		pll_rate = priv->gpll_hz;
  

• 		break;
  

• 	case DCLK_VOP_SRC_SEL_CPLL:
  

• 		pll_rate = priv->cpll_hz;
  

• 		break;
  

• 	case DCLK_VOP_SRC_SEL_AUPLL:
  

• 		pll_rate = priv->aupll_hz;
  

• 		break;
  

• 	case DCLK_VOP_SRC_SEL_V0PLL:
  

• 		pll_rate = 0;
  

• 		break;
  

• 	default:
  

• 		printf("do not support this vop pll sel\n");
  

• 		return -EINVAL;
  

• 	}
  

• 	div = DIV_ROUND_UP(pll_rate, rate);
  

• 	if (div > 255)
  

• 		continue;
  

• 	now = pll_rate / div;
  

• 	if (abs(rate - now) < abs(rate - best_rate)) {
  

• 		best_rate = now;
  

• 		best_div = div;
  

• 		best_sel = i;
  

• 	}
  

• 	debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
  

• 	      pll_rate, best_rate, best_div, best_sel);
  

• }
  

• if (best_rate) {
  

• 	rk_clrsetreg(&cru->clksel_con[conid],
  

• 		     mask,
  

• 		     best_sel << sel_shift |
  

• 		     (best_div - 1) << div_shift);
  

• } else {
  

• 	printf("do not support this vop freq %lu\n", rate);
  

• 	return -EINVAL;
  

• }
  

• }
• return rk3588_dclk_vop_get_clk(priv, clk_id);

+}

+static ulong rk3588_gmac_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 con, div;
• switch (clk_id) {
• case CLK_GMAC0_PTP_REF:

• con = readl(&cru->clksel_con[81]);
  

• div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
  

• return DIV_TO_RATE(priv->cpll_hz, div);
  

• case CLK_GMAC1_PTP_REF:

• con = readl(&cru->clksel_con[81]);
  

• div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC1_PTP_DIV_SHIFT;
  

• return DIV_TO_RATE(priv->cpll_hz, div);
  

• case CLK_GMAC_125M:

• con = readl(&cru->clksel_con[83]);
  

• div = (con & CLK_GMAC_125M_DIV_MASK) >> CLK_GMAC_125M_DIV_SHIFT;
  

• return DIV_TO_RATE(priv->cpll_hz, div);
  

• case CLK_GMAC_50M:

• con = readl(&cru->clksel_con[84]);
  

• div = (con & CLK_GMAC_50M_DIV_MASK) >> CLK_GMAC_50M_DIV_SHIFT;
  

• return DIV_TO_RATE(priv->cpll_hz, div);
  

• default:

• return -ENOENT;
  

• }

+}

+static ulong rk3588_gmac_set_clk(struct rk3588_clk_priv *priv,

• 		 ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• int div;
• div = DIV_ROUND_UP(priv->cpll_hz, rate);
• switch (clk_id) {
• case CLK_GMAC0_PTP_REF:

• rk_clrsetreg(&cru->clksel_con[81],
  

• 	     CLK_GMAC0_PTP_DIV_MASK | CLK_GMAC0_PTP_SEL_MASK,
  

• 	     CLK_GMAC0_PTP_SEL_CPLL << CLK_GMAC0_PTP_SEL_SHIFT |
  

• 	     (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);
  

• break;
  

• case CLK_GMAC1_PTP_REF:

• rk_clrsetreg(&cru->clksel_con[81],
  

• 	     CLK_GMAC1_PTP_DIV_MASK | CLK_GMAC1_PTP_SEL_MASK,
  

• 	     CLK_GMAC1_PTP_SEL_CPLL << CLK_GMAC1_PTP_SEL_SHIFT |
  

• 	     (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);
  

• break;
  

• case CLK_GMAC_125M:

• rk_clrsetreg(&cru->clksel_con[83],
  

• 	     CLK_GMAC_125M_DIV_MASK | CLK_GMAC_125M_SEL_MASK,
  

• 	     CLK_GMAC_125M_SEL_CPLL << CLK_GMAC_125M_SEL_SHIFT |
  

• 	     (div - 1) << CLK_GMAC_125M_DIV_SHIFT);
  

• break;
  

• case CLK_GMAC_50M:

• rk_clrsetreg(&cru->clksel_con[84],
  

• 	     CLK_GMAC_50M_DIV_MASK | CLK_GMAC_50M_SEL_MASK,
  

• 	     CLK_GMAC_50M_SEL_CPLL << CLK_GMAC_50M_SEL_SHIFT |
  

• 	     (div - 1) << CLK_GMAC_50M_DIV_SHIFT);
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_gmac_get_clk(priv, clk_id);

+}

+static ulong rk3588_uart_get_rate(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 reg, con, fracdiv, div, src, p_src, p_rate;
• unsigned long m, n;
• switch (clk_id) {
• case SCLK_UART1:

• reg = 41;
  

• break;
  

• case SCLK_UART2:

• reg = 43;
  

• break;
  

• case SCLK_UART3:

• reg = 45;
  

• break;
  

• case SCLK_UART4:

• reg = 47;
  

• break;
  

• case SCLK_UART5:

• reg = 49;
  

• break;
  

• case SCLK_UART6:

• reg = 51;
  

• break;
  

• case SCLK_UART7:

• reg = 53;
  

• break;
  

• case SCLK_UART8:

• reg = 55;
  

• break;
  

• case SCLK_UART9:

• reg = 57;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• con = readl(&cru->clksel_con[reg + 2]);
• src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
• con = readl(&cru->clksel_con[reg]);
• div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
• p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
• if (p_src == CLK_UART_SRC_SEL_GPLL)

• p_rate = priv->gpll_hz;
  

• else

• p_rate = priv->cpll_hz;
  

• if (src == CLK_UART_SEL_SRC) {

• return DIV_TO_RATE(p_rate, div);
  

• } else if (src == CLK_UART_SEL_FRAC) {

• fracdiv = readl(&cru->clksel_con[reg + 1]);
  

• n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
  

• n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
  

• m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
  

• m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
  

• return DIV_TO_RATE(p_rate, div) * n / m;
  

• } else {

• return OSC_HZ;
  

• }

+}

+static ulong rk3588_uart_set_rate(struct rk3588_clk_priv *priv,

• 		  ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• u32 reg, clk_src, uart_src, div;
• unsigned long m = 0, n = 0, val;
• if (priv->gpll_hz % rate == 0) {

• clk_src = CLK_UART_SRC_SEL_GPLL;
  

• uart_src = CLK_UART_SEL_SRC;
  

• div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• } else if (priv->cpll_hz % rate == 0) {

• clk_src = CLK_UART_SRC_SEL_CPLL;
  

• uart_src = CLK_UART_SEL_SRC;
  

• div = DIV_ROUND_UP(priv->gpll_hz, rate);
  

• } else if (rate == OSC_HZ) {

• clk_src = CLK_UART_SRC_SEL_GPLL;
  

• uart_src = CLK_UART_SEL_XIN24M;
  

• div = 2;
  

• } else {

• clk_src = CLK_UART_SRC_SEL_GPLL;
  

• uart_src = CLK_UART_SEL_FRAC;
  

• div = 2;
  

• rational_best_approximation(rate, priv->gpll_hz / div,
  

• 			    GENMASK(16 - 1, 0),
  

• 			    GENMASK(16 - 1, 0),
  

• 			    &m, &n);
  

• }
• switch (clk_id) {
• case SCLK_UART1:

• reg = 41;
  

• break;
  

• case SCLK_UART2:

• reg = 43;
  

• break;
  

• case SCLK_UART3:

• reg = 45;
  

• break;
  

• case SCLK_UART4:

• reg = 47;
  

• break;
  

• case SCLK_UART5:

• reg = 49;
  

• break;
  

• case SCLK_UART6:

• reg = 51;
  

• break;
  

• case SCLK_UART7:

• reg = 53;
  

• break;
  

• case SCLK_UART8:

• reg = 55;
  

• break;
  

• case SCLK_UART9:

• reg = 57;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• rk_clrsetreg(&cru->clksel_con[reg],

•      CLK_UART_SRC_SEL_MASK |
  

•      CLK_UART_SRC_DIV_MASK,
  

•      (clk_src << CLK_UART_SRC_SEL_SHIFT) |
  

•      ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
  

• rk_clrsetreg(&cru->clksel_con[reg + 2],

•      CLK_UART_SEL_MASK,
  

•      (uart_src << CLK_UART_SEL_SHIFT));
  

• if (m && n) {

• val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
  

• writel(val, &cru->clksel_con[reg + 1]);
  

• }
• return rk3588_uart_get_rate(priv, clk_id);

+}

+static ulong rk3588_pciephy_get_rate(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 con, div, src;
• switch (clk_id) {
• case CLK_REF_PIPE_PHY0:

• con = readl(&cru->clksel_con[177]);
  

• src = (con & CLK_PCIE_PHY0_REF_SEL_MASK) >> CLK_PCIE_PHY0_REF_SEL_SHIFT;
  

• con = readl(&cru->clksel_con[176]);
  

• div = (con & CLK_PCIE_PHY0_PLL_DIV_MASK) >> CLK_PCIE_PHY0_PLL_DIV_SHIFT;
  

• break;
  

• case CLK_REF_PIPE_PHY1:

• con = readl(&cru->clksel_con[177]);
  

• src = (con & CLK_PCIE_PHY1_REF_SEL_MASK) >> CLK_PCIE_PHY1_REF_SEL_SHIFT;
  

• con = readl(&cru->clksel_con[176]);
  

• div = (con & CLK_PCIE_PHY1_PLL_DIV_MASK) >> CLK_PCIE_PHY1_PLL_DIV_SHIFT;
  

• break;
  

• case CLK_REF_PIPE_PHY2:

• con = readl(&cru->clksel_con[177]);
  

• src = (con & CLK_PCIE_PHY2_REF_SEL_MASK) >> CLK_PCIE_PHY2_REF_SEL_SHIFT;
  

• div = (con & CLK_PCIE_PHY2_PLL_DIV_MASK) >> CLK_PCIE_PHY2_PLL_DIV_SHIFT;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• if (src == CLK_PCIE_PHY_REF_SEL_PPLL)

• return DIV_TO_RATE(priv->ppll_hz, div);
  

• else

• return OSC_HZ;
  

+}

+static ulong rk3588_pciephy_set_rate(struct rk3588_clk_priv *priv,

• 		     ulong clk_id, ulong rate)
  

+{

• struct rk3588_cru *cru = priv->cru;
• u32 clk_src, div;
• if (rate == OSC_HZ) {

• clk_src = CLK_PCIE_PHY_REF_SEL_24M;
  

• div = 1;
  

• } else {

• clk_src = CLK_PCIE_PHY_REF_SEL_PPLL;
  

• div = DIV_ROUND_UP(priv->ppll_hz, rate);
  

• }
• switch (clk_id) {
• case CLK_REF_PIPE_PHY0:

• rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY0_REF_SEL_MASK,
  

• 	     (clk_src << CLK_PCIE_PHY0_REF_SEL_SHIFT));
  

• rk_clrsetreg(&cru->clksel_con[176], CLK_PCIE_PHY0_PLL_DIV_MASK,
  

• 	     ((div - 1) << CLK_PCIE_PHY0_PLL_DIV_SHIFT));
  

• break;
  

• case CLK_REF_PIPE_PHY1:

• rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY1_REF_SEL_MASK,
  

• 	     (clk_src << CLK_PCIE_PHY1_REF_SEL_SHIFT));
  

• rk_clrsetreg(&cru->clksel_con[176], CLK_PCIE_PHY1_PLL_DIV_MASK,
  

• 	     ((div - 1) << CLK_PCIE_PHY1_PLL_DIV_SHIFT));
  

• break;
  

• case CLK_REF_PIPE_PHY2:

• rk_clrsetreg(&cru->clksel_con[177], CLK_PCIE_PHY2_REF_SEL_MASK |
  

• 	     CLK_PCIE_PHY2_PLL_DIV_MASK,
  

• 	     (clk_src << CLK_PCIE_PHY2_REF_SEL_SHIFT) |
  

• 	     ((div - 1) << CLK_PCIE_PHY2_PLL_DIV_SHIFT));
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rk3588_pciephy_get_rate(priv, clk_id);

+} +#endif

+static ulong rk3588_clk_get_rate(struct clk *clk) +{

• struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
• ulong rate = 0;
• if (!priv->gpll_hz) {

• printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  

• return -ENOENT;
  

• }
• if (!priv->ppll_hz) {

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• }
• switch (clk->id) {
• case PLL_LPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru,
  

• 			     LPLL);
  

• break;
  

• case PLL_B0PLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru,
  

• 			     B0PLL);
  

• break;
  

• case PLL_B1PLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru,
  

• 			     B1PLL);
  

• break;
  

• case PLL_GPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru,
  

• 			     GPLL);
  

• break;
  

• case PLL_CPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru,
  

• 			     CPLL);
  

• break;
  

• case PLL_NPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru,
  

• 			     NPLL);
  

• break;
  

• case PLL_V0PLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru,
  

• 			     V0PLL);
  

• break;
  

• case PLL_AUPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru,
  

• 			     AUPLL);
  

• break;
  

• case PLL_PPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru,
  

• 			     PPLL);
  

• break;
  

• case ACLK_CENTER_ROOT:
• case PCLK_CENTER_ROOT:
• case HCLK_CENTER_ROOT:
• case ACLK_CENTER_LOW_ROOT:

• rate = rk3588_center_get_clk(priv, clk->id);
  

• break;
  

• case ACLK_TOP_ROOT:
• case PCLK_TOP_ROOT:
• case ACLK_LOW_TOP_ROOT:

• rate = rk3588_top_get_clk(priv, clk->id);
  

• break;
  

• case CLK_I2C0:
• case CLK_I2C1:
• case CLK_I2C2:
• case CLK_I2C3:
• case CLK_I2C4:
• case CLK_I2C5:
• case CLK_I2C6:
• case CLK_I2C7:
• case CLK_I2C8:

• rate = rk3588_i2c_get_clk(priv, clk->id);
  

• break;
  

• case CLK_SPI0:
• case CLK_SPI1:
• case CLK_SPI2:
• case CLK_SPI3:
• case CLK_SPI4:

• rate = rk3588_spi_get_clk(priv, clk->id);
  

• break;
  

• case CLK_PWM1:
• case CLK_PWM2:
• case CLK_PWM3:
• case CLK_PMU1PWM:

• rate = rk3588_pwm_get_clk(priv, clk->id);
  

• break;
  

• case CLK_SARADC:
• case CLK_TSADC:

• rate = rk3588_adc_get_clk(priv, clk->id);
  

• break;
  

• case CCLK_SRC_SDIO:
• case CCLK_EMMC:
• case BCLK_EMMC:
• case SCLK_SFC:
• case DCLK_DECOM:

• rate = rk3588_mmc_get_clk(priv, clk->id);
  

• break;
  

• case TCLK_WDT0:

• rate = OSC_HZ;
  

• break;
  

+#ifndef CONFIG_SPL_BUILD

• case CLK_AUX16M_0:
• case CLK_AUX16M_1:

• rk3588_aux16m_get_clk(priv, clk->id);
  

• break;
  

• case ACLK_VOP_ROOT:
• case ACLK_VOP:
• case ACLK_VOP_LOW_ROOT:
• case HCLK_VOP_ROOT:

• rate = rk3588_aclk_vop_get_clk(priv, clk->id);
  

• break;
  

• case DCLK_VOP0:
• case DCLK_VOP0_SRC:
• case DCLK_VOP1:
• case DCLK_VOP1_SRC:
• case DCLK_VOP2:
• case DCLK_VOP2_SRC:
• case DCLK_VOP3:

• rate = rk3588_dclk_vop_get_clk(priv, clk->id);
  

• break;
  

• case CLK_GMAC0_PTP_REF:
• case CLK_GMAC1_PTP_REF:
• case CLK_GMAC_125M:
• case CLK_GMAC_50M:

• rate = rk3588_gmac_get_clk(priv, clk->id);
  

• break;
  

• case SCLK_UART1:
• case SCLK_UART2:
• case SCLK_UART3:
• case SCLK_UART4:
• case SCLK_UART5:
• case SCLK_UART6:
• case SCLK_UART7:
• case SCLK_UART8:
• case SCLK_UART9:

• rate = rk3588_uart_get_rate(priv, clk->id);
  

• break;
  

• case CLK_REF_PIPE_PHY0:
• case CLK_REF_PIPE_PHY1:
• case CLK_REF_PIPE_PHY2:

• rate = rk3588_pciephy_get_rate(priv, clk->id);
  

• break;
  

+#endif

• default:

• return -ENOENT;
  

• }
• return rate;

+};

+static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) +{

• struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
• ulong ret = 0;
• if (!priv->gpll_hz) {

• printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  

• return -ENOENT;
  

• }
• if (!priv->ppll_hz) {

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• }
• switch (clk->id) {
• case PLL_CPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
  

• 			    CPLL, rate);
  

• priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL],
  

• 				      priv->cru, CPLL);
  

• break;
  

• case PLL_GPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
  

• 			    GPLL, rate);
  

• priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL],
  

• 				      priv->cru, GPLL);
  

• break;
  

• case PLL_NPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru,
  

• 			    NPLL, rate);
  

• break;
  

• case PLL_V0PLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru,
  

• 			    V0PLL, rate);
  

• priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
  

• 				       priv->cru, V0PLL);
  

• break;
  

• case PLL_AUPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[AUPLL], priv->cru,
  

• 			    AUPLL, rate);
  

• priv->aupll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL],
  

• 				       priv->cru, AUPLL);
  

• break;
  

• case PLL_PPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
  

• 			    PPLL, rate);
  

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• break;
  

• case ACLK_CENTER_ROOT:
• case PCLK_CENTER_ROOT:
• case HCLK_CENTER_ROOT:
• case ACLK_CENTER_LOW_ROOT:

• ret = rk3588_center_set_clk(priv, clk->id, rate);
  

• break;
  

• case ACLK_TOP_ROOT:
• case PCLK_TOP_ROOT:
• case ACLK_LOW_TOP_ROOT:

• ret = rk3588_top_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_I2C0:
• case CLK_I2C1:
• case CLK_I2C2:
• case CLK_I2C3:
• case CLK_I2C4:
• case CLK_I2C5:
• case CLK_I2C6:
• case CLK_I2C7:
• case CLK_I2C8:

• ret = rk3588_i2c_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_SPI0:
• case CLK_SPI1:
• case CLK_SPI2:
• case CLK_SPI3:
• case CLK_SPI4:

• ret = rk3588_spi_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_PWM1:
• case CLK_PWM2:
• case CLK_PWM3:
• case CLK_PMU1PWM:

• ret = rk3588_pwm_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_SARADC:
• case CLK_TSADC:

• ret = rk3588_adc_set_clk(priv, clk->id, rate);
  

• break;
  

• case CCLK_SRC_SDIO:
• case CCLK_EMMC:
• case BCLK_EMMC:
• case SCLK_SFC:
• case DCLK_DECOM:

• ret = rk3588_mmc_set_clk(priv, clk->id, rate);
  

• break;
  

• case TCLK_WDT0:

• ret = OSC_HZ;
  

• break;
  

+#ifndef CONFIG_SPL_BUILD

• case CLK_AUX16M_0:
• case CLK_AUX16M_1:

• rk3588_aux16m_set_clk(priv, clk->id, rate);
  

• break;
  

• case ACLK_VOP_ROOT:
• case ACLK_VOP:
• case ACLK_VOP_LOW_ROOT:
• case HCLK_VOP_ROOT:

• ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate);
  

• break;
  

• case DCLK_VOP0:
• case DCLK_VOP0_SRC:
• case DCLK_VOP1:
• case DCLK_VOP1_SRC:
• case DCLK_VOP2:
• case DCLK_VOP2_SRC:
• case DCLK_VOP3:

• ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_GMAC0_PTP_REF:
• case CLK_GMAC1_PTP_REF:
• case CLK_GMAC_125M:
• case CLK_GMAC_50M:

• ret = rk3588_gmac_set_clk(priv, clk->id, rate);
  

• break;
  

• case SCLK_UART1:
• case SCLK_UART2:
• case SCLK_UART3:
• case SCLK_UART4:
• case SCLK_UART5:
• case SCLK_UART6:
• case SCLK_UART7:
• case SCLK_UART8:
• case SCLK_UART9:

• ret = rk3588_uart_set_rate(priv, clk->id, rate);
  

• break;
  

• case CLK_REF_PIPE_PHY0:
• case CLK_REF_PIPE_PHY1:
• case CLK_REF_PIPE_PHY2:

• ret = rk3588_pciephy_set_rate(priv, clk->id, rate);
  

• break;
  

+#endif

• default:

• return -ENOENT;
  

• }
• return ret;

+};

+#define ROCKCHIP_MMC_DELAY_SEL BIT(10) +#define ROCKCHIP_MMC_DEGREE_MASK 0x3 +#define ROCKCHIP_MMC_DELAYNUM_OFFSET 2 +#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)

+#define PSECS_PER_SEC 1000000000000LL +/*

• • Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
• • simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
• */

+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60

+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA)) +static int __maybe_unused rk3588_dclk_vop_set_parent(struct clk *clk,

• 				     struct clk *parent)
  

+{

• struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
• struct rk3588_cru *cru = priv->cru;
• u32 sel;
• const char *clock_dev_name = parent->dev->name;
• if (parent->id == PLL_V0PLL)

• sel = 2;
  

• else if (parent->id == PLL_GPLL)

• sel = 0;
  

• else if (parent->id == PLL_CPLL)

• sel = 1;
  

• else

• sel = 3;
  

• switch (clk->id) {
• case DCLK_VOP0_SRC:

• rk_clrsetreg(&cru->clksel_con[111], DCLK0_VOP_SRC_SEL_MASK,
  

• 	     sel << DCLK0_VOP_SRC_SEL_SHIFT);
  

• break;
  

• case DCLK_VOP1_SRC:

• rk_clrsetreg(&cru->clksel_con[111], DCLK1_VOP_SRC_SEL_MASK,
  

• 	     sel << DCLK1_VOP_SRC_SEL_SHIFT);
  

• break;
  

• case DCLK_VOP2_SRC:

• rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SRC_SEL_MASK,
  

• 	     sel << DCLK2_VOP_SRC_SEL_SHIFT);
  

• break;
  

• case DCLK_VOP3:

• rk_clrsetreg(&cru->clksel_con[113], DCLK3_VOP_SRC_SEL_MASK,
  

• 	     sel << DCLK3_VOP_SRC_SEL_SHIFT);
  

• break;
  

• case DCLK_VOP0:

• if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
  

• 	sel = 1;
  

• else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
  

• 	sel = 2;
  

• else
  

• 	sel = 0;
  

• rk_clrsetreg(&cru->clksel_con[112], DCLK0_VOP_SEL_MASK,
  

• 	     sel << DCLK0_VOP_SEL_SHIFT);
  

• break;
  

• case DCLK_VOP1:

• if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
  

• 	sel = 1;
  

• else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
  

• 	sel = 2;
  

• else
  

• 	sel = 0;
  

• rk_clrsetreg(&cru->clksel_con[112], DCLK1_VOP_SEL_MASK,
  

• 	     sel << DCLK1_VOP_SEL_SHIFT);
  

• break;
  

• case DCLK_VOP2:

• if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
  

• 	sel = 1;
  

• else if (!strcmp(clock_dev_name, "hdmiphypll_clk1"))
  

• 	sel = 2;
  

• else
  

• 	sel = 0;
  

• rk_clrsetreg(&cru->clksel_con[112], DCLK2_VOP_SEL_MASK,
  

• 	     sel << DCLK2_VOP_SEL_SHIFT);
  

• break;
  

• default:

• return -EINVAL;
  

• }
• return 0;

+}

+static int rk3588_clk_set_parent(struct clk *clk, struct clk *parent) +{

• switch (clk->id) {
• case DCLK_VOP0_SRC:
• case DCLK_VOP1_SRC:
• case DCLK_VOP2_SRC:
• case DCLK_VOP0:
• case DCLK_VOP1:
• case DCLK_VOP2:
• case DCLK_VOP3:

• return rk3588_dclk_vop_set_parent(clk, parent);
  

• default:

• return -ENOENT;
  

• }
• return 0;

+} +#endif

+static struct clk_ops rk3588_clk_ops = {

• .get_rate = rk3588_clk_get_rate,
• .set_rate = rk3588_clk_set_rate,

+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))

• .set_parent = rk3588_clk_set_parent,

+#endif +};

+static void rk3588_clk_init(struct rk3588_clk_priv *priv) +{

• int ret, div;
• div = DIV_ROUND_UP(GPLL_HZ, 300 * MHz);
• rk_clrsetreg(&priv->cru->clksel_con[38],

•      ACLK_BUS_ROOT_SEL_MASK |
  

•      ACLK_BUS_ROOT_DIV_MASK,
  

•      div << ACLK_BUS_ROOT_DIV_SHIFT);
  

• if (priv->cpll_hz != CPLL_HZ) {

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
  

• 			    CPLL, CPLL_HZ);
  

• if (!ret)
  

• 	priv->cpll_hz = CPLL_HZ;
  

• }
• if (priv->gpll_hz != GPLL_HZ) {

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
  

• 			    GPLL, GPLL_HZ);
  

• if (!ret)
  

• 	priv->gpll_hz = GPLL_HZ;
  

• }

+#ifdef CONFIG_PCI

• if (priv->ppll_hz != PPLL_HZ) {

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
  

• 			    PPLL, PPLL_HZ);
  

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• }

+#endif

• rk_clrsetreg(&priv->cru->clksel_con[9],

•      ACLK_TOP_S400_SEL_MASK |
  

•      ACLK_TOP_S200_SEL_MASK,
  

•      (ACLK_TOP_S400_SEL_400M << ACLK_TOP_S400_SEL_SHIFT) |
  

•      (ACLK_TOP_S200_SEL_200M << ACLK_TOP_S200_SEL_SHIFT));
  

+}

+static int rk3588_clk_probe(struct udevice *dev) +{

• struct rk3588_clk_priv *priv = dev_get_priv(dev);
• int ret;
• priv->sync_kernel = false;

+#ifdef CONFIG_SPL_BUILD

• rockchip_pll_set_rate(&rk3588_pll_clks[B0PLL], priv->cru,

• 	      B0PLL, LPLL_HZ);
  

• rockchip_pll_set_rate(&rk3588_pll_clks[B1PLL], priv->cru,

• 	      B1PLL, LPLL_HZ);
  

• if (!priv->armclk_enter_hz) {

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[LPLL], priv->cru,
  

• 			    LPLL, LPLL_HZ);
  

• priv->armclk_enter_hz =
  

• 	rockchip_pll_get_rate(&rk3588_pll_clks[LPLL],
  

• 			      priv->cru, LPLL);
  

• priv->armclk_init_hz = priv->armclk_enter_hz;
  

• }

+#endif

• priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
• if (IS_ERR(priv->grf))

• return PTR_ERR(priv->grf);
  

• rk3588_clk_init(priv);
• /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
• ret = clk_set_defaults(dev, 1);
• if (ret)

• debug("%s clk_set_defaults failed %d\n", __func__, ret);
  

• else

• priv->sync_kernel = true;
  

• return 0;

+}

+static int rk3588_clk_ofdata_to_platdata(struct udevice *dev) +{

• struct rk3588_clk_priv *priv = dev_get_priv(dev);
• priv->cru = dev_read_addr_ptr(dev);
• return 0;

+}

+static int rk3588_clk_bind(struct udevice *dev) +{

• int ret;
• struct udevice *sys_child;
• struct sysreset_reg *priv;
• /* The reset driver does not have a device node, so bind it here */
• ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",

• 		 &sys_child);
  

• if (ret) {

• debug("Warning: No sysreset driver: ret=%d\n", ret);
  

• } else {

• priv = malloc(sizeof(struct sysreset_reg));
  

• priv->glb_srst_fst_value = offsetof(struct rk3588_cru,
  

• 				    glb_srst_fst);
  

• priv->glb_srst_snd_value = offsetof(struct rk3588_cru,
  

• 				    glb_srsr_snd);
  

• dev_set_priv(sys_child, priv);
  

• }

+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)

• ret = offsetof(struct rk3588_cru, softrst_con[0]);
• ret = rockchip_reset_bind(dev, ret, 49158);
• if (ret)

• debug("Warning: software reset driver bind faile\n");
  

+#endif

• return 0;

+}

+static const struct udevice_id rk3588_clk_ids[] = {

• { .compatible = "rockchip,rk3588-cru" },
• { }

+};

+U_BOOT_DRIVER(rockchip_rk3588_cru) = {

• .name = "rockchip_rk3588_cru",
• .id = UCLASS_CLK,
• .of_match = rk3588_clk_ids,
• .priv_auto = sizeof(struct rk3588_clk_priv),
• .of_to_plat = rk3588_clk_ofdata_to_platdata,
• .ops = &rk3588_clk_ops,
• .bind = rk3588_clk_bind,
• .probe = rk3588_clk_probe,

+};

Hi Eugen,

On Thu, 16 Feb 2023 at 14:30, Eugen Hristev eugen.hristev@collabora.com wrote:

On 1/30/23 16:57, Jagan Teki wrote:

...

Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai

---

drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3588.c | 1996 +++++++++++++++++++++++++++++ 2 files changed, 1997 insertions(+) create mode 100644 drivers/clk/rockchip/clk_rk3588.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index f719f4e379..9e379cc2e3 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c

Hello Jagan,

Have you noticed my questions on your previous version? I don't see any changes in your current version on these aspects:

https://patchwork.ozlabs.org/project/uboot/patch/20230125222741.303259-6-jag...

and here

https://patchwork.ozlabs.org/project/uboot/patch/20230125222741.303259-12-ja...

Sorry for the late response, I will respond to it on that thread.

Thanks, Jagan.

Hi Jagan,

On 2023-01-30 15:57, Jagan Teki wrote:

Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai

---

drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3588.c | 1996 +++++++++++++++++++++++++++++ 2 files changed, 1997 insertions(+) create mode 100644 drivers/clk/rockchip/clk_rk3588.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index f719f4e379..9e379cc2e3 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c new file mode 100644 index 0000000000..b87b023bd7 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -0,0 +1,1996 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
• • Author: Elaine Zhang zhangqing@rock-chips.com
• */

+#include <common.h> +#include <bitfield.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch-rockchip/cru_rk3588.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/io.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rk3588-cru.h>

+DECLARE_GLOBAL_DATA_PTR;

+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))

+static struct rockchip_pll_rate_table rk3588_pll_rates[] = {

• /* _mhz, _p, _m, _s, _k */
• RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
• RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
• RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
• RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
• RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
• RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
• RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
• RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
• RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
• RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
• RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
• RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
• RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
• RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
• RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
• RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
• { /* sentinel */ },

+};

+static struct rockchip_pll_clock rk3588_pll_clks[] = {

• [B0PLL] = PLL(pll_rk3588, PLL_B0PLL, RK3588_B0_PLL_CON(0),

•       RK3588_B0_PLL_MODE_CON, 0, 15, 0,
  

•       rk3588_pll_rates),
  

• [B1PLL] = PLL(pll_rk3588, PLL_B1PLL, RK3588_B1_PLL_CON(8),

•       RK3588_B1_PLL_MODE_CON, 0, 15, 0,
  

•       rk3588_pll_rates),
  

• [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3588_LPLL_CON(16),

•      RK3588_LPLL_MODE_CON, 0, 15, 0, rk3588_pll_rates),
  

• [V0PLL] = PLL(pll_rk3588, PLL_V0PLL, RK3588_PLL_CON(88),

•       RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
  

• [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3588_PLL_CON(96),

•       RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
  

• [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3588_PLL_CON(104),

•      RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
  

• [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3588_PLL_CON(112),

•      RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
  

• [NPLL] = PLL(pll_rk3588, PLL_NPLL, RK3588_PLL_CON(120),

•      RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
  

• [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3588_PMU_PLL_CON(128),

•      RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
  

+};

+#ifndef CONFIG_SPL_BUILD +/*

• • rational_best_approximation(31415, 10000,

• • (1 << 8) - 1, (1 << 5) - 1, &n, &d);
    

• • you may look at given_numerator as a fixed point number,
• • with the fractional part size described in given_denominator.
• • for theoretical background, see:
• • http://en.wikipedia.org/wiki/Continued_fraction
• */

+static void rational_best_approximation(unsigned long given_numerator,

• 			unsigned long given_denominator,
  

• 			unsigned long max_numerator,
  

• 			unsigned long max_denominator,
  

• 			unsigned long *best_numerator,
  

• 			unsigned long *best_denominator)
  

+{

• unsigned long n, d, n0, d0, n1, d1;
• n = given_numerator;
• d = given_denominator;
• n0 = 0;
• d1 = 0;
• n1 = 1;
• d0 = 1;
• for (;;) {

• unsigned long t, a;
  

• if (n1 > max_numerator || d1 > max_denominator) {
  

• 	n1 = n0;
  

• 	d1 = d0;
  

• 	break;
  

• }
  

• if (d == 0)
  

• 	break;
  

• t = d;
  

• a = n / d;
  

• d = n % d;
  

• n = t;
  

• t = n0 + a * n1;
  

• n0 = n1;
  

• n1 = t;
  

• t = d0 + a * d1;
  

• d0 = d1;
  

• d1 = t;
  

• }
• *best_numerator = n1;
• *best_denominator = d1;

+} +#endif

[...]

+static ulong rk3588_top_get_clk(struct rk3588_clk_priv *priv, ulong clk_id) +{

• struct rk3588_cru *cru = priv->cru;
• u32 con, sel, div, rate, prate;
• switch (clk_id) {
• case ACLK_TOP_ROOT:

• con = readl(&cru->clksel_con[8]);
  

• div = (con & ACLK_TOP_ROOT_DIV_MASK) >>
  

•       ACLK_TOP_ROOT_DIV_SHIFT;
  

• sel = (con & ACLK_TOP_ROOT_SRC_SEL_MASK) >>
  

•       ACLK_TOP_ROOT_SRC_SEL_SHIFT;
  

• if (sel == ACLK_TOP_ROOT_SRC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = priv->cpll_hz;
  

Should be gpll_hz instead of cpll_hz.

• return DIV_TO_RATE(prate, div);
  

• case ACLK_LOW_TOP_ROOT:

• con = readl(&cru->clksel_con[8]);
  

• div = (con & ACLK_LOW_TOP_ROOT_DIV_MASK) >>
  

•       ACLK_LOW_TOP_ROOT_DIV_SHIFT;
  

• sel = (con & ACLK_LOW_TOP_ROOT_SRC_SEL_MASK) >>
  

•       ACLK_LOW_TOP_ROOT_SRC_SEL_SHIFT;
  

• if (sel == ACLK_LOW_TOP_ROOT_SRC_SEL_CPLL)
  

• 	prate = priv->cpll_hz;
  

• else
  

• 	prate = priv->gpll_hz;
  

• return DIV_TO_RATE(prate, div);
  

• case PCLK_TOP_ROOT:

• con = readl(&cru->clksel_con[8]);
  

• sel = (con & PCLK_TOP_ROOT_SEL_MASK) >> PCLK_TOP_ROOT_SEL_SHIFT;
  

• if (sel == PCLK_TOP_ROOT_SEL_100M)
  

• 	rate = 100 * MHz;
  

• else if (sel == PCLK_TOP_ROOT_SEL_50M)
  

• 	rate = 50 * MHz;
  

• else
  

• 	rate = OSC_HZ;
  

• break;
  

• default:

• return -ENOENT;
  

• }
• return rate;

+}

[...]

+static ulong rk3588_clk_get_rate(struct clk *clk) +{

• struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
• ulong rate = 0;
• if (!priv->gpll_hz) {

• printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  

• return -ENOENT;
  

• }
• if (!priv->ppll_hz) {

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• }
• switch (clk->id) {
• case PLL_LPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[LPLL], priv->cru,
  

• 			     LPLL);
  

• break;
  

• case PLL_B0PLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[B0PLL], priv->cru,
  

• 			     B0PLL);
  

• break;
  

• case PLL_B1PLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[B1PLL], priv->cru,
  

• 			     B1PLL);
  

• break;
  

• case PLL_GPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL], priv->cru,
  

• 			     GPLL);
  

• break;
  

• case PLL_CPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL], priv->cru,
  

• 			     CPLL);
  

• break;
  

• case PLL_NPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[NPLL], priv->cru,
  

• 			     NPLL);
  

• break;
  

• case PLL_V0PLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL], priv->cru,
  

• 			     V0PLL);
  

• break;
  

• case PLL_AUPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL], priv->cru,
  

• 			     AUPLL);
  

• break;
  

• case PLL_PPLL:

• rate = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL], priv->cru,
  

• 			     PPLL);
  

• break;
  

• case ACLK_CENTER_ROOT:
• case PCLK_CENTER_ROOT:
• case HCLK_CENTER_ROOT:
• case ACLK_CENTER_LOW_ROOT:

• rate = rk3588_center_get_clk(priv, clk->id);
  

• break;
  

• case ACLK_TOP_ROOT:
• case PCLK_TOP_ROOT:
• case ACLK_LOW_TOP_ROOT:

• rate = rk3588_top_get_clk(priv, clk->id);
  

• break;
  

• case CLK_I2C0:
• case CLK_I2C1:
• case CLK_I2C2:
• case CLK_I2C3:
• case CLK_I2C4:
• case CLK_I2C5:
• case CLK_I2C6:
• case CLK_I2C7:
• case CLK_I2C8:

• rate = rk3588_i2c_get_clk(priv, clk->id);
  

• break;
  

• case CLK_SPI0:
• case CLK_SPI1:
• case CLK_SPI2:
• case CLK_SPI3:
• case CLK_SPI4:

• rate = rk3588_spi_get_clk(priv, clk->id);
  

• break;
  

• case CLK_PWM1:
• case CLK_PWM2:
• case CLK_PWM3:
• case CLK_PMU1PWM:

• rate = rk3588_pwm_get_clk(priv, clk->id);
  

• break;
  

• case CLK_SARADC:
• case CLK_TSADC:

• rate = rk3588_adc_get_clk(priv, clk->id);
  

• break;
  

• case CCLK_SRC_SDIO:
• case CCLK_EMMC:
• case BCLK_EMMC:
• case SCLK_SFC:
• case DCLK_DECOM:

• rate = rk3588_mmc_get_clk(priv, clk->id);
  

• break;
  

• case TCLK_WDT0:

• rate = OSC_HZ;
  

• break;
  

+#ifndef CONFIG_SPL_BUILD

• case CLK_AUX16M_0:
• case CLK_AUX16M_1:

• rk3588_aux16m_get_clk(priv, clk->id);
  

This is missing "rate =" before function call.

• break;
  

• case ACLK_VOP_ROOT:
• case ACLK_VOP:
• case ACLK_VOP_LOW_ROOT:
• case HCLK_VOP_ROOT:

• rate = rk3588_aclk_vop_get_clk(priv, clk->id);
  

• break;
  

• case DCLK_VOP0:
• case DCLK_VOP0_SRC:
• case DCLK_VOP1:
• case DCLK_VOP1_SRC:
• case DCLK_VOP2:
• case DCLK_VOP2_SRC:
• case DCLK_VOP3:

• rate = rk3588_dclk_vop_get_clk(priv, clk->id);
  

• break;
  

• case CLK_GMAC0_PTP_REF:
• case CLK_GMAC1_PTP_REF:
• case CLK_GMAC_125M:
• case CLK_GMAC_50M:

• rate = rk3588_gmac_get_clk(priv, clk->id);
  

• break;
  

• case SCLK_UART1:
• case SCLK_UART2:
• case SCLK_UART3:
• case SCLK_UART4:
• case SCLK_UART5:
• case SCLK_UART6:
• case SCLK_UART7:
• case SCLK_UART8:
• case SCLK_UART9:

• rate = rk3588_uart_get_rate(priv, clk->id);
  

• break;
  

• case CLK_REF_PIPE_PHY0:
• case CLK_REF_PIPE_PHY1:
• case CLK_REF_PIPE_PHY2:

• rate = rk3588_pciephy_get_rate(priv, clk->id);
  

• break;
  

+#endif

• default:

• return -ENOENT;
  

• }
• return rate;

+};

+static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate) +{

• struct rk3588_clk_priv *priv = dev_get_priv(clk->dev);
• ulong ret = 0;
• if (!priv->gpll_hz) {

• printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
  

• return -ENOENT;
  

• }
• if (!priv->ppll_hz) {

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• }
• switch (clk->id) {
• case PLL_CPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[CPLL], priv->cru,
  

• 			    CPLL, rate);
  

• priv->cpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[CPLL],
  

• 				      priv->cru, CPLL);
  

• break;
  

• case PLL_GPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[GPLL], priv->cru,
  

• 			    GPLL, rate);
  

• priv->gpll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[GPLL],
  

• 				      priv->cru, GPLL);
  

• break;
  

• case PLL_NPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[NPLL], priv->cru,
  

• 			    NPLL, rate);
  

• break;
  

• case PLL_V0PLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL], priv->cru,
  

• 			    V0PLL, rate);
  

• priv->v0pll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
  

• 				       priv->cru, V0PLL);
  

• break;
  

• case PLL_AUPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[AUPLL], priv->cru,
  

• 			    AUPLL, rate);
  

• priv->aupll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[AUPLL],
  

• 				       priv->cru, AUPLL);
  

• break;
  

• case PLL_PPLL:

• ret = rockchip_pll_set_rate(&rk3588_pll_clks[PPLL], priv->cru,
  

• 			    PPLL, rate);
  

• priv->ppll_hz = rockchip_pll_get_rate(&rk3588_pll_clks[PPLL],
  

• 				      priv->cru, PPLL);
  

• break;
  

• case ACLK_CENTER_ROOT:
• case PCLK_CENTER_ROOT:
• case HCLK_CENTER_ROOT:
• case ACLK_CENTER_LOW_ROOT:

• ret = rk3588_center_set_clk(priv, clk->id, rate);
  

• break;
  

• case ACLK_TOP_ROOT:
• case PCLK_TOP_ROOT:
• case ACLK_LOW_TOP_ROOT:

• ret = rk3588_top_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_I2C0:
• case CLK_I2C1:
• case CLK_I2C2:
• case CLK_I2C3:
• case CLK_I2C4:
• case CLK_I2C5:
• case CLK_I2C6:
• case CLK_I2C7:
• case CLK_I2C8:

• ret = rk3588_i2c_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_SPI0:
• case CLK_SPI1:
• case CLK_SPI2:
• case CLK_SPI3:
• case CLK_SPI4:

• ret = rk3588_spi_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_PWM1:
• case CLK_PWM2:
• case CLK_PWM3:
• case CLK_PMU1PWM:

• ret = rk3588_pwm_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_SARADC:
• case CLK_TSADC:

• ret = rk3588_adc_set_clk(priv, clk->id, rate);
  

• break;
  

• case CCLK_SRC_SDIO:
• case CCLK_EMMC:
• case BCLK_EMMC:
• case SCLK_SFC:
• case DCLK_DECOM:

• ret = rk3588_mmc_set_clk(priv, clk->id, rate);
  

• break;
  

• case TCLK_WDT0:

• ret = OSC_HZ;
  

• break;
  

+#ifndef CONFIG_SPL_BUILD

• case CLK_AUX16M_0:
• case CLK_AUX16M_1:

• rk3588_aux16m_set_clk(priv, clk->id, rate);
  

This is missing "ret = " before function call.

Regards, Jonas

• break;
  

• case ACLK_VOP_ROOT:
• case ACLK_VOP:
• case ACLK_VOP_LOW_ROOT:
• case HCLK_VOP_ROOT:

• ret = rk3588_aclk_vop_set_clk(priv, clk->id, rate);
  

• break;
  

• case DCLK_VOP0:
• case DCLK_VOP0_SRC:
• case DCLK_VOP1:
• case DCLK_VOP1_SRC:
• case DCLK_VOP2:
• case DCLK_VOP2_SRC:
• case DCLK_VOP3:

• ret = rk3588_dclk_vop_set_clk(priv, clk->id, rate);
  

• break;
  

• case CLK_GMAC0_PTP_REF:
• case CLK_GMAC1_PTP_REF:
• case CLK_GMAC_125M:
• case CLK_GMAC_50M:

• ret = rk3588_gmac_set_clk(priv, clk->id, rate);
  

• break;
  

• case SCLK_UART1:
• case SCLK_UART2:
• case SCLK_UART3:
• case SCLK_UART4:
• case SCLK_UART5:
• case SCLK_UART6:
• case SCLK_UART7:
• case SCLK_UART8:
• case SCLK_UART9:

• ret = rk3588_uart_set_rate(priv, clk->id, rate);
  

• break;
  

• case CLK_REF_PIPE_PHY0:
• case CLK_REF_PIPE_PHY1:
• case CLK_REF_PIPE_PHY2:

• ret = rk3588_pciephy_set_rate(priv, clk->id, rate);
  

• break;
  

+#endif

• default:

• return -ENOENT;
  

• }
• return ret;

+};

[...]

On 2023/1/30 22:57, Jagan Teki wrote:

Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

arch/arm/include/asm/arch-rockchip/clock.h | 24 ++ drivers/clk/rockchip/clk_pll.c | 267 ++++++++++++++++++++- 2 files changed, 288 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 566bdcc4fa..90e66c7da0 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -22,6 +22,14 @@ enum { ROCKCHIP_SYSCON_PMUSGRF, ROCKCHIP_SYSCON_CIC, ROCKCHIP_SYSCON_MSCH,

• ROCKCHIP_SYSCON_USBGRF,

• ROCKCHIP_SYSCON_PCIE30_PHY_GRF,

• ROCKCHIP_SYSCON_PHP_GRF,

• ROCKCHIP_SYSCON_PIPE_PHY0_GRF,

• ROCKCHIP_SYSCON_PIPE_PHY1_GRF,

• ROCKCHIP_SYSCON_PIPE_PHY2_GRF,

• ROCKCHIP_SYSCON_VOP_GRF,

• ROCKCHIP_SYSCON_VO_GRF, };

  /* Standard Rockchip clock numbers */

@@ -61,6 +69,15 @@ enum rk_clk_id { .frac = _frac, \ }

+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \ +{ \

• .rate = _rate##U, \
• .p = _p, \
• .m = _m, \
• .s = _s, \
• .k = _k, \

+}

• struct rockchip_pll_rate_table { unsigned long rate; unsigned int nr;

@@ -74,6 +91,11 @@ struct rockchip_pll_rate_table { unsigned int postdiv2; unsigned int dsmpd; unsigned int frac;

• /* for RK3588 */

• unsigned int m;

• unsigned int p;

• unsigned int s;

• unsigned int k; };

  enum rockchip_pll_type {

@@ -82,6 +104,7 @@ enum rockchip_pll_type { pll_rk3328, pll_rk3366, pll_rk3399,

• pll_rk3588, };

  struct rockchip_pll_clock {

@@ -171,5 +194,6 @@ int rockchip_get_clk(struct udevice **devp);

• Return: 0 success, or error value

*/ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); +int rockchip_get_scmi_clk(struct udevice **devp);

#endif diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 09b97cf57a..d657ef38f3 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -45,6 +45,10 @@ enum {

#define MIN_FOUTVCO_FREQ (800 * MHZ) #define MAX_FOUTVCO_FREQ (2000 * MHZ) +#define RK3588_VCO_MIN_HZ (2250UL * MHZ) +#define RK3588_VCO_MAX_HZ (4500UL * MHZ) +#define RK3588_FOUT_MIN_HZ (37UL * MHZ) +#define RK3588_FOUT_MAX_HZ (4500UL * MHZ)

int gcd(int m, int n) { @@ -164,6 +168,65 @@ rockchip_pll_clk_set_by_auto(ulong fin_hz, return rate_table; }

+static struct rockchip_pll_rate_table * +rk3588_pll_clk_set_by_auto(unsigned long fin_hz,

• 	   unsigned long fout_hz)
  

+{

• struct rockchip_pll_rate_table *rate_table = &rockchip_auto_table;
• u32 p, m, s;
• ulong fvco, fref, fout, ffrac;
• if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)

• return NULL;
  

• if (fout_hz > RK3588_FOUT_MAX_HZ || fout_hz < RK3588_FOUT_MIN_HZ)

• return NULL;
  

• if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {

• for (s = 0; s <= 6; s++) {
  

• 	fvco = fout_hz << s;
  

• 	if (fvco < RK3588_VCO_MIN_HZ ||
  

• 	    fvco > RK3588_VCO_MAX_HZ)
  

• 		continue;
  

• 	for (p = 2; p <= 4; p++) {
  

• 		for (m = 64; m <= 1023; m++) {
  

• 			if (fvco == m * fin_hz / p) {
  

• 				rate_table->p = p;
  

• 				rate_table->m = m;
  

• 				rate_table->s = s;
  

• 				rate_table->k = 0;
  

• 				return rate_table;
  

• 			}
  

• 		}
  

• 	}
  

• }
  

• pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
  

• } else {

• for (s = 0; s <= 6; s++) {
  

• 	fvco = fout_hz << s;
  

• 	if (fvco < RK3588_VCO_MIN_HZ ||
  

• 	    fvco > RK3588_VCO_MAX_HZ)
  

• 		continue;
  

• 	for (p = 1; p <= 4; p++) {
  

• 		for (m = 64; m <= 1023; m++) {
  

• 			if ((fvco >= m * fin_hz / p) && (fvco < (m + 1) * fin_hz / p)) {
  

• 				rate_table->p = p;
  

• 				rate_table->m = m;
  

• 				rate_table->s = s;
  

• 				fref = fin_hz / p;
  

• 				ffrac = fvco - (m * fref);
  

• 				fout = ffrac * 65536;
  

• 				rate_table->k = fout / fref;
  

• 				return rate_table;
  

• 			}
  

• 		}
  

• 	}
  

• }
  

• pr_err("CANNOT FIND Fout by auto,fout = %lu\n", fout_hz);
  

• }
• return NULL;

+}

• static const struct rockchip_pll_rate_table * rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) {

@@ -174,10 +237,14 @@ rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) break; rate_table++; }

• if (rate_table->rate != rate)

• return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
  

• else

• if (rate_table->rate != rate) {

• if (pll->type == pll_rk3588)
  

• 	return rk3588_pll_clk_set_by_auto(24 * MHZ, rate);
  

• else
  

• 	return rockchip_pll_clk_set_by_auto(24 * MHZ, rate);
  

• } else { return rate_table;

• } }

  static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,

@@ -296,6 +363,192 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, } }

+#define RK3588_PLLCON(i) ((i) * 0x4) +#define RK3588_PLLCON0_M_MASK 0x3ff << 0 +#define RK3588_PLLCON0_M_SHIFT 0 +#define RK3588_PLLCON1_P_MASK 0x3f << 0 +#define RK3588_PLLCON1_P_SHIFT 0 +#define RK3588_PLLCON1_S_MASK 0x7 << 6 +#define RK3588_PLLCON1_S_SHIFT 6 +#define RK3588_PLLCON2_K_MASK 0xffff +#define RK3588_PLLCON2_K_SHIFT 0 +#define RK3588_PLLCON1_PWRDOWN BIT(13) +#define RK3588_PLLCON6_LOCK_STATUS BIT(15) +#define RK3588_B0PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x50000 + 0x300) +#define RK3588_B1PLL_CLKSEL_CON(i) ((i) * 0x4 + 0x52000 + 0x300) +#define RK3588_LPLL_CLKSEL_CON(i) ((i) * 0x4 + 0x58000 + 0x300) +#define RK3588_CORE_DIV_MASK 0x1f +#define RK3588_CORE_L02_DIV_SHIFT 0 +#define RK3588_CORE_L13_DIV_SHIFT 7 +#define RK3588_CORE_B02_DIV_SHIFT 8 +#define RK3588_CORE_B13_DIV_SHIFT 0

+static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll,

• 	       void __iomem *base, ulong pll_id,
  

• 	       ulong drate)
  

+{

• const struct rockchip_pll_rate_table *rate;
• rate = rockchip_get_pll_settings(pll, drate);
• if (!rate) {

• printf("%s unsupported rate\n", __func__);
  

• return -EINVAL;
  

• }
• debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",

•      __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
  

• /*

• * When power on or changing PLL setting,
  

• * we must force PLL into slow mode to ensure output stable clock.
  

• */
  

• if (pll_id == 3)

• rk_clrsetreg(base + 0x84c, 0x1 << 1, 0x1 << 1);
  

• rk_clrsetreg(base + pll->mode_offset,

•      pll->mode_mask << pll->mode_shift,
  

•      RKCLK_PLL_MODE_SLOW << pll->mode_shift);
  

• if (pll_id == 0)

• rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
  

• 	     pll->mode_mask << 6,
  

• 	     RKCLK_PLL_MODE_SLOW << 6);
  

• else if (pll_id == 1)

• rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
  

• 	     pll->mode_mask << 6,
  

• 	     RKCLK_PLL_MODE_SLOW << 6);
  

• else if (pll_id == 2)

• rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
  

• 	     pll->mode_mask << 14,
  

• 	     RKCLK_PLL_MODE_SLOW << 14);
  

• /* Power down */
• rk_setreg(base + pll->con_offset + RK3588_PLLCON(1),

•   RK3588_PLLCON1_PWRDOWN);
  

• rk_clrsetreg(base + pll->con_offset,

•      RK3588_PLLCON0_M_MASK,
  

•      (rate->m << RK3588_PLLCON0_M_SHIFT));
  

• rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1),

•      (RK3588_PLLCON1_P_MASK |
  

•      RK3588_PLLCON1_S_MASK),
  

•      (rate->p << RK3588_PLLCON1_P_SHIFT |
  

•      rate->s << RK3588_PLLCON1_S_SHIFT));
  

• if (rate->k) {

• rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2),
  

• 	     RK3588_PLLCON2_K_MASK,
  

• 	     rate->k << RK3588_PLLCON2_K_SHIFT);
  

• }
• /* Power up */
• rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1),

•   RK3588_PLLCON1_PWRDOWN);
  

• /* waiting for pll lock */
• while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) &

• RK3588_PLLCON6_LOCK_STATUS)) {
  

• udelay(1);
  

• debug("%s: wait pll lock, pll_id=%ld\n", __func__, pll_id);
  

• }
• rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,

•      RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
  

• if (pll_id == 0) {

• rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
  

• 	     pll->mode_mask << 6,
  

• 	     2 << 6);
  

• rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(0),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_B02_DIV_SHIFT);
  

• rk_clrsetreg(base + RK3588_B0PLL_CLKSEL_CON(1),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_B13_DIV_SHIFT);
  

• } else if (pll_id == 1) {

• rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
  

• 	     pll->mode_mask << 6,
  

• 	     2 << 6);
  

• rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(0),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_B02_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_B02_DIV_SHIFT);
  

• rk_clrsetreg(base + RK3588_B1PLL_CLKSEL_CON(1),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_B13_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_B13_DIV_SHIFT);
  

• } else if (pll_id == 2) {

• rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(5),
  

• 	     pll->mode_mask << 14,
  

• 	     2 << 14);
  

• rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_L13_DIV_SHIFT);
  

• rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(6),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_L02_DIV_SHIFT);
  

• rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_L13_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_L13_DIV_SHIFT);
  

• rk_clrsetreg(base + RK3588_LPLL_CLKSEL_CON(7),
  

• 	     RK3588_CORE_DIV_MASK << RK3588_CORE_L02_DIV_SHIFT,
  

• 	     0 << RK3588_CORE_L02_DIV_SHIFT);
  

• }
• if (pll_id == 3)

• rk_clrsetreg(base + 0x84c, 0x1 << 1, 0);
  

• debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",

•      pll, readl(base + pll->con_offset),
  

•      readl(base + pll->con_offset + 0x4),
  

•      readl(base + pll->con_offset + 0x8),
  

•      readl(base + pll->mode_offset));
  

• return 0;

+}

+static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll,

• 		 void __iomem *base, ulong pll_id)
  

+{

• u32 m, p, s, k;
• u32 con = 0, shift, mode;
• u64 rate, postdiv;
• con = readl(base + pll->mode_offset);
• shift = pll->mode_shift;
• if (pll_id == 8)

• mode = RKCLK_PLL_MODE_NORMAL;
  

• else

• mode = (con & (pll->mode_mask << shift)) >> shift;
  

• switch (mode) {
• case RKCLK_PLL_MODE_SLOW:

• return OSC_HZ;
  

• case RKCLK_PLL_MODE_NORMAL:

• /* normal mode */
  

• con = readl(base + pll->con_offset);
  

• m = (con & RK3588_PLLCON0_M_MASK) >>
  

• 	   RK3588_PLLCON0_M_SHIFT;
  

• con = readl(base + pll->con_offset + RK3588_PLLCON(1));
  

• p = (con & RK3588_PLLCON1_P_MASK) >>
  

• 	   RK3036_PLLCON0_FBDIV_SHIFT;
  

• s = (con & RK3588_PLLCON1_S_MASK) >>
  

• 	 RK3588_PLLCON1_S_SHIFT;
  

• con = readl(base + pll->con_offset + RK3588_PLLCON(2));
  

• k = (con & RK3588_PLLCON2_K_MASK) >>
  

• 	RK3588_PLLCON2_K_SHIFT;
  

• rate = OSC_HZ / p;
  

• rate *= m;
  

• if (k) {
  

• 	/* fractional mode */
  

• 	u64 frac_rate64 = OSC_HZ * k;
  

• 	postdiv = p * 65536;
  

• 	do_div(frac_rate64, postdiv);
  

• 	rate += frac_rate64;
  

• }
  

• rate = rate >> s;
  

• return rate;
  

• case RKCLK_PLL_MODE_DEEP:
• default:

• return 32768;
  

• }

+}

• ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, void __iomem *base, ulong pll_id)

@@ -311,6 +564,10 @@ ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, pll->mode_mask = PLL_RK3328_MODE_MASK; rate = rk3036_pll_get_rate(pll, base, pll_id); break;

• case pll_rk3588:

• pll->mode_mask = PLL_MODE_MASK;
  

• rate = rk3588_pll_get_rate(pll, base, pll_id);
  

• break;
  

  default: printf("%s: Unknown pll type for pll clk %ld\n", __func__, pll_id);

@@ -336,6 +593,10 @@ int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, pll->mode_mask = PLL_RK3328_MODE_MASK; ret = rk3036_pll_set_rate(pll, base, pll_id, drate); break;

• case pll_rk3588:

• pll->mode_mask = PLL_MODE_MASK;
  

• ret = rk3588_pll_set_rate(pll, base, pll_id, drate);
  

• break;
  

  default: printf("%s: Unknown pll type for pll clk %ld\n", __func__, pll_id);

On 2023/1/30 22:57, Jagan Teki wrote:

Add ddr driver for rk3588 to get the ram capacity.

Co-developed-by: Jonas Karlman jonas@kwiboo.se Signed-off-by: Jonas Karlman jonas@kwiboo.se Signed-off-by: Jagan Teki jagan@edgeble.ai

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/ram/rockchip/Makefile | 1 + drivers/ram/rockchip/sdram_rk3588.c | 57 +++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 drivers/ram/rockchip/sdram_rk3588.c

diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile index 98839ad6a6..36dc0500da 100644 --- a/drivers/ram/rockchip/Makefile +++ b/drivers/ram/rockchip/Makefile @@ -14,5 +14,6 @@ obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o +obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o diff --git a/drivers/ram/rockchip/sdram_rk3588.c b/drivers/ram/rockchip/sdram_rk3588.c new file mode 100644 index 0000000000..cf56e2a941 --- /dev/null +++ b/drivers/ram/rockchip/sdram_rk3588.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • (C) Copyright 2021 Rockchip Electronics Co., Ltd.
• */

+#include <common.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3588.h> +#include <asm/arch-rockchip/sdram.h>

+struct dram_info {

• struct ram_info info;
• struct rk3588_pmu1grf *pmugrf;

+};

+static int rk3588_dmc_probe(struct udevice *dev) +{

• struct dram_info *priv = dev_get_priv(dev);
• priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
• priv->info.base = CFG_SYS_SDRAM_BASE;
• priv->info.size =

• rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]) +
  

• rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[4]);
  

• return 0;

+}

+static int rk3588_dmc_get_info(struct udevice *dev, struct ram_info *info) +{

• struct dram_info *priv = dev_get_priv(dev);
• *info = priv->info;
• return 0;

+}

+static struct ram_ops rk3588_dmc_ops = {

• .get_info = rk3588_dmc_get_info,

+};

+static const struct udevice_id rk3588_dmc_ids[] = {

• { .compatible = "rockchip,rk3588-dmc" },
• { }

+};

+U_BOOT_DRIVER(dmc_rk3588) = {

• .name = "rockchip_rk3588_dmc",
• .id = UCLASS_RAM,
• .of_match = rk3588_dmc_ids,
• .ops = &rk3588_dmc_ops,
• .probe = rk3588_dmc_probe,
• .priv_auto = sizeof(struct dram_info),

+};

On 2023/1/30 22:57, Jagan Teki wrote:

Add power-domain header for RK3588 SoC from description in TRM.

commit <67944950c2d0> ("dt-bindings: power: add power-domain header for rk3588")

Signed-off-by: Finley Xiao finley.xiao@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

include/dt-bindings/power/rk3588-power.h | 69 ++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 include/dt-bindings/power/rk3588-power.h

diff --git a/include/dt-bindings/power/rk3588-power.h b/include/dt-bindings/power/rk3588-power.h new file mode 100644 index 0000000000..1b92fec013 --- /dev/null +++ b/include/dt-bindings/power/rk3588-power.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +#ifndef __DT_BINDINGS_POWER_RK3588_POWER_H__ +#define __DT_BINDINGS_POWER_RK3588_POWER_H__

+/* VD_LITDSU */ +#define RK3588_PD_CPU_0 0 +#define RK3588_PD_CPU_1 1 +#define RK3588_PD_CPU_2 2 +#define RK3588_PD_CPU_3 3

+/* VD_BIGCORE0 */ +#define RK3588_PD_CPU_4 4 +#define RK3588_PD_CPU_5 5

+/* VD_BIGCORE1 */ +#define RK3588_PD_CPU_6 6 +#define RK3588_PD_CPU_7 7

+/* VD_NPU */ +#define RK3588_PD_NPU 8 +#define RK3588_PD_NPUTOP 9 +#define RK3588_PD_NPU1 10 +#define RK3588_PD_NPU2 11

+/* VD_GPU */ +#define RK3588_PD_GPU 12

+/* VD_VCODEC */ +#define RK3588_PD_VCODEC 13 +#define RK3588_PD_RKVDEC0 14 +#define RK3588_PD_RKVDEC1 15 +#define RK3588_PD_VENC0 16 +#define RK3588_PD_VENC1 17

+/* VD_DD01 */ +#define RK3588_PD_DDR01 18

+/* VD_DD23 */ +#define RK3588_PD_DDR23 19

+/* VD_LOGIC */ +#define RK3588_PD_CENTER 20 +#define RK3588_PD_VDPU 21 +#define RK3588_PD_RGA30 22 +#define RK3588_PD_AV1 23 +#define RK3588_PD_VOP 24 +#define RK3588_PD_VO0 25 +#define RK3588_PD_VO1 26 +#define RK3588_PD_VI 27 +#define RK3588_PD_ISP1 28 +#define RK3588_PD_FEC 29 +#define RK3588_PD_RGA31 30 +#define RK3588_PD_USB 31 +#define RK3588_PD_PHP 32 +#define RK3588_PD_GMAC 33 +#define RK3588_PD_PCIE 34 +#define RK3588_PD_NVM 35 +#define RK3588_PD_NVM0 36 +#define RK3588_PD_SDIO 37 +#define RK3588_PD_AUDIO 38 +#define RK3588_PD_SECURE 39 +#define RK3588_PD_SDMMC 40 +#define RK3588_PD_CRYPTO 41 +#define RK3588_PD_BUS 42

+/* VD_PMU */ +#define RK3588_PD_PMU1 43

+#endif

On 2023/1/30 22:57, Jagan Teki wrote:

Add reset ID defines for rk3588.

commit <0a8eb7dae617> ("dt-bindings: reset: add rk3588 reset definitions")

Signed-off-by: Sebastian Reichel sebastian.reichel@collabora.com Signed-off-by: Jagan Teki jagan@edgeble.ai

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

.../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++++++++++++++++ 1 file changed, 754 insertions(+) create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h

diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h new file mode 100644 index 0000000000..738e56aead --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h @@ -0,0 +1,754 @@ +/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/*

• • Copyright (c) 2021 Rockchip Electronics Co. Ltd.
• • Copyright (c) 2022 Collabora Ltd.
• • Author: Elaine Zhang zhangqing@rock-chips.com
• • Author: Sebastian Reichel sebastian.reichel@collabora.com
• */

+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H

+#define SRST_A_TOP_BIU 0 +#define SRST_P_TOP_BIU 1 +#define SRST_P_CSIPHY0 2 +#define SRST_CSIPHY0 3 +#define SRST_P_CSIPHY1 4 +#define SRST_CSIPHY1 5 +#define SRST_A_TOP_M500_BIU 6

+#define SRST_A_TOP_M400_BIU 7 +#define SRST_A_TOP_S200_BIU 8 +#define SRST_A_TOP_S400_BIU 9 +#define SRST_A_TOP_M300_BIU 10 +#define SRST_USBDP_COMBO_PHY0_INIT 11 +#define SRST_USBDP_COMBO_PHY0_CMN 12 +#define SRST_USBDP_COMBO_PHY0_LANE 13 +#define SRST_USBDP_COMBO_PHY0_PCS 14 +#define SRST_USBDP_COMBO_PHY1_INIT 15

+#define SRST_USBDP_COMBO_PHY1_CMN 16 +#define SRST_USBDP_COMBO_PHY1_LANE 17 +#define SRST_USBDP_COMBO_PHY1_PCS 18 +#define SRST_DCPHY0 19 +#define SRST_P_MIPI_DCPHY0 20 +#define SRST_P_MIPI_DCPHY0_GRF 21

+#define SRST_DCPHY1 22 +#define SRST_P_MIPI_DCPHY1 23 +#define SRST_P_MIPI_DCPHY1_GRF 24 +#define SRST_P_APB2ASB_SLV_CDPHY 25 +#define SRST_P_APB2ASB_SLV_CSIPHY 26 +#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 +#define SRST_P_APB2ASB_SLV_VCCIO6 28 +#define SRST_P_APB2ASB_SLV_EMMCIO 29 +#define SRST_P_APB2ASB_SLV_IOC_TOP 30 +#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31

+#define SRST_P_CRU 32 +#define SRST_A_CHANNEL_SECURE2VO1USB 33 +#define SRST_A_CHANNEL_SECURE2CENTER 34 +#define SRST_H_CHANNEL_SECURE2VO1USB 35 +#define SRST_H_CHANNEL_SECURE2CENTER 36

+#define SRST_P_CHANNEL_SECURE2VO1USB 37 +#define SRST_P_CHANNEL_SECURE2CENTER 38

+#define SRST_H_AUDIO_BIU 39 +#define SRST_P_AUDIO_BIU 40 +#define SRST_H_I2S0_8CH 41 +#define SRST_M_I2S0_8CH_TX 42 +#define SRST_M_I2S0_8CH_RX 43 +#define SRST_P_ACDCDIG 44 +#define SRST_H_I2S2_2CH 45 +#define SRST_H_I2S3_2CH 46

+#define SRST_M_I2S2_2CH 47 +#define SRST_M_I2S3_2CH 48 +#define SRST_DAC_ACDCDIG 49 +#define SRST_H_SPDIF0 50

+#define SRST_M_SPDIF0 51 +#define SRST_H_SPDIF1 52 +#define SRST_M_SPDIF1 53 +#define SRST_H_PDM1 54 +#define SRST_PDM1 55

+#define SRST_A_BUS_BIU 56 +#define SRST_P_BUS_BIU 57 +#define SRST_A_GIC 58 +#define SRST_A_GIC_DBG 59 +#define SRST_A_DMAC0 60 +#define SRST_A_DMAC1 61 +#define SRST_A_DMAC2 62 +#define SRST_P_I2C1 63 +#define SRST_P_I2C2 64 +#define SRST_P_I2C3 65 +#define SRST_P_I2C4 66 +#define SRST_P_I2C5 67 +#define SRST_P_I2C6 68 +#define SRST_P_I2C7 69 +#define SRST_P_I2C8 70

+#define SRST_I2C1 71 +#define SRST_I2C2 72 +#define SRST_I2C3 73 +#define SRST_I2C4 74 +#define SRST_I2C5 75 +#define SRST_I2C6 76 +#define SRST_I2C7 77 +#define SRST_I2C8 78 +#define SRST_P_CAN0 79 +#define SRST_CAN0 80 +#define SRST_P_CAN1 81 +#define SRST_CAN1 82 +#define SRST_P_CAN2 83 +#define SRST_CAN2 84 +#define SRST_P_SARADC 85

+#define SRST_P_TSADC 86 +#define SRST_TSADC 87 +#define SRST_P_UART1 88 +#define SRST_P_UART2 89 +#define SRST_P_UART3 90 +#define SRST_P_UART4 91 +#define SRST_P_UART5 92 +#define SRST_P_UART6 93 +#define SRST_P_UART7 94 +#define SRST_P_UART8 95 +#define SRST_P_UART9 96 +#define SRST_S_UART1 97

+#define SRST_S_UART2 98 +#define SRST_S_UART3 99 +#define SRST_S_UART4 100 +#define SRST_S_UART5 101 +#define SRST_S_UART6 102 +#define SRST_S_UART7 103

+#define SRST_S_UART8 104 +#define SRST_S_UART9 105 +#define SRST_P_SPI0 106 +#define SRST_P_SPI1 107 +#define SRST_P_SPI2 108 +#define SRST_P_SPI3 109 +#define SRST_P_SPI4 110 +#define SRST_SPI0 111 +#define SRST_SPI1 112 +#define SRST_SPI2 113 +#define SRST_SPI3 114 +#define SRST_SPI4 115

+#define SRST_P_WDT0 116 +#define SRST_T_WDT0 117 +#define SRST_P_SYS_GRF 118 +#define SRST_P_PWM1 119 +#define SRST_PWM1 120 +#define SRST_P_PWM2 121 +#define SRST_PWM2 122 +#define SRST_P_PWM3 123 +#define SRST_PWM3 124 +#define SRST_P_BUSTIMER0 125 +#define SRST_P_BUSTIMER1 126 +#define SRST_BUSTIMER0 127

+#define SRST_BUSTIMER1 128 +#define SRST_BUSTIMER2 129 +#define SRST_BUSTIMER3 130 +#define SRST_BUSTIMER4 131 +#define SRST_BUSTIMER5 132 +#define SRST_BUSTIMER6 133 +#define SRST_BUSTIMER7 134 +#define SRST_BUSTIMER8 135 +#define SRST_BUSTIMER9 136 +#define SRST_BUSTIMER10 137 +#define SRST_BUSTIMER11 138 +#define SRST_P_MAILBOX0 139 +#define SRST_P_MAILBOX1 140 +#define SRST_P_MAILBOX2 141 +#define SRST_P_GPIO1 142 +#define SRST_GPIO1 143

+#define SRST_P_GPIO2 144 +#define SRST_GPIO2 145 +#define SRST_P_GPIO3 146 +#define SRST_GPIO3 147 +#define SRST_P_GPIO4 148 +#define SRST_GPIO4 149 +#define SRST_A_DECOM 150 +#define SRST_P_DECOM 151 +#define SRST_D_DECOM 152 +#define SRST_P_TOP 153 +#define SRST_A_GICADB_GIC2CORE_BUS 154 +#define SRST_P_DFT2APB 155 +#define SRST_P_APB2ASB_MST_TOP 156 +#define SRST_P_APB2ASB_MST_CDPHY 157 +#define SRST_P_APB2ASB_MST_BOT_RIGHT 158

+#define SRST_P_APB2ASB_MST_IOC_TOP 159 +#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 +#define SRST_P_APB2ASB_MST_CSIPHY 161 +#define SRST_P_APB2ASB_MST_VCCIO3_5 162 +#define SRST_P_APB2ASB_MST_VCCIO6 163 +#define SRST_P_APB2ASB_MST_EMMCIO 164 +#define SRST_A_SPINLOCK 165 +#define SRST_P_OTPC_NS 166 +#define SRST_OTPC_NS 167 +#define SRST_OTPC_ARB 168

+#define SRST_P_BUSIOC 169 +#define SRST_P_PMUCM0_INTMUX 170 +#define SRST_P_DDRCM0_INTMUX 171

+#define SRST_P_DDR_DFICTL_CH0 172 +#define SRST_P_DDR_MON_CH0 173 +#define SRST_P_DDR_STANDBY_CH0 174 +#define SRST_P_DDR_UPCTL_CH0 175 +#define SRST_TM_DDR_MON_CH0 176 +#define SRST_P_DDR_GRF_CH01 177 +#define SRST_DFI_CH0 178 +#define SRST_SBR_CH0 179 +#define SRST_DDR_UPCTL_CH0 180 +#define SRST_DDR_DFICTL_CH0 181 +#define SRST_DDR_MON_CH0 182 +#define SRST_DDR_STANDBY_CH0 183 +#define SRST_A_DDR_UPCTL_CH0 184 +#define SRST_P_DDR_DFICTL_CH1 185 +#define SRST_P_DDR_MON_CH1 186 +#define SRST_P_DDR_STANDBY_CH1 187

+#define SRST_P_DDR_UPCTL_CH1 188 +#define SRST_TM_DDR_MON_CH1 189 +#define SRST_DFI_CH1 190 +#define SRST_SBR_CH1 191 +#define SRST_DDR_UPCTL_CH1 192 +#define SRST_DDR_DFICTL_CH1 193 +#define SRST_DDR_MON_CH1 194 +#define SRST_DDR_STANDBY_CH1 195 +#define SRST_A_DDR_UPCTL_CH1 196 +#define SRST_A_DDR01_MSCH0 197 +#define SRST_A_DDR01_RS_MSCH0 198 +#define SRST_A_DDR01_FRS_MSCH0 199

+#define SRST_A_DDR01_SCRAMBLE0 200 +#define SRST_A_DDR01_FRS_SCRAMBLE0 201 +#define SRST_A_DDR01_MSCH1 202 +#define SRST_A_DDR01_RS_MSCH1 203 +#define SRST_A_DDR01_FRS_MSCH1 204 +#define SRST_A_DDR01_SCRAMBLE1 205 +#define SRST_A_DDR01_FRS_SCRAMBLE1 206 +#define SRST_P_DDR01_MSCH0 207 +#define SRST_P_DDR01_MSCH1 208

+#define SRST_P_DDR_DFICTL_CH2 209 +#define SRST_P_DDR_MON_CH2 210 +#define SRST_P_DDR_STANDBY_CH2 211 +#define SRST_P_DDR_UPCTL_CH2 212 +#define SRST_TM_DDR_MON_CH2 213 +#define SRST_P_DDR_GRF_CH23 214 +#define SRST_DFI_CH2 215 +#define SRST_SBR_CH2 216 +#define SRST_DDR_UPCTL_CH2 217 +#define SRST_DDR_DFICTL_CH2 218 +#define SRST_DDR_MON_CH2 219 +#define SRST_DDR_STANDBY_CH2 220 +#define SRST_A_DDR_UPCTL_CH2 221 +#define SRST_P_DDR_DFICTL_CH3 222 +#define SRST_P_DDR_MON_CH3 223 +#define SRST_P_DDR_STANDBY_CH3 224

+#define SRST_P_DDR_UPCTL_CH3 225 +#define SRST_TM_DDR_MON_CH3 226 +#define SRST_DFI_CH3 227 +#define SRST_SBR_CH3 228 +#define SRST_DDR_UPCTL_CH3 229 +#define SRST_DDR_DFICTL_CH3 230 +#define SRST_DDR_MON_CH3 231 +#define SRST_DDR_STANDBY_CH3 232 +#define SRST_A_DDR_UPCTL_CH3 233 +#define SRST_A_DDR23_MSCH2 234 +#define SRST_A_DDR23_RS_MSCH2 235 +#define SRST_A_DDR23_FRS_MSCH2 236

+#define SRST_A_DDR23_SCRAMBLE2 237 +#define SRST_A_DDR23_FRS_SCRAMBLE2 238 +#define SRST_A_DDR23_MSCH3 239 +#define SRST_A_DDR23_RS_MSCH3 240 +#define SRST_A_DDR23_FRS_MSCH3 241 +#define SRST_A_DDR23_SCRAMBLE3 242 +#define SRST_A_DDR23_FRS_SCRAMBLE3 243 +#define SRST_P_DDR23_MSCH2 244 +#define SRST_P_DDR23_MSCH3 245

+#define SRST_ISP1 246 +#define SRST_ISP1_VICAP 247 +#define SRST_A_ISP1_BIU 248 +#define SRST_H_ISP1_BIU 249

+#define SRST_A_RKNN1 250 +#define SRST_A_RKNN1_BIU 251 +#define SRST_H_RKNN1 252 +#define SRST_H_RKNN1_BIU 253

+#define SRST_A_RKNN2 254 +#define SRST_A_RKNN2_BIU 255 +#define SRST_H_RKNN2 256 +#define SRST_H_RKNN2_BIU 257

+#define SRST_A_RKNN_DSU0 258 +#define SRST_P_NPUTOP_BIU 259 +#define SRST_P_NPU_TIMER 260 +#define SRST_NPUTIMER0 261 +#define SRST_NPUTIMER1 262 +#define SRST_P_NPU_WDT 263 +#define SRST_T_NPU_WDT 264 +#define SRST_P_NPU_PVTM 265 +#define SRST_P_NPU_GRF 266 +#define SRST_NPU_PVTM 267

+#define SRST_NPU_PVTPLL 268 +#define SRST_H_NPU_CM0_BIU 269 +#define SRST_F_NPU_CM0_CORE 270 +#define SRST_T_NPU_CM0_JTAG 271 +#define SRST_A_RKNN0 272 +#define SRST_A_RKNN0_BIU 273 +#define SRST_H_RKNN0 274 +#define SRST_H_RKNN0_BIU 275

+#define SRST_H_NVM_BIU 276 +#define SRST_A_NVM_BIU 277 +#define SRST_H_EMMC 278 +#define SRST_A_EMMC 279 +#define SRST_C_EMMC 280 +#define SRST_B_EMMC 281 +#define SRST_T_EMMC 282 +#define SRST_S_SFC 283 +#define SRST_H_SFC 284 +#define SRST_H_SFC_XIP 285

+#define SRST_P_GRF 286 +#define SRST_P_DEC_BIU 287 +#define SRST_P_PHP_BIU 288 +#define SRST_A_PCIE_GRIDGE 289 +#define SRST_A_PHP_BIU 290 +#define SRST_A_GMAC0 291 +#define SRST_A_GMAC1 292 +#define SRST_A_PCIE_BIU 293 +#define SRST_PCIE0_POWER_UP 294 +#define SRST_PCIE1_POWER_UP 295 +#define SRST_PCIE2_POWER_UP 296

+#define SRST_PCIE3_POWER_UP 297 +#define SRST_PCIE4_POWER_UP 298 +#define SRST_P_PCIE0 299 +#define SRST_P_PCIE1 300 +#define SRST_P_PCIE2 301 +#define SRST_P_PCIE3 302

+#define SRST_P_PCIE4 303 +#define SRST_A_PHP_GIC_ITS 304 +#define SRST_A_MMU_PCIE 305 +#define SRST_A_MMU_PHP 306 +#define SRST_A_MMU_BIU 307

+#define SRST_A_USB3OTG2 308

+#define SRST_PMALIVE0 309 +#define SRST_PMALIVE1 310 +#define SRST_PMALIVE2 311 +#define SRST_A_SATA0 312 +#define SRST_A_SATA1 313 +#define SRST_A_SATA2 314 +#define SRST_RXOOB0 315 +#define SRST_RXOOB1 316 +#define SRST_RXOOB2 317 +#define SRST_ASIC0 318 +#define SRST_ASIC1 319 +#define SRST_ASIC2 320

+#define SRST_A_RKVDEC_CCU 321 +#define SRST_H_RKVDEC0 322 +#define SRST_A_RKVDEC0 323 +#define SRST_H_RKVDEC0_BIU 324 +#define SRST_A_RKVDEC0_BIU 325 +#define SRST_RKVDEC0_CA 326 +#define SRST_RKVDEC0_HEVC_CA 327 +#define SRST_RKVDEC0_CORE 328

+#define SRST_H_RKVDEC1 329 +#define SRST_A_RKVDEC1 330 +#define SRST_H_RKVDEC1_BIU 331 +#define SRST_A_RKVDEC1_BIU 332 +#define SRST_RKVDEC1_CA 333 +#define SRST_RKVDEC1_HEVC_CA 334 +#define SRST_RKVDEC1_CORE 335

+#define SRST_A_USB_BIU 336 +#define SRST_H_USB_BIU 337 +#define SRST_A_USB3OTG0 338 +#define SRST_A_USB3OTG1 339 +#define SRST_H_HOST0 340 +#define SRST_H_HOST_ARB0 341 +#define SRST_H_HOST1 342 +#define SRST_H_HOST_ARB1 343 +#define SRST_A_USB_GRF 344 +#define SRST_C_USB2P0_HOST0 345

+#define SRST_C_USB2P0_HOST1 346 +#define SRST_HOST_UTMI0 347 +#define SRST_HOST_UTMI1 348

+#define SRST_A_VDPU_BIU 349 +#define SRST_A_VDPU_LOW_BIU 350 +#define SRST_H_VDPU_BIU 351 +#define SRST_A_JPEG_DECODER_BIU 352 +#define SRST_A_VPU 353 +#define SRST_H_VPU 354 +#define SRST_A_JPEG_ENCODER0 355 +#define SRST_H_JPEG_ENCODER0 356 +#define SRST_A_JPEG_ENCODER1 357 +#define SRST_H_JPEG_ENCODER1 358 +#define SRST_A_JPEG_ENCODER2 359 +#define SRST_H_JPEG_ENCODER2 360

+#define SRST_A_JPEG_ENCODER3 361 +#define SRST_H_JPEG_ENCODER3 362 +#define SRST_A_JPEG_DECODER 363 +#define SRST_H_JPEG_DECODER 364 +#define SRST_H_IEP2P0 365 +#define SRST_A_IEP2P0 366 +#define SRST_IEP2P0_CORE 367 +#define SRST_H_RGA2 368 +#define SRST_A_RGA2 369 +#define SRST_RGA2_CORE 370 +#define SRST_H_RGA3_0 371 +#define SRST_A_RGA3_0 372 +#define SRST_RGA3_0_CORE 373

+#define SRST_H_RKVENC0_BIU 374 +#define SRST_A_RKVENC0_BIU 375 +#define SRST_H_RKVENC0 376 +#define SRST_A_RKVENC0 377 +#define SRST_RKVENC0_CORE 378

+#define SRST_H_RKVENC1_BIU 379 +#define SRST_A_RKVENC1_BIU 380 +#define SRST_H_RKVENC1 381 +#define SRST_A_RKVENC1 382 +#define SRST_RKVENC1_CORE 383

+#define SRST_A_VI_BIU 384 +#define SRST_H_VI_BIU 385 +#define SRST_P_VI_BIU 386 +#define SRST_D_VICAP 387 +#define SRST_A_VICAP 388 +#define SRST_H_VICAP 389 +#define SRST_ISP0 390 +#define SRST_ISP0_VICAP 391

+#define SRST_FISHEYE0 392 +#define SRST_FISHEYE1 393 +#define SRST_P_CSI_HOST_0 394 +#define SRST_P_CSI_HOST_1 395 +#define SRST_P_CSI_HOST_2 396 +#define SRST_P_CSI_HOST_3 397 +#define SRST_P_CSI_HOST_4 398 +#define SRST_P_CSI_HOST_5 399

+#define SRST_CSIHOST0_VICAP 400 +#define SRST_CSIHOST1_VICAP 401 +#define SRST_CSIHOST2_VICAP 402 +#define SRST_CSIHOST3_VICAP 403 +#define SRST_CSIHOST4_VICAP 404 +#define SRST_CSIHOST5_VICAP 405 +#define SRST_CIFIN 406

+#define SRST_A_VOP_BIU 407 +#define SRST_A_VOP_LOW_BIU 408 +#define SRST_H_VOP_BIU 409 +#define SRST_P_VOP_BIU 410 +#define SRST_H_VOP 411 +#define SRST_A_VOP 412 +#define SRST_D_VOP0 413 +#define SRST_D_VOP2HDMI_BRIDGE0 414 +#define SRST_D_VOP2HDMI_BRIDGE1 415

+#define SRST_D_VOP1 416 +#define SRST_D_VOP2 417 +#define SRST_D_VOP3 418 +#define SRST_P_VOPGRF 419 +#define SRST_P_DSIHOST0 420 +#define SRST_P_DSIHOST1 421 +#define SRST_DSIHOST0 422 +#define SRST_DSIHOST1 423 +#define SRST_VOP_PMU 424 +#define SRST_P_VOP_CHANNEL_BIU 425

+#define SRST_H_VO0_BIU 426 +#define SRST_H_VO0_S_BIU 427 +#define SRST_P_VO0_BIU 428 +#define SRST_P_VO0_S_BIU 429 +#define SRST_A_HDCP0_BIU 430 +#define SRST_P_VO0GRF 431 +#define SRST_H_HDCP_KEY0 432 +#define SRST_A_HDCP0 433 +#define SRST_H_HDCP0 434 +#define SRST_HDCP0 435

+#define SRST_P_TRNG0 436 +#define SRST_DP0 437 +#define SRST_DP1 438 +#define SRST_H_I2S4_8CH 439 +#define SRST_M_I2S4_8CH_TX 440 +#define SRST_H_I2S8_8CH 441

+#define SRST_M_I2S8_8CH_TX 442 +#define SRST_H_SPDIF2_DP0 443 +#define SRST_M_SPDIF2_DP0 444 +#define SRST_H_SPDIF5_DP1 445 +#define SRST_M_SPDIF5_DP1 446

+#define SRST_A_HDCP1_BIU 447 +#define SRST_A_VO1_BIU 448 +#define SRST_H_VOP1_BIU 449 +#define SRST_H_VOP1_S_BIU 450 +#define SRST_P_VOP1_BIU 451 +#define SRST_P_VO1GRF 452 +#define SRST_P_VO1_S_BIU 453

+#define SRST_H_I2S7_8CH 454 +#define SRST_M_I2S7_8CH_RX 455 +#define SRST_H_HDCP_KEY1 456 +#define SRST_A_HDCP1 457 +#define SRST_H_HDCP1 458 +#define SRST_HDCP1 459 +#define SRST_P_TRNG1 460 +#define SRST_P_HDMITX0 461

+#define SRST_HDMITX0_REF 462 +#define SRST_P_HDMITX1 463 +#define SRST_HDMITX1_REF 464 +#define SRST_A_HDMIRX 465 +#define SRST_P_HDMIRX 466 +#define SRST_HDMIRX_REF 467

+#define SRST_P_EDP0 468 +#define SRST_EDP0_24M 469 +#define SRST_P_EDP1 470 +#define SRST_EDP1_24M 471 +#define SRST_M_I2S5_8CH_TX 472 +#define SRST_H_I2S5_8CH 473 +#define SRST_M_I2S6_8CH_TX 474

+#define SRST_M_I2S6_8CH_RX 475 +#define SRST_H_I2S6_8CH 476 +#define SRST_H_SPDIF3 477 +#define SRST_M_SPDIF3 478 +#define SRST_H_SPDIF4 479 +#define SRST_M_SPDIF4 480 +#define SRST_H_SPDIFRX0 481 +#define SRST_M_SPDIFRX0 482 +#define SRST_H_SPDIFRX1 483 +#define SRST_M_SPDIFRX1 484

+#define SRST_H_SPDIFRX2 485 +#define SRST_M_SPDIFRX2 486 +#define SRST_LINKSYM_HDMITXPHY0 487 +#define SRST_LINKSYM_HDMITXPHY1 488 +#define SRST_VO1_BRIDGE0 489 +#define SRST_VO1_BRIDGE1 490

+#define SRST_H_I2S9_8CH 491 +#define SRST_M_I2S9_8CH_RX 492 +#define SRST_H_I2S10_8CH 493 +#define SRST_M_I2S10_8CH_RX 494 +#define SRST_P_S_HDMIRX 495

+#define SRST_GPU 496 +#define SRST_SYS_GPU 497 +#define SRST_A_S_GPU_BIU 498 +#define SRST_A_M0_GPU_BIU 499 +#define SRST_A_M1_GPU_BIU 500 +#define SRST_A_M2_GPU_BIU 501 +#define SRST_A_M3_GPU_BIU 502 +#define SRST_P_GPU_BIU 503 +#define SRST_P_GPU_PVTM 504

+#define SRST_GPU_PVTM 505 +#define SRST_P_GPU_GRF 506 +#define SRST_GPU_PVTPLL 507 +#define SRST_GPU_JTAG 508

+#define SRST_A_AV1_BIU 509 +#define SRST_A_AV1 510 +#define SRST_P_AV1_BIU 511 +#define SRST_P_AV1 512

+#define SRST_A_DDR_BIU 513 +#define SRST_A_DMA2DDR 514 +#define SRST_A_DDR_SHAREMEM 515 +#define SRST_A_DDR_SHAREMEM_BIU 516 +#define SRST_A_CENTER_S200_BIU 517 +#define SRST_A_CENTER_S400_BIU 518 +#define SRST_H_AHB2APB 519 +#define SRST_H_CENTER_BIU 520 +#define SRST_F_DDR_CM0_CORE 521

+#define SRST_DDR_TIMER0 522 +#define SRST_DDR_TIMER1 523 +#define SRST_T_WDT_DDR 524 +#define SRST_T_DDR_CM0_JTAG 525 +#define SRST_P_CENTER_GRF 526 +#define SRST_P_AHB2APB 527 +#define SRST_P_WDT 528 +#define SRST_P_TIMER 529 +#define SRST_P_DMA2DDR 530 +#define SRST_P_SHAREMEM 531 +#define SRST_P_CENTER_BIU 532 +#define SRST_P_CENTER_CHANNEL_BIU 533

+#define SRST_P_USBDPGRF0 534 +#define SRST_P_USBDPPHY0 535 +#define SRST_P_USBDPGRF1 536 +#define SRST_P_USBDPPHY1 537 +#define SRST_P_HDPTX0 538 +#define SRST_P_HDPTX1 539 +#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 +#define SRST_P_USB2PHY_U3_0_GRF0 541 +#define SRST_P_USB2PHY_U3_1_GRF0 542 +#define SRST_P_USB2PHY_U2_0_GRF0 543 +#define SRST_P_USB2PHY_U2_1_GRF0 544 +#define SRST_HDPTX0_ROPLL 545 +#define SRST_HDPTX0_LCPLL 546 +#define SRST_HDPTX0 547 +#define SRST_HDPTX1_ROPLL 548

+#define SRST_HDPTX1_LCPLL 549 +#define SRST_HDPTX1 550 +#define SRST_HDPTX0_HDMIRXPHY_SET 551 +#define SRST_USBDP_COMBO_PHY0 552 +#define SRST_USBDP_COMBO_PHY0_LCPLL 553 +#define SRST_USBDP_COMBO_PHY0_ROPLL 554 +#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 +#define SRST_USBDP_COMBO_PHY1 556 +#define SRST_USBDP_COMBO_PHY1_LCPLL 557 +#define SRST_USBDP_COMBO_PHY1_ROPLL 558 +#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 +#define SRST_HDMIHDP0 560 +#define SRST_HDMIHDP1 561

+#define SRST_A_VO1USB_TOP_BIU 562 +#define SRST_H_VO1USB_TOP_BIU 563

+#define SRST_H_SDIO_BIU 564 +#define SRST_H_SDIO 565 +#define SRST_SDIO 566

+#define SRST_H_RGA3_BIU 567 +#define SRST_A_RGA3_BIU 568 +#define SRST_H_RGA3_1 569 +#define SRST_A_RGA3_1 570 +#define SRST_RGA3_1_CORE 571

+#define SRST_REF_PIPE_PHY0 572 +#define SRST_REF_PIPE_PHY1 573 +#define SRST_REF_PIPE_PHY2 574

+#define SRST_P_PHPTOP_CRU 575 +#define SRST_P_PCIE2_GRF0 576 +#define SRST_P_PCIE2_GRF1 577 +#define SRST_P_PCIE2_GRF2 578 +#define SRST_P_PCIE2_PHY0 579 +#define SRST_P_PCIE2_PHY1 580 +#define SRST_P_PCIE2_PHY2 581 +#define SRST_P_PCIE3_PHY 582 +#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 +#define SRST_PCIE30_PHY 584

+#define SRST_H_PMU1_BIU 585 +#define SRST_P_PMU1_BIU 586 +#define SRST_H_PMU_CM0_BIU 587 +#define SRST_F_PMU_CM0_CORE 588 +#define SRST_T_PMU1_CM0_JTAG 589

+#define SRST_DDR_FAIL_SAFE 590 +#define SRST_P_CRU_PMU1 591 +#define SRST_P_PMU1_GRF 592 +#define SRST_P_PMU1_IOC 593 +#define SRST_P_PMU1WDT 594 +#define SRST_T_PMU1WDT 595 +#define SRST_P_PMU1TIMER 596 +#define SRST_PMU1TIMER0 597 +#define SRST_PMU1TIMER1 598 +#define SRST_P_PMU1PWM 599 +#define SRST_PMU1PWM 600

+#define SRST_P_I2C0 601 +#define SRST_I2C0 602 +#define SRST_S_UART0 603 +#define SRST_P_UART0 604 +#define SRST_H_I2S1_8CH 605 +#define SRST_M_I2S1_8CH_TX 606 +#define SRST_M_I2S1_8CH_RX 607 +#define SRST_H_PDM0 608 +#define SRST_PDM0 609

+#define SRST_H_VAD 610 +#define SRST_HDPTX0_INIT 611 +#define SRST_HDPTX0_CMN 612 +#define SRST_HDPTX0_LANE 613 +#define SRST_HDPTX1_INIT 614

+#define SRST_HDPTX1_CMN 615 +#define SRST_HDPTX1_LANE 616 +#define SRST_M_MIPI_DCPHY0 617 +#define SRST_S_MIPI_DCPHY0 618 +#define SRST_M_MIPI_DCPHY1 619 +#define SRST_S_MIPI_DCPHY1 620 +#define SRST_OTGPHY_U3_0 621 +#define SRST_OTGPHY_U3_1 622 +#define SRST_OTGPHY_U2_0 623 +#define SRST_OTGPHY_U2_1 624

+#define SRST_P_PMU0GRF 625 +#define SRST_P_PMU0IOC 626 +#define SRST_P_GPIO0 627 +#define SRST_GPIO0 628

+#define SRST_A_SECURE_NS_BIU 629 +#define SRST_H_SECURE_NS_BIU 630 +#define SRST_A_SECURE_S_BIU 631 +#define SRST_H_SECURE_S_BIU 632 +#define SRST_P_SECURE_S_BIU 633 +#define SRST_CRYPTO_CORE 634

+#define SRST_CRYPTO_PKA 635 +#define SRST_CRYPTO_RNG 636 +#define SRST_A_CRYPTO 637 +#define SRST_H_CRYPTO 638 +#define SRST_KEYLADDER_CORE 639 +#define SRST_KEYLADDER_RNG 640 +#define SRST_A_KEYLADDER 641 +#define SRST_H_KEYLADDER 642 +#define SRST_P_OTPC_S 643 +#define SRST_OTPC_S 644 +#define SRST_WDT_S 645

+#define SRST_T_WDT_S 646 +#define SRST_H_BOOTROM 647 +#define SRST_A_DCF 648 +#define SRST_P_DCF 649 +#define SRST_H_BOOTROM_NS 650 +#define SRST_P_KEYLADDER 651 +#define SRST_H_TRNG_S 652

+#define SRST_H_TRNG_NS 653 +#define SRST_D_SDMMC_BUFFER 654 +#define SRST_H_SDMMC 655 +#define SRST_H_SDMMC_BUFFER 656 +#define SRST_SDMMC 657 +#define SRST_P_TRNG_CHK 658 +#define SRST_TRNG_S 659

+#endif

On 2023/1/30 22:57, Jagan Teki wrote:

Add IOC unit header include for rk3588.

Signed-off-by: Steven Liu steven.liu@rock-chips.com Signed-off-by: Joseph Chen chenjh@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

.../include/asm/arch-rockchip/ioc_rk3588.h | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3588.h

diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h new file mode 100644 index 0000000000..5a656f850c --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3588.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • (C) Copyright 2021 Rockchip Electronics Co., Ltd.
• */

+#ifndef _ASM_ARCH_IOC_RK3588_H +#define _ASM_ARCH_IOC_RK3588_H

+struct rk3588_bus_ioc {

• unsigned int reserved0000[3]; /* Address Offset: 0x0000 */
• unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x000C */
• unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0010 */
• unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0014 */
• unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x0018 */
• unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x001C */
• unsigned int gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
• unsigned int gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
• unsigned int gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
• unsigned int gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
• unsigned int gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
• unsigned int gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
• unsigned int gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
• unsigned int gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
• unsigned int gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
• unsigned int gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
• unsigned int gpio2b_iomux_sel_l; /* Address Offset: 0x0048 */
• unsigned int gpio2b_iomux_sel_h; /* Address Offset: 0x004C */
• unsigned int gpio2c_iomux_sel_l; /* Address Offset: 0x0050 */
• unsigned int gpio2c_iomux_sel_h; /* Address Offset: 0x0054 */
• unsigned int gpio2d_iomux_sel_l; /* Address Offset: 0x0058 */
• unsigned int gpio2d_iomux_sel_h; /* Address Offset: 0x005C */
• unsigned int gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
• unsigned int gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
• unsigned int gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
• unsigned int gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
• unsigned int gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
• unsigned int gpio3c_iomux_sel_h; /* Address Offset: 0x0074 */
• unsigned int gpio3d_iomux_sel_l; /* Address Offset: 0x0078 */
• unsigned int gpio3d_iomux_sel_h; /* Address Offset: 0x007C */
• unsigned int gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
• unsigned int gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
• unsigned int gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
• unsigned int gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
• unsigned int gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
• unsigned int gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
• unsigned int gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
• unsigned int gpio4d_iomux_sel_h; /* Address Offset: 0x009C */

+};

+check_member(rk3588_bus_ioc, gpio4d_iomux_sel_h, 0x009C);

+struct rk3588_pmu1_ioc {

• unsigned int gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
• unsigned int gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
• unsigned int gpio0b_iomux_sel_l; /* Address Offset: 0x0008 */
• unsigned int reserved0012; /* Address Offset: 0x000C */
• unsigned int gpio0a_ds_l; /* Address Offset: 0x0010 */
• unsigned int gpio0a_ds_h; /* Address Offset: 0x0014 */
• unsigned int gpio0b_ds_l; /* Address Offset: 0x0018 */
• unsigned int reserved0028; /* Address Offset: 0x001C */
• unsigned int gpio0a_p; /* Address Offset: 0x0020 */
• unsigned int gpio0b_p; /* Address Offset: 0x0024 */
• unsigned int gpio0a_ie; /* Address Offset: 0x0028 */
• unsigned int gpio0b_ie; /* Address Offset: 0x002C */
• unsigned int gpio0a_smt; /* Address Offset: 0x0030 */
• unsigned int gpio0b_smt; /* Address Offset: 0x0034 */
• unsigned int gpio0a_pdis; /* Address Offset: 0x0038 */
• unsigned int gpio0b_pdis; /* Address Offset: 0x003C */
• unsigned int xin_con; /* Address Offset: 0x0040 */

+};

+check_member(rk3588_pmu1_ioc, xin_con, 0x0040);

+struct rk3588_pmu2_ioc {

• unsigned int gpio0b_iomux_sel_h; /* Address Offset: 0x0000 */
• unsigned int gpio0c_iomux_sel_l; /* Address Offset: 0x0004 */
• unsigned int gpio0c_iomux_sel_h; /* Address Offset: 0x0008 */
• unsigned int gpio0d_iomux_sel_l; /* Address Offset: 0x000C */
• unsigned int gpio0d_iomux_sel_h; /* Address Offset: 0x0010 */
• unsigned int gpio0b_ds_h; /* Address Offset: 0x0014 */
• unsigned int gpio0c_ds_l; /* Address Offset: 0x0018 */
• unsigned int gpio0c_ds_h; /* Address Offset: 0x001C */
• unsigned int gpio0d_ds_l; /* Address Offset: 0x0020 */
• unsigned int gpio0d_ds_h; /* Address Offset: 0x0024 */
• unsigned int gpio0b_p; /* Address Offset: 0x0028 */
• unsigned int gpio0c_p; /* Address Offset: 0x002C */
• unsigned int gpio0d_p; /* Address Offset: 0x0030 */
• unsigned int gpio0b_ie; /* Address Offset: 0x0034 */
• unsigned int gpio0c_ie; /* Address Offset: 0x0038 */
• unsigned int gpio0d_ie; /* Address Offset: 0x003C */
• unsigned int gpio0b_smt; /* Address Offset: 0x0040 */
• unsigned int gpio0c_smt; /* Address Offset: 0x0044 */
• unsigned int gpio0d_smt; /* Address Offset: 0x0048 */
• unsigned int gpio0b_pdis; /* Address Offset: 0x004C */
• unsigned int gpio0c_pdis; /* Address Offset: 0x0050 */
• unsigned int gpio0d_pdis; /* Address Offset: 0x0054 */

+};

+check_member(rk3588_pmu2_ioc, gpio0d_pdis, 0x0054);

+#endif