[U-Boot] [PATCH] pci: Fix expansion ROM programming for multi-function devices
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 41d5447..79f27c7 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -185,6 +185,7 @@ void pciauto_setup_device(struct pci_controller *hose, #ifndef CONFIG_PCI_ENUM_ONLY /* Configure the expansion ROM address */ pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type); + header_type &= 0x7f; if (header_type != PCI_HEADER_TYPE_CARDBUS) { rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
Hi Tom,
On Wed, Oct 7, 2015 at 5:13 PM, Bin Meng bmeng.cn@gmail.com wrote:
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 41d5447..79f27c7 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -185,6 +185,7 @@ void pciauto_setup_device(struct pci_controller *hose, #ifndef CONFIG_PCI_ENUM_ONLY /* Configure the expansion ROM address */ pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
header_type &= 0x7f; if (header_type != PCI_HEADER_TYPE_CARDBUS) { rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ? PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;--
I think we should get this patch in v2015.10 as it's a bug fix otherwise multi-function devices won't get ROM address assigned.
Regards, Bin
On 7 October 2015 at 10:13, Bin Meng bmeng.cn@gmail.com wrote:
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+)
Acked-by: Simon Glass sjg@chromium.org
Hi Bin,
On 8 October 2015 at 19:07, Simon Glass sjg@chromium.org wrote:
On 7 October 2015 at 10:13, Bin Meng bmeng.cn@gmail.com wrote:
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+)
Acked-by: Simon Glass sjg@chromium.org
I'm not sure if this fix actually fixes anything for existing boards, but I'll pick it up.
Is there anything else I have missed?
Regards, Simon
Hi Simon,
On Fri, Oct 9, 2015 at 2:10 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 8 October 2015 at 19:07, Simon Glass sjg@chromium.org wrote:
On 7 October 2015 at 10:13, Bin Meng bmeng.cn@gmail.com wrote:
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+)
Acked-by: Simon Glass sjg@chromium.org
I'm not sure if this fix actually fixes anything for existing boards, but I'll pick it up.
Yes, it fixes the Crown Bay board where Topcliff PCI device D0:F0 is a multi-function device and has a ROM.
Is there anything else I have missed?
So far I believe everything for this release is in. Thanks!
Regards, Bin
On 8 October 2015 at 18:30, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Fri, Oct 9, 2015 at 2:10 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 8 October 2015 at 19:07, Simon Glass sjg@chromium.org wrote:
On 7 October 2015 at 10:13, Bin Meng bmeng.cn@gmail.com wrote:
PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/pci/pci_auto.c | 1 + 1 file changed, 1 insertion(+)
Acked-by: Simon Glass sjg@chromium.org
I'm not sure if this fix actually fixes anything for existing boards, but I'll pick it up.
Yes, it fixes the Crown Bay board where Topcliff PCI device D0:F0 is a multi-function device and has a ROM.
Is there anything else I have missed?
So far I believe everything for this release is in. Thanks!
Regards, Bin
Applied to u-boot-x86, and now in mainline.
participants (2)
-
Bin Meng -
Simon Glass