[PATCH 0/4] clk: qcom: add PCIe clocks
Add the PCIe clocks for the SM8550, SM8650 and X1E80100 platforms to enable support for PCIe feature.
Depends on: - https://lore.kernel.org/all/20241118-topic-x1e80100-clk-v1-0-8841e87ad81f@li...
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- Neil Armstrong (4): clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock clk: qcom: sm8550: add support for PCIe clocks clk: qcom: sm8650: add support for PCIe clocks clk: qcom: x1e80100: add support for PCIe clocks
drivers/clk/qcom/clock-qcom.c | 19 ++++++++++++++ drivers/clk/qcom/clock-qcom.h | 2 ++ drivers/clk/qcom/clock-sm8550.c | 36 ++++++++++++++++++++++++++ drivers/clk/qcom/clock-sm8650.c | 36 ++++++++++++++++++++++++++ drivers/clk/qcom/clock-x1e80100.c | 54 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 147 insertions(+) --- base-commit: c7934881aa75d34aea2493322de0a417524ebf4a change-id: 20241125-topic-pcie-clk-8e345d8ace7a
Best regards,
The PCIe PIPE clock requires a special setup function to mux & enable the clock from the PCIe PHY before the PHY has enabled the clock.
Import the clk_phy_mux_enable() from the Linux driver to use the same implementation regarding the PIPE clock.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/clk/qcom/clock-qcom.c | 19 +++++++++++++++++++ drivers/clk/qcom/clock-qcom.h | 2 ++ 2 files changed, 21 insertions(+)
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c index 25ca67e537d112dda236837d3d3984f9b666365e..7687bbe6a23b436e4ddf3b29d1c910062961126d 100644 --- a/drivers/clk/qcom/clock-qcom.c +++ b/drivers/clk/qcom/clock-qcom.c @@ -166,6 +166,25 @@ void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, clk_bcr_update(base + cmd_rcgr); }
+#define PHY_MUX_MASK GENMASK(1, 0) +#define PHY_MUX_PHY_SRC 0 +#define PHY_MUX_REF_SRC 2 + +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + cmd_rcgr); + cfg &= ~(PHY_MUX_MASK); + if (enabled) + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC); + else + cfg |= FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC); + + writel(cfg, base + cmd_rcgr); +} + const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) { if (!f) diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h index 78d9b1d81ece1b3dd96b7bd0ab1a69fa016523b6..ff336dea39cf5cbe35f37f93669285897ba185a4 100644 --- a/drivers/clk/qcom/clock-qcom.h +++ b/drivers/clk/qcom/clock-qcom.h @@ -6,6 +6,7 @@ #define _CLOCK_QCOM_H
#include <asm/io.h> +#include <linux/bitfield.h>
#define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) @@ -102,6 +103,7 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, uint32_t cmd_rcgr, int div, int m, int n, int source, u8 mnd_width); void clk_rcg_set_rate(phys_addr_t base, uint32_t cmd_rcgr, int div, int source); +void clk_phy_mux_enable(phys_addr_t base, uint32_t cmd_rcgr, bool enabled);
static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id) {
Add the PCIe clocks for the SM8550 GCC.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/clk/qcom/clock-sm8550.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c index c0249925cc7eb165faefea35ef29c5ff59faf07f..62b5a409e8e08243ad53a0bc58af1c7754a3d950 100644 --- a/drivers/clk/qcom/clock-sm8550.c +++ b/drivers/clk/qcom/clock-sm8550.c @@ -57,6 +57,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } };
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8550_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -84,6 +94,24 @@ static ulong sm8550_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -182,6 +210,14 @@ static int sm8550_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; }
qcom_gate_clk_en(priv, clk->id);
Add the PCIe clocks for the SM8650 GCC.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/clk/qcom/clock-sm8650.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c index 0ce83e9b24375820016397c3c5491dd9d44edb4b..9baaecb571f6c575c0e7c48d66214c1331b6642f 100644 --- a/drivers/clk/qcom/clock-sm8650.c +++ b/drivers/clk/qcom/clock-sm8650.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } };
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong sm8650_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -81,6 +91,24 @@ static ulong sm8650_set_rate(struct clk *clk, ulong rate) case GCC_USB3_PRIM_PHY_AUX_CLK_SRC: clk_rcg_set_rate(priv->base, 0x39070, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_0_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b074, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_1_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x8d07c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_0_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b058, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_1_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x8d060, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -179,6 +207,14 @@ static int sm8650_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_0_PIPE_CLK: + // GCC_PCIE_0_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b070, true); + break; + case GCC_PCIE_1_PIPE_CLK: + // GCC_PCIE_1_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x8d078, true); + break; }
qcom_gate_clk_en(priv, clk->id);
Add the PCIe clocks for the x1e80100 GCC.
Signed-off-by: Neil Armstrong neil.armstrong@linaro.org --- drivers/clk/qcom/clock-x1e80100.c | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+)
diff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c index 6bcd705f6c8d40dc477c55fe1f594df70e1187ad..bd9c6ed1c8a0b4ca0b5164d849efa5c0755c1e2e 100644 --- a/drivers/clk/qcom/clock-x1e80100.c +++ b/drivers/clk/qcom/clock-x1e80100.c @@ -54,6 +54,16 @@ static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { { } };
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + { } +}; + static ulong x1e80100_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -78,6 +88,24 @@ static ulong x1e80100_set_rate(struct clk *clk, ulong rate) case GCC_USB30_PRIM_MOCK_UTMI_CLK: clk_rcg_set_rate(priv->base, 0x39044, 0, 0); return TCXO_DIV2_RATE; + case GCC_PCIE_4_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x6b080, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_4_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x6b064, freq->pre_div, freq->src); + return freq->freq; + case GCC_PCIE_6A_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, 0x3108c, + freq->pre_div, freq->m, freq->n, freq->src, 16); + return freq->freq; + case GCC_PCIE_6A_PHY_RCHNG_CLK: + freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate); + clk_rcg_set_rate(priv->base, 0x31070, freq->pre_div, freq->src); + return freq->freq; default: return 0; } @@ -86,6 +114,24 @@ static ulong x1e80100_set_rate(struct clk *clk, ulong rate) static const struct gate_clk x1e80100_clks[] = { GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK, 0x52000, BIT(20)), + GATE_CLK(GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK, 0x52028, BIT(22)), + GATE_CLK(GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK, 0x52028, BIT(12)), + GATE_CLK(GCC_CNOC_PCIE_NORTH_SF_AXI_CLK, 0x52008, BIT(6)), + GATE_CLK(GCC_PCIE_4_AUX_CLK, 0x52008, BIT(3)), + GATE_CLK(GCC_PCIE_4_CFG_AHB_CLK, 0x52008, BIT(2)), + GATE_CLK(GCC_PCIE_4_MSTR_AXI_CLK, 0x52008, BIT(1)), + GATE_CLK(GCC_PCIE_4_PHY_RCHNG_CLK, 0x52000, BIT(22)), + GATE_CLK(GCC_PCIE_4_PIPE_CLK, 0x52008, BIT(4)), + GATE_CLK(GCC_PCIE_4_SLV_AXI_CLK, 0x52008, BIT(0)), + GATE_CLK(GCC_PCIE_4_SLV_Q2A_AXI_CLK, 0x52008, BIT(5)), + GATE_CLK(GCC_PCIE_6A_AUX_CLK, 0x52018, BIT(24)), + GATE_CLK(GCC_PCIE_6A_CFG_AHB_CLK, 0x52018, BIT(23)), + GATE_CLK(GCC_PCIE_6A_MSTR_AXI_CLK, 0x52018, BIT(22)), + GATE_CLK(GCC_PCIE_6A_PHY_RCHNG_CLK, 0x52018, BIT(27)), + GATE_CLK(GCC_PCIE_6A_PIPE_CLK, 0x52018, BIT(26)), + GATE_CLK(GCC_PCIE_6A_SLV_AXI_CLK, 0x52018, BIT(21)), + GATE_CLK(GCC_PCIE_6A_SLV_Q2A_AXI_CLK, 0x52018, BIT(20)), GATE_CLK(GCC_QUPV3_WRAP2_CORE_2X_CLK, 0x52010, BIT(3)), GATE_CLK(GCC_QUPV3_WRAP2_CORE_CLK, 0x52010, BIT(0)), GATE_CLK(GCC_QUPV3_WRAP2_S0_CLK, 0x52010, BIT(4)), @@ -118,6 +164,14 @@ static int x1e80100_enable(struct clk *clk) qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK); qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); break; + case GCC_PCIE_4_PIPE_CLK: + // GCC_PCIE_4_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x6b07c, true); + break; + case GCC_PCIE_6A_PIPE_CLK: + // GCC_PCIE_6A_PIPE_CLK_SRC + clk_phy_mux_enable(priv->base, 0x31088, true); + break; }
qcom_gate_clk_en(priv, clk->id);
On Mon, 25 Nov 2024 09:34:25 +0100, Neil Armstrong wrote:
Add the PCIe clocks for the SM8550, SM8650 and X1E80100 platforms to enable support for PCIe feature.
Depends on:
[...]
Applied, thanks!
[1/4] clk: qcom: add clk_phy_mux_enable() for PCIe PIPE clock https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/5b359312... [2/4] clk: qcom: sm8550: add support for PCIe clocks https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/5310a13b... [3/4] clk: qcom: sm8650: add support for PCIe clocks https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/bb77008c... [4/4] clk: qcom: x1e80100: add support for PCIe clocks https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commit/cd86b564...
Best regards,
participants (2)
-
Caleb Connolly -
Neil Armstrong