[U-Boot-Users] AMCC440SPe & PCI Express

Patil, Pankaj P.

22 Dec 2006 22 Dec '06

8:49 p.m.

Hi, I have been using u-boot-1.1.5 on my custom 440SPe based board. I am able to establish a link on PCIE0. However, I am having trouble accessing outbound Memory on PCIE0. My memory map seetings for Outbound PCIE memory are the default U-boot Settings. I was curious if anybody's tried accessing PCIE Outbound memory with the default settings. I seem to get a bus error when I try to access that region.

Thanks Pankaj

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Wolfgang Denk

22 Dec 22 Dec

10:49 p.m.

Dear Pankaj,

in message 9B832BEB407A774AA0520CCFC23221970B47D178@CXOEXC11.AMERICAS.CPQCORP.NET you wrote:

...

I have been using u-boot-1.1.5 on my custom 440SPe based board. I am able to establish a link on PCIE0. However, I am having trouble accessing outbound Memory on PCIE0. My memory map seetings for Outbound PCIE memory are the default U-boot Settings. I was curious if anybody's tried accessing PCIE Outbound memory with the default settings. I seem to get a bus error when I try to access that region.

I confirm that there is some problem with PCIe on these systems. We're working on this right now. Please stay tuned.

Best regards,

Wolfgang Denk

-- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Q: How do you play religious roulette? A: You stand around in a circle and blaspheme and see who gets struck by lightning first.

Patil, Pankaj P.

11:21 p.m.

Thanks for the update, I noticed that changing PECFG_POM0LAL to 0xB0000000 instead of 0x00000000 in 440spe_pcie.c seems to get rid of the bus error. I don't have a YUCCA board so i cannot verify it but worth the try. Another strange thing i noticed was that i have a multifunction device on PCIE0. U-boot, however would only detect function0. pci display 1.1.0 succeeds but pci display 1.1.1 fails to detect. This might be my device problem. Its a tachyon. Just curious if anybody had trouble detecting multifunction device on PCIE??

Thanks again Pankaj

-----Original Message----- From: wd@denx.de [mailto:wd@denx.de] Sent: Friday, December 22, 2006 2:50 PM To: Patil, Pankaj P. Cc: u-boot-users@lists.sourceforge.net Subject: Re: [U-Boot-Users] AMCC440SPe & PCI Express

Dear Pankaj,

in message 9B832BEB407A774AA0520CCFC23221970B47D178@CXOEXC11.AMERICAS.CPQCORP.NET you wrote:

...

I have been using u-boot-1.1.5 on my custom 440SPe based board. I am able to establish a link on PCIE0. However, I am having trouble accessing outbound Memory on PCIE0. My memory map seetings for Outbound PCIE memory are the default U-boot Settings. I was curious if anybody's tried accessing PCIE Outbound memory with the default settings. I seem to get a bus error when I try to access that region.

I confirm that there is some problem with PCIe on these systems. We're working on this right now. Please stay tuned.

Best regards,

Wolfgang Denk

kans

26 Nov 26 Nov

12:02 p.m.

Hello,

I am using u-boot 1.3.0-rc3 for my custom 440SPE board and configured PCIE1 as endpoint.

After configuring the KATMAI board as RC(running Linux), I am able to establish the link between KATMAI and my board.

I have few doubts here.

1. CFG space (OUTBOUND BAR4) is mentioned as 512MB minimum. But the CFGMSK register says it can start from 128 Bytes. Using lesser values from 512MB creates Machine Check exception.

2. I have set PIMEN as 0x1. ie. Enable access for BAR0(I have set PIM01SAL/H for 1MB). The Katmai board views BAR0(1MB memory), BAR2 as IO, and BAR4 as Memory. It doesnt assign any addresses to BAR2 and BAR4. Also I have not enabled any IO space in my custom board.

Please let me know for 1. Why there are Machine check exceptions using lesser values in CFG(less than 512MB)? 2. Why other BARs are getting enabled?

-- Kans

wd wrote:

...

Dear Pankaj,

in message 9B832BEB407A774AA0520CCFC23221970B47D178@CXOEXC11.AMERICAS.CPQCORP.NET you wrote:

...
I have been using u-boot-1.1.5 on my custom 440SPe based board. I am able to establish a link on PCIE0. However, I am having trouble accessing outbound Memory on PCIE0. My memory map seetings for Outbound PCIE memory are the default U-boot Settings. I was curious if anybody's tried accessing PCIE Outbound memory with the default settings. I seem to get a bus error when I try to access that region.

I confirm that there is some problem with PCIe on these systems. We're working on this right now. Please stay tuned.

Best regards,

Wolfgang Denk

-- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Q: How do you play religious roulette? A: You stand around in a circle and blaspheme and see who gets struck by lightning first.

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-- View this message in context: http://www.nabble.com/AMCC440SPe---PCI-Express-tf2872188.html#a13947577 Sent from the Uboot - Users mailing list archive at Nabble.com.

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kans
Patil, Pankaj P.
Wolfgang Denk