[U-Boot] [PATCH] arm: sunxi: initial support for NanoPi Neo2
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 170 +++++++++++++++++++++++++++++++++ board/sunxi/MAINTAINERS | 5 + configs/nanopi_neo2_defconfig | 19 ++++ 4 files changed, 195 insertions(+) create mode 100644 arch/arm/dts/sun50i-h5-nanopi-neo2.dts create mode 100644 configs/nanopi_neo2_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4d656ce4cc..fa2f3932cb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -311,6 +311,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ dtb-$(CONFIG_MACH_SUN8I_V3S) += \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ + sun50i-h5-nanopi-neo2.dtb \ sun50i-h5-orangepi-pc2.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts new file mode 100644 index 0000000000..4d1028b378 --- /dev/null +++ b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2016 ARM Ltd. + * Copyright (c) 2016 James Pettigrew james@innovum.com.au + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "FriendlyARM NanoPi NEO2"; + compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5"; + + cpus { + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x40000000 0x20000000>; + }; + + aliases { + serial0 = &uart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_npi>, <&leds_r_npi>; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_npi: led-pins { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_npi: led-pins { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1c8817375d..0c645bc7ca 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -243,6 +243,11 @@ M: Jelle van der Waa jelle@vdwaa.nl S: Maintained F: configs/nanopi_neo_defconfig
+NANOPI-NEO2 BOARD +M: Patrick Wildt patrick@blueri.se +S: Maintained +F: configs/nanopi_neo2_defconfig + NANOPI-NEO-AIR BOARD M: Jelle van der Waa jelle@vdwaa.nl S: Maintained diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig new file mode 100644 index 0000000000..e0e50e33ba --- /dev/null +++ b/configs/nanopi_neo2_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ZQ=3881977 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +CONFIG_SPL=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y
On Tue, May 09, 2017 at 02:43:41PM +0200, Patrick Wildt wrote:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 170 +++++++++++++++++++++++++++++++++
Is this dts file coming from the Linux Kernel? If so, please cite the githash / tag that it's from, thanks.
Hej Patrick,
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
Using this dtb here via UEFI distro boot, my openSUSE kernel image that booted okay on orangepi_pc2 fails to find the MMC devices on Neo2, although it obviously succeeded to boot from SD in U-Boot and GRUB...
Also, if I "reset" from the downstream or patched mainline U-Boot prompt, SPL gets stuck:
=> reset resetting ... INFO: PSCI Affinity Map: INFO: AffInst: Level 0, MPID 0x0, State ON INFO: AffInst: Level 0, MPID 0x1, State OFF INFO: AffInst: Level 0, MPID 0x2, State OFF INFO: AffInst: Level 0, MPID 0x3, State OFF
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1
If instead I unpower it (by plugging Micro USB), it boots okay:
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):1.0~20160809T000419~45ab97e NOTICE: BL3-1: Built : 01:01:56, Nov 15 2016 NOTICE: Configuring AXP PMIC ERROR: set run-time address: 0x0 ERROR: PMIC: unknown PMIC type number 0x0 ERROR: Could not connect to AXP PMIC. INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9
U-Boot 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24 +0200) Allwinner Technology
CPU: Allwinner H5 (SUN50I) Model: FriendlyARM NanoPi NEO2 DRAM: 512 MiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: No ethernet found. starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0
Andre, is this reset problem maybe an ATF issue?
Regards, Andreas
Hi,
On 24/05/17 12:50, Andreas Färber wrote:
Hej Patrick,
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
I think we have a similar diversion between Linux and U-Boot .dts here, given that the U-Boot support was merged earlier. Updating the DTs for H5 and the board(s) was on my plan, but it's a bit more involved since it affects the H3 .dts as well (H3 and H5 use a shared stub .dtsi now). Also the H5 .dtsi just got into Linux (4.12-rc1), so it hasn't been in an officially released kernel yet.
Using this dtb here via UEFI distro boot, my openSUSE kernel image that booted okay on orangepi_pc2 fails to find the MMC devices on Neo2, although it obviously succeeded to boot from SD in U-Boot and GRUB...
Also, if I "reset" from the downstream or patched mainline U-Boot prompt, SPL gets stuck:
=> reset resetting ... INFO: PSCI Affinity Map: INFO: AffInst: Level 0, MPID 0x0, State ON INFO: AffInst: Level 0, MPID 0x1, State OFF INFO: AffInst: Level 0, MPID 0x2, State OFF INFO: AffInst: Level 0, MPID 0x3, State OFF
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1
If instead I unpower it (by plugging Micro USB), it boots okay:
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):1.0~20160809T000419~45ab97e NOTICE: BL3-1: Built : 01:01:56, Nov 15 2016
Your ATF build is quite old, it doesn't really support the H5. Please you the latest HEAD[1], it should print the SoC name at the beginning, and then won't try to configure an AXP on the H5. Please let me know if that fixes your problem.
Cheers, Andre.
[1] https://github.com/apritzel/arm-trusted-firmware/commits/allwinner
NOTICE: Configuring AXP PMIC ERROR: set run-time address: 0x0 ERROR: PMIC: unknown PMIC type number 0x0 ERROR: Could not connect to AXP PMIC. INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9
U-Boot 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24 +0200) Allwinner Technology
CPU: Allwinner H5 (SUN50I) Model: FriendlyARM NanoPi NEO2 DRAM: 512 MiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: No ethernet found. starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0
Andre, is this reset problem maybe an ATF issue?
Regards, Andreas
On Wed, May 24, 2017 at 01:44:26PM +0100, Andre Przywara wrote:
Hi,
On 24/05/17 12:50, Andreas Färber wrote:
Hej Patrick,
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
I think we have a similar diversion between Linux and U-Boot .dts here, given that the U-Boot support was merged earlier. Updating the DTs for H5 and the board(s) was on my plan, but it's a bit more involved since it affects the H3 .dts as well (H3 and H5 use a shared stub .dtsi now). Also the H5 .dtsi just got into Linux (4.12-rc1), so it hasn't been in an officially released kernel yet.
I'm fine with re-syncing to v4.12-rc2, btw.
Am 24.05.2017 um 14:44 schrieb Andre Przywara:
On 24/05/17 12:50, Andreas Färber wrote:
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
I think we have a similar diversion between Linux and U-Boot .dts here, given that the U-Boot support was merged earlier. Updating the DTs for H5 and the board(s) was on my plan, but it's a bit more involved since it affects the H3 .dts as well (H3 and H5 use a shared stub .dtsi now). Also the H5 .dtsi just got into Linux (4.12-rc1), so it hasn't been in an officially released kernel yet.
Using this dtb here via UEFI distro boot, my openSUSE kernel image that booted okay on orangepi_pc2 fails to find the MMC devices on Neo2, although it obviously succeeded to boot from SD in U-Boot and GRUB...
Hmm, this may be related to my initrd being too big for 512 MB RAM:
[ 0.298393] Unpacking initramfs... [ 3.619116] Initramfs unpacking failed: write error [ 3.671293] Freeing initrd memory: 72888K
Also, if I "reset" from the downstream or patched mainline U-Boot prompt, SPL gets stuck:
=> reset resetting ... INFO: PSCI Affinity Map: INFO: AffInst: Level 0, MPID 0x0, State ON INFO: AffInst: Level 0, MPID 0x1, State OFF INFO: AffInst: Level 0, MPID 0x2, State OFF INFO: AffInst: Level 0, MPID 0x3, State OFF
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1
If instead I unpower it (by plugging Micro USB), it boots okay:
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):1.0~20160809T000419~45ab97e NOTICE: BL3-1: Built : 01:01:56, Nov 15 2016
Your ATF build is quite old, it doesn't really support the H5. Please you the latest HEAD[1], it should print the SoC name at the beginning, and then won't try to configure an AXP on the H5.
Switching from allwinner-scpi to allwinner branch I now see H5:
NOTICE: BL3-1: Running on H5 (1718) in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):1.0~20170220T001539�aa75c8da NOTICE: BL3-1: Built : 12:54:47, May 24 2017 INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9
but the reset issue persists. It appears to be a works-sometimes type problem - could it depend on SRAM contents or something? (1 out of ~5)
Cheers, Andreas
On Wed, May 24, 2017 at 01:44:26PM +0100, Andre Przywara wrote:
Hi,
On 24/05/17 12:50, Andreas Färber wrote:
Hej Patrick,
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
I mailed Tom in private asking what to explictly state since 90% was from u-boot and 10% from Linux-Sunxi (not mainline). I didn't get a reply, so there was no further mail from me.
So should I pull it now from v4.12-rc2?
Patrick
I think we have a similar diversion between Linux and U-Boot .dts here, given that the U-Boot support was merged earlier. Updating the DTs for H5 and the board(s) was on my plan, but it's a bit more involved since it affects the H3 .dts as well (H3 and H5 use a shared stub .dtsi now). Also the H5 .dtsi just got into Linux (4.12-rc1), so it hasn't been in an officially released kernel yet.
Using this dtb here via UEFI distro boot, my openSUSE kernel image that booted okay on orangepi_pc2 fails to find the MMC devices on Neo2, although it obviously succeeded to boot from SD in U-Boot and GRUB...
Also, if I "reset" from the downstream or patched mainline U-Boot prompt, SPL gets stuck:
=> reset resetting ... INFO: PSCI Affinity Map: INFO: AffInst: Level 0, MPID 0x0, State ON INFO: AffInst: Level 0, MPID 0x1, State OFF INFO: AffInst: Level 0, MPID 0x2, State OFF INFO: AffInst: Level 0, MPID 0x3, State OFF
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1
If instead I unpower it (by plugging Micro USB), it boots okay:
U-Boot SPL 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24) DRAM: 512 MiB Trying to boot from MMC1 NOTICE: BL3-1: Running in SRAM A2 (@0x44000) NOTICE: Configuring SPC Controller NOTICE: BL3-1: v1.0(debug):1.0~20160809T000419~45ab97e NOTICE: BL3-1: Built : 01:01:56, Nov 15 2016
Your ATF build is quite old, it doesn't really support the H5. Please you the latest HEAD[1], it should print the SoC name at the beginning, and then won't try to configure an AXP on the H5. Please let me know if that fixes your problem.
Cheers, Andre.
[1] https://github.com/apritzel/arm-trusted-firmware/commits/allwinner
NOTICE: Configuring AXP PMIC ERROR: set run-time address: 0x0 ERROR: PMIC: unknown PMIC type number 0x0 ERROR: Could not connect to AXP PMIC. INFO: BL3-1: Initializing runtime services INFO: BL3-1: Preparing for EL3 exit to normal world INFO: BL3-1: Next image address: 0x4a000000, SPSR: 0x3c9
U-Boot 2017.05-00660-g4bffee2792 (May 24 2017 - 00:43:24 +0200) Allwinner Technology
CPU: Allwinner H5 (SUN50I) Model: FriendlyARM NanoPi NEO2 DRAM: 512 MiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: No ethernet found. starting USB... USB0: USB EHCI 1.00 USB1: USB OHCI 1.0 scanning bus 0 for devices... 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found Hit any key to stop autoboot: 0
Andre, is this reset problem maybe an ATF issue?
Regards, Andreas
On Thu, Jun 01, 2017 at 02:45:03PM +0200, Patrick Wildt wrote:
On Wed, May 24, 2017 at 01:44:26PM +0100, Andre Przywara wrote:
Hi,
On 24/05/17 12:50, Andreas Färber wrote:
Hej Patrick,
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
I mailed Tom in private asking what to explictly state since 90% was from u-boot and 10% from Linux-Sunxi (not mainline). I didn't get a reply, so there was no further mail from me.
So should I pull it now from v4.12-rc2?
Sorry. I'm trying to help make sure dts changes are on their way to the mainline Linux kernel, so that we don't get out of sync. So, does v4.12-rc2 have everything you need? Thanks!
On Thu, Jun 01, 2017 at 08:57:26AM -0400, Tom Rini wrote:
On Thu, Jun 01, 2017 at 02:45:03PM +0200, Patrick Wildt wrote:
On Wed, May 24, 2017 at 01:44:26PM +0100, Andre Przywara wrote:
Hi,
On 24/05/17 12:50, Andreas Färber wrote:
Hej Patrick,
Am 09.05.2017 um 14:43 schrieb Patrick Wildt:
The NanoPi Neo2 is basically the same as the NanoPi Neo, but that they replaced the SoC with the 64-bit Allwinner H5 SoC. Add a (64-bit only) defconfig defining the required options to build the U-Boot proper.
Create a new .dts file for it by including the (32-bit) H3 SoC .dtsi and changing the differing components accordingly, like it's been done for the OrangePi PC 2.
Signed-off-by: Patrick Wildt patrick@blueri.se
I've tested this patch on top of yesterday's master branch (4c78028737c3185f49f5691183aeac3478b5f699 "mksunxi_fit_atf.sh: Allow for this to complete when bl31.bin is missing").
Considering Tom's unanswered question, is there any diff to the upstream kernel .dts? Expected would be to just copy the Linux .dts file here and to state which tree and commit/tag it was taken from.
I mailed Tom in private asking what to explictly state since 90% was from u-boot and 10% from Linux-Sunxi (not mainline). I didn't get a reply, so there was no further mail from me.
So should I pull it now from v4.12-rc2?
Sorry. I'm trying to help make sure dts changes are on their way to the mainline Linux kernel, so that we don't get out of sync. So, does v4.12-rc2 have everything you need? Thanks!
-- Tom
There's even v4.12-rc3 now. It does not have the NanoPi Neo2, but I guess as a start one should do a sync for the rest of the stuff.
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Copied from 5ed02dbb497422bf225783f46e6eadd237d23d6b, v4.12-rc3.
Opinions?
Patrick
diff --git a/arch/arm/dts/sun50i-a64-bananapi-m64.dts b/arch/arm/dts/sun50i-a64-bananapi-m64.dts index 02db114..6872135 100644 --- a/arch/arm/dts/sun50i-a64-bananapi-m64.dts +++ b/arch/arm/dts/sun50i-a64-bananapi-m64.dts @@ -1,6 +1,5 @@ /* * Copyright (c) 2016 ARM Ltd. - * Copyright (C) 2017 Jagan Teki jteki@openedev.com * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index de60f78..dfecc17 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -1,17 +1,17 @@ /* - * Copyright (c) 2016 ARM Ltd. + * Copyright (C) 2016 ARM Ltd. * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * - * a) This library is free software; you can redistribute it and/or + * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * - * This library is distributed in the hope that it will be useful, + * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. @@ -41,107 +41,148 @@ */
/dts-v1/; +#include "sun50i-h5.dtsi"
-#include "sun8i-h3.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { - model = "OrangePi PC 2"; - compatible = "xunlong,orangepi-pc-2", "allwinner,sun50i-h5"; - - cpus { - cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; - enable-method = "psci"; - }; - cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; - enable-method = "psci"; - }; - cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; - enable-method = "psci"; - }; - cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; + model = "Xunlong Orange Pi PC 2"; + compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5"; + + reg_vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; };
- timer { - compatible = "arm,armv8-timer"; + aliases { + serial0 = &uart0; };
chosen { stdout-path = "serial0:115200n8"; };
- memory { - reg = <0x40000000 0x40000000>; - }; + leds { + compatible = "gpio-leds";
- aliases { - serial0 = &uart0; - ethernet0 = &emac; + pwr { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status { + label = "orangepi:red:status"; + gpios = <&pio 0 20 GPIO_ACTIVE_HIGH>; + }; };
- soc { - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + r-gpio-keys { + compatible = "gpio-keys"; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; }; }; + + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; + }; +}; + +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; };
-&gic { - compatible = "arm,gic-400"; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; };
&mmc0 { - compatible = "allwinner,sun50i-h5-mmc", - "allwinner,sun50i-a64-mmc", - "allwinner,sun5i-a13-mmc"; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 5 6 0>; - cd-inverted; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; };
-&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; +&ohci0 { status = "okay"; };
-&usbphy { +&ohci1 { status = "okay"; };
-&ohci1 { +&ohci2 { status = "okay"; };
-&ehci1 { +&ohci3 { status = "okay"; };
-&emac { +&uart0 { pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-mode = "rgmii"; - phy = <&phy1>; + pinctrl-0 = <&uart0_pins_a>; status = "okay"; +};
- phy1: ethernet-phy@1 { - reg = <1>; - }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + /* USB Type-A ports' VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; + status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi new file mode 100644 index 0000000..4d314a2 --- /dev/null +++ b/arch/arm/dts/sun50i-h5.dtsi @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 ARM Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-h3-h5.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; + +&ccu { + compatible = "allwinner,sun50i-h5-ccu"; +}; + +&mmc0 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc"; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; +}; + +&mmc1 { + compatible = "allwinner,sun50i-h5-mmc", + "allwinner,sun50i-a64-mmc"; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; +}; + +&mmc2 { + compatible = "allwinner,sun50i-h5-emmc", + "allwinner,sun50i-a64-emmc"; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; +}; + +&pio { + compatible = "allwinner,sun50i-h5-pinctrl"; +}; diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index 20d489c..9e8b082 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -49,7 +49,6 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "Xunlong Orange Pi Zero"; @@ -92,22 +91,16 @@ wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; }; };
-&ehci1 { +&ehci0 { status = "okay"; };
-&emac { - phy = <&phy1>; - phy-mode = "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; +&ehci1 { status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; };
&mmc0 { @@ -138,6 +131,14 @@ }; };
+&mmc1_pins_a { + bias-pull-up; +}; + +&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; }; @@ -148,7 +149,29 @@ status = "okay"; };
+&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usbphy { - /* USB VBUS is always on */ + /* + * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only + * power up the board; when it's used as OTG port, this VBUS is + * always off even if the board is powered via GPIO pins. + */ status = "okay"; + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ }; diff --git a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts index f3b1d5f..52acbe1 100644 --- a/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/dts/sun8i-h3-bananapi-m2-plus.dts @@ -46,7 +46,6 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "Banana Pi BPI-M2-Plus"; @@ -156,24 +155,18 @@
&r_pio { pwr_led_bpi_m2p: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL10"; + function = "gpio_out"; };
sw_r_bpi_m2p: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL3"; + function = "gpio_in"; };
wifi_en_bpi_m2p: wifi_en_pin { - allwinner,pins = "PL7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL7"; + function = "gpio_out"; }; };
@@ -185,7 +178,7 @@
&uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; status = "okay"; };
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts index 3ba081c..03ff6f8 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -45,7 +45,6 @@ #include "sunxi-common-regulators.dtsi"
#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "FriendlyARM NanoPi NEO Air"; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/dts/sun8i-h3-nanopi-neo.dts index 5113059..8d2cc6e 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo.dts @@ -46,14 +46,3 @@ model = "FriendlyARM NanoPi NEO"; compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; }; - -&emac { - phy = <&phy1>; - phy-mode = "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; - status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index caa1a69..5b6d145 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -46,7 +46,6 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "Xunlong Orange Pi 2"; @@ -109,17 +108,6 @@ status = "okay"; };
-&emac { - phy = <&phy1>; - phy-mode = "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; - status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - &ir { pinctrl-names = "default"; pinctrl-0 = <&ir_pins_a>; @@ -156,33 +144,25 @@
&pio { leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA15"; + function = "gpio_out"; }; };
&r_pio { leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL10"; + function = "gpio_out"; };
sw_r_opc: key_pins@0 { - allwinner,pins = "PL3", "PL4"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL3", "PL4"; + function = "gpio_in"; };
wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { - allwinner,pins = "PL7"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL7"; + function = "gpio_out"; }; };
@@ -197,8 +177,26 @@ status = "okay"; };
+&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usb1_vbus_pin_a { - allwinner,pins = "PG13"; + pins = "PG13"; };
&usbphy { diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts index 1550fee..9b47a0d 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-lite.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts @@ -46,7 +46,6 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "Xunlong Orange Pi Lite"; @@ -143,26 +142,20 @@
&pio { leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA15"; + function = "gpio_out"; }; };
&r_pio { leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL10"; + function = "gpio_out"; };
sw_r_opc: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL3"; + function = "gpio_in"; }; };
diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts index 8df5c74..5fea430 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -46,7 +46,6 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "Xunlong Orange Pi One"; @@ -90,19 +89,12 @@ }; };
-&ehci1 { +&ehci0 { status = "okay"; };
-&emac { - phy = <&phy1>; - phy-mode = "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; +&ehci1 { status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; };
&mmc0 { @@ -115,42 +107,70 @@ status = "okay"; };
+&ohci0 { + status = "okay"; +}; + &ohci1 { status = "okay"; };
&pio { leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA15"; + function = "gpio_out"; }; };
&r_pio { leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL10"; + function = "gpio_out"; };
sw_r_opc: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL3"; + function = "gpio_in"; }; };
+®_usb0_vbus { + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; };
+&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { - /* USB VBUS is always on */ + /* USB Type-A port's VBUS is always on */ + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + usb0_vbus-supply = <®_usb0_vbus>; status = "okay"; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts index 851fd2c..8b93f5c 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts @@ -82,7 +82,7 @@
&mmc2_8bit_pins { /* Increase drive strength for DDR modes */ - allwinner,drive = <SUN4I_PINCTRL_40_MA>; + drive-strength = <40>; /* eMMC is missing pull-ups */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index b8340f7..f148111 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -46,7 +46,6 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h>
/ { model = "Xunlong Orange Pi PC"; @@ -90,6 +89,14 @@ }; };
+&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "okay"; +}; + &ehci1 { status = "okay"; }; @@ -132,26 +139,20 @@
&pio { leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PA15"; + function = "gpio_out"; }; };
&r_pio { leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL10"; + function = "gpio_out"; };
sw_r_opc: key_pins@0 { - allwinner,pins = "PL3"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL3"; + function = "gpio_in"; }; };
@@ -161,18 +162,25 @@ status = "okay"; };
-&usbphy { - /* USB VBUS is always on */ - status = "okay"; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; };
-&emac { - phy = <&phy1>; - phy-mode = "mii"; - allwinner,use-internal-phy; - allwinner,leds-active-low; +&usbphy { + /* USB VBUS is always on */ status = "okay"; - phy1: ethernet-phy@1 { - reg = <1>; - }; }; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts index e7079b2..8c40ab7 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -47,18 +47,6 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
- reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_orangepi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; - reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -76,15 +64,6 @@ status = "okay"; };
-&emac { - /* The Orange Pi Plus uses an external phy */ - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-mode = "rgmii"; - /delete-property/allwinner,use-internal-phy; -}; - &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; @@ -97,24 +76,15 @@
&mmc2_8bit_pins { /* Increase drive strength for DDR modes */ - allwinner,drive = <SUN4I_PINCTRL_40_MA>; + drive-strength = <40>; /* eMMC is missing pull-ups */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; };
&pio { - gmac_power_pin_orangepi: gmac_power_pin@0 { - allwinner,pins = "PD6"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - usb3_vbus_pin_a: usb3_vbus_pin@0 { - allwinner,pins = "PG11"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG11"; + function = "gpio_out"; }; };
diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts index f97b040..5851a47 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus2e.dts @@ -50,34 +50,4 @@ / { model = "Xunlong Orange Pi Plus 2E"; compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; - - reg_gmac_3v3: gmac-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&gmac_power_pin_orangepi>; - regulator-name = "gmac-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - startup-delay-us = <100000>; - enable-active-high; - gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&emac { - /* The Orange Pi Plus 2E uses an external gbit phy */ - pinctrl-names = "default"; - pinctrl-0 = <&emac_rgmii_pins>; - phy-supply = <®_gmac_3v3>; - phy-mode = "rgmii"; - /delete-property/allwinner,use-internal-phy; -}; - -&pio { - gmac_power_pin_orangepi: gmac_power_pin@0 { - allwinner,pins = "PD6"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; }; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index afa6079..b36f9f4 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -40,20 +40,9 @@ * OTHER DEALINGS IN THE SOFTWARE. */
-#include "skeleton.dtsi" - -#include <dt-bindings/clock/sun8i-h3-ccu.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> -#include <dt-bindings/reset/sun8i-h3-ccu.h> +#include "sunxi-h3-h5.dtsi"
/ { - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &emac; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -90,445 +79,48 @@ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; +};
- clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - apb0: apb0_clk { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&osc24M>; - clock-output-names = "apb0"; - }; - - apb0_gates: clk@01f01428 { - compatible = "allwinner,sun8i-h3-apb0-gates-clk", - "allwinner,sun4i-a10-gates-clk"; - reg = <0x01f01428 0x4>; - #clock-cells = <1>; - clocks = <&apb0>; - clock-indices = <0>, <1>; - clock-output-names = "apb0_pio", "apb0_ir"; - }; - - ir_clk: ir_clk@01f01454 { - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01f01454 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "ir"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon: syscon@01c00000 { - compatible = "allwinner,sun8i-h3-syscon","syscon"; - reg = <0x01c00000 0x34>; - }; - - dma: dma-controller@01c02000 { - compatible = "allwinner,sun8i-h3-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-h3-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>, - <0x01c1b800 0x4>, - <0x01c1c800 0x4>, - <0x01c1d800 0x4>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1", - "pmu2", - "pmu3"; - clocks = <&ccu CLK_USB_PHY0>, - <&ccu CLK_USB_PHY1>, - <&ccu CLK_USB_PHY2>, - <&ccu CLK_USB_PHY3>; - clock-names = "usb0_phy", - "usb1_phy", - "usb2_phy", - "usb3_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>, - <&ccu RST_USB_PHY2>, - <&ccu RST_USB_PHY3>; - reset-names = "usb0_reset", - "usb1_reset", - "usb2_reset", - "usb3_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci1: usb@01c1b000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1b000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@01c1b400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1b400 0x100>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci2: usb@01c1c000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1c000 0x100>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@01c1c400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1c400 0x100>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, - <&ccu CLK_USB_OHCI2>; - resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; - phys = <&usbphy 2>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci3: usb@01c1d000 { - compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; - reg = <0x01c1d000 0x100>; - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci3: usb@01c1d400 { - compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; - reg = <0x01c1d400 0x100>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, - <&ccu CLK_USB_OHCI3>; - resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; - phys = <&usbphy 3>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@01c20000 { - compatible = "allwinner,sun8i-h3-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - pio: pinctrl@01c20800 { - compatible = "allwinner,sun8i-h3-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - emac_rgmii_pins: emac0@0 { - allwinner,pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD7", - "PD8", "PD9", "PD10", - "PD12", "PD13", "PD15", - "PD16", "PD17"; - allwinner,function = "emac"; - allwinner,drive = <SUN4I_PINCTRL_40_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc0_cd_pin: mmc0_cd_pin@0 { - allwinner,pins = "PF6"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; - }; - - mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart0_pins_a: uart0@0 { - allwinner,pins = "PA4", "PA5"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - - uart1_pins_a: uart1@0 { - allwinner,pins = "PG6", "PG7", "PG8", "PG9"; - allwinner,function = "uart1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - }; - - timer@01c20c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - wdt0: watchdog@01c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - }; - - uart0: serial@01c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart1: serial@01c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart2: serial@01c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - uart3: serial@01c28c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28c00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-h3-emac"; - reg = <0x01c30000 0x104>, <0x01c00030 0x4>; - reg-names = "emac", "syscon"; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - resets = <&ccu RST_BUS_EMAC>, <&ccu RST_BUS_EPHY>; - reset-names = "ahb", "ephy"; - clocks = <&ccu CLK_BUS_EMAC>, <&ccu CLK_BUS_EPHY>; - clock-names = "ahb", "ephy"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - rtc: rtc@01f00000 { - compatible = "allwinner,sun6i-a31-rtc"; - reg = <0x01f00000 0x54>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - }; +&ccu { + compatible = "allwinner,sun8i-h3-ccu"; +};
- apb0_reset: reset@01f014b0 { - reg = <0x01f014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; +&mmc0 { + compatible = "allwinner,sun7i-a20-mmc"; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; +};
- ir: ir@01f02000 { - compatible = "allwinner,sun5i-a13-ir"; - clocks = <&apb0_gates 1>, <&ir_clk>; - clock-names = "apb", "ir"; - resets = <&apb0_reset 1>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x01f02000 0x40>; - status = "disabled"; - }; +&mmc1 { + compatible = "allwinner,sun7i-a20-mmc"; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; +};
- r_pio: pinctrl@01f02c00 { - compatible = "allwinner,sun8i-h3-r-pinctrl"; - reg = <0x01f02c00 0x400>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>; - resets = <&apb0_reset 0>; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; +&mmc2 { + compatible = "allwinner,sun7i-a20-mmc"; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; + clock-names = "ahb", + "mmc", + "output", + "sample"; +};
- ir_pins_a: ir@0 { - allwinner,pins = "PL11"; - allwinner,function = "s_cir_rx"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; - }; - }; +&pio { + compatible = "allwinner,sun8i-h3-pinctrl"; }; diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi new file mode 100644 index 0000000..1aeeacb --- /dev/null +++ b/arch/arm/dts/sunxi-h3-h5.dtsi @@ -0,0 +1,601 @@ +/* + * Copyright (C) 2015 Jens Kuske jenskuske@gmail.com + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/clock/sun8i-h3-ccu.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/sun8i-h3-ccu.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + iosc: internal-osc-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <16000000>; + clock-accuracy = <300000000>; + clock-output-names = "iosc"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-h3-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg = <0x01c0f000 0x1000>; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@01c10000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg = <0x01c10000 0x1000>; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@01c11000 { + /* compatible and clocks are in per SoC .dtsi file */ + reg = <0x01c11000 0x1000>; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-h3-musb"; + reg = <0x01c19000 0x400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>, + <&ccu CLK_USB_PHY2>, + <&ccu CLK_USB_PHY3>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>, + <&ccu RST_USB_PHY2>, + <&ccu RST_USB_PHY3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@01c1a000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1a000 0x100>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ohci0: usb@01c1a400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1a400 0x100>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + status = "disabled"; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; + resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@01c1c000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; + resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, + <&ccu CLK_USB_OHCI2>; + resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@01c1d000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1d000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; + resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@01c1d400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1d400 0x100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, + <&ccu CLK_USB_OHCI3>; + resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ccu: clock@01c20000 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&osc32k>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pio: pinctrl@01c20800 { + /* compatible is in per SoC .dtsi file */ + reg = <0x01c20800 0x400>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + i2c0_pins: i2c0 { + pins = "PA11", "PA12"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + pins = "PA18", "PA19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2 { + pins = "PE12", "PE13"; + function = "i2c2"; + }; + + mmc0_pins_a: mmc0@0 { + pins = "PF0", "PF1", "PF2", "PF3", + "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc0_cd_pin: mmc0_cd_pin@0 { + pins = "PF6"; + function = "gpio_in"; + bias-pull-up; + }; + + mmc1_pins_a: mmc1@0 { + pins = "PG0", "PG1", "PG2", "PG3", + "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; + }; + + mmc2_8bit_pins: mmc2_8bit { + pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; + }; + + spdif_tx_pins_a: spdif@0 { + pins = "PA17"; + function = "spdif"; + }; + + spi0_pins: spi0 { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + + spi1_pins: spi1 { + pins = "PA15", "PA16", "PA14", "PA13"; + function = "spi1"; + }; + + uart0_pins_a: uart0@0 { + pins = "PA4", "PA5"; + function = "uart0"; + }; + + uart1_pins: uart1 { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_rts_cts_pins: uart1_rts_cts { + pins = "PG8", "PG9"; + function = "uart1"; + }; + + uart2_pins: uart2 { + pins = "PA0", "PA1"; + function = "uart2"; + }; + + uart3_pins: uart3 { + pins = "PA13", "PA14"; + function = "uart3"; + }; + }; + + timer@01c20c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x01c20c00 0xa0>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc24M>; + }; + + spi0: spi@01c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@01c69000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c69000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 24>, <&dma 24>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + wdt0: watchdog@01c20ca0 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + + spdif: spdif@01c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; + resets = <&ccu RST_BUS_SPDIF>; + clock-names = "apb", "spdif"; + dmas = <&dma 2>; + dma-names = "tx"; + status = "disabled"; + }; + + pwm: pwm@01c21400 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x8>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-h3-codec"; + reg = <0x01c22c00 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; + status = "disabled"; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@01c28400 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28400 0x400>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart2: serial@01c28800 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28800 0x400>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@01c28c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28c00 0x400>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,gic-400"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x2000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; + + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; + clocks = <&osc24M>, <&osc32k>, <&iosc>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + codec_analog: codec-analog@01f015c0 { + compatible = "allwinner,sun8i-h3-codec-analog"; + reg = <0x01f015c0 0x4>; + }; + + ir: ir@01f02000 { + compatible = "allwinner,sun5i-a13-ir"; + clocks = <&r_ccu 4>, <&r_ccu 11>; + clock-names = "apb", "ir"; + resets = <&r_ccu 0>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x01f02000 0x40>; + status = "disabled"; + }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun8i-h3-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + ir_pins_a: ir@0 { + pins = "PL11"; + function = "s_cir_rx"; + }; + }; + }; +}; diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig new file mode 100644 index 0000000..74c7d74 --- /dev/null +++ b/configs/nanopi_neo2_defconfig @@ -0,0 +1,19 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_MACH_SUN50I_H5=y +CONFIG_SPL=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ZQ=3881977 +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-neo2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_CONSOLE_MUX=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SUN8I_EMAC=y +CONFIG_USB_EHCI_HCD=y +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index a3dbe28..2526f72 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -465,14 +465,20 @@ static int parse_phy_pins(struct udevice *dev) }
drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,drive", 4); - pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,pull", 0); + "drive-strength", 40) / 10; + + if (fdt_getprop(gd->fdt_blob, offset, "bias-pull-down", NULL)) + pull = 2; + else if (fdt_getprop(gd->fdt_blob, offset, "bias-pull-up", NULL)) + pull = 1; + else + pull = 0; + for (i = 0; ; i++) { int pin;
pin_name = fdt_stringlist_get(gd->fdt_blob, offset, - "allwinner,pins", i, NULL); + "pins", i, NULL); if (!pin_name) break; if (pin_name[0] != 'P') @@ -488,7 +494,7 @@ static int parse_phy_pins(struct udevice *dev) }
if (!i) { - printf("WARNING: emac: cannot find allwinner,pins property\n"); + printf("WARNING: emac: cannot find pins property\n"); return -2; }
Am 01.06.2017 um 16:04 schrieb Patrick Wildt:
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Andre or someone had already sent a series sync'ing a64 and pine64. Can you keep h5/h3 separate or rebase onto that series please to not cause merge conflicts? Thanks for your work on this.
Regards, Andreas
P.S. Recently a couple mails to you bounced.
On Thu, Jun 1, 2017 at 8:23 PM, Andreas Färber afaerber@suse.de wrote:
Am 01.06.2017 um 16:04 schrieb Patrick Wildt:
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Andre or someone had already sent a series sync'ing a64 and pine64. Can you keep h5/h3 separate or rebase onto that series please to not cause merge conflicts? Thanks for your work on this.
Yeah, it's been on u-boot-sunxi/master
thanks!
On Thu, Jun 01, 2017 at 08:27:02PM +0530, Jagan Teki wrote:
On Thu, Jun 1, 2017 at 8:23 PM, Andreas Färber afaerber@suse.de wrote:
Am 01.06.2017 um 16:04 schrieb Patrick Wildt:
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Andre or someone had already sent a series sync'ing a64 and pine64. Can you keep h5/h3 separate or rebase onto that series please to not cause merge conflicts? Thanks for your work on this.
Yeah, it's been on u-boot-sunxi/master
thanks!
Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.
I had already rebased it against u-boot-sunxi/master, so the attached diff should be fine. Should I send it as a separate [PATCH] mail?
Thanks, Patrick
On Thu, Jun 01, 2017 at 05:56:09PM +0200, Patrick Wildt wrote:
On Thu, Jun 01, 2017 at 08:27:02PM +0530, Jagan Teki wrote:
On Thu, Jun 1, 2017 at 8:23 PM, Andreas Färber afaerber@suse.de wrote:
Am 01.06.2017 um 16:04 schrieb Patrick Wildt:
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Andre or someone had already sent a series sync'ing a64 and pine64. Can you keep h5/h3 separate or rebase onto that series please to not cause merge conflicts? Thanks for your work on this.
Yeah, it's been on u-boot-sunxi/master
thanks!
I had already rebased it against u-boot-sunxi/master, so the attached diff should be fine. Should I send it as a separate [PATCH] mail?
To be clear, you were re-syncing those boards with only changes that will be going upstream to the Linux kernel at some point, right? Or are already there? And nothing U-Boot specific?
On Thu, Jun 01, 2017 at 11:57:48AM -0400, Tom Rini wrote:
On Thu, Jun 01, 2017 at 05:56:09PM +0200, Patrick Wildt wrote:
On Thu, Jun 01, 2017 at 08:27:02PM +0530, Jagan Teki wrote:
On Thu, Jun 1, 2017 at 8:23 PM, Andreas Färber afaerber@suse.de wrote:
Am 01.06.2017 um 16:04 schrieb Patrick Wildt:
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Andre or someone had already sent a series sync'ing a64 and pine64. Can you keep h5/h3 separate or rebase onto that series please to not cause merge conflicts? Thanks for your work on this.
Yeah, it's been on u-boot-sunxi/master
thanks!
I had already rebased it against u-boot-sunxi/master, so the attached diff should be fine. Should I send it as a separate [PATCH] mail?
To be clear, you were re-syncing those boards with only changes that will be going upstream to the Linux kernel at some point, right? Or are already there? And nothing U-Boot specific?
More the other way around. I replaced the u-boot ones with the files from linux, so there should be nothing u-boot specific anymore if there was at all. Is that approach incorrect?
On Thu, Jun 01, 2017 at 05:59:35PM +0200, Patrick Wildt wrote:
On Thu, Jun 01, 2017 at 11:57:48AM -0400, Tom Rini wrote:
On Thu, Jun 01, 2017 at 05:56:09PM +0200, Patrick Wildt wrote:
On Thu, Jun 01, 2017 at 08:27:02PM +0530, Jagan Teki wrote:
On Thu, Jun 1, 2017 at 8:23 PM, Andreas Färber afaerber@suse.de wrote:
Am 01.06.2017 um 16:04 schrieb Patrick Wildt:
What's holding us up from using the Linux device trees without any changes? This diff I attach inline copies all a64, h3 and h5 related files from v4.12-rc3 (so, mainline) and modifies the emac driver to use the new pinmux attributes.
Andre or someone had already sent a series sync'ing a64 and pine64. Can you keep h5/h3 separate or rebase onto that series please to not cause merge conflicts? Thanks for your work on this.
Yeah, it's been on u-boot-sunxi/master
thanks!
I had already rebased it against u-boot-sunxi/master, so the attached diff should be fine. Should I send it as a separate [PATCH] mail?
To be clear, you were re-syncing those boards with only changes that will be going upstream to the Linux kernel at some point, right? Or are already there? And nothing U-Boot specific?
More the other way around. I replaced the u-boot ones with the files from linux, so there should be nothing u-boot specific anymore if there was at all. Is that approach incorrect?
No, that's what I wanted to hear, thanks!
participants (5)
-
Andre Przywara -
Andreas Färber -
Jagan Teki -
Patrick Wildt -
Tom Rini