[U-Boot] [PATCH 1/8] powerpc/srio: Correct the register defined errors in the struct ccsr_rio_t
Many registers were not defined in the struct ccsr_rio_t in the file arch/powerpc/include/asm/immap_85xx.h. For example it lacks registers from offset 0xc0600 to 0xd0160. Accordingly, some register's offset need to be modified in the struct.
In addition, add the register's offset in the comments.
Signed-off-by: Liu Gang Gang.Liu@freescale.com --- arch/powerpc/include/asm/immap_85xx.h | 338 ++++++++++++++++++++------------- 1 files changed, 202 insertions(+), 136 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 92da130..623be17 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1355,168 +1355,234 @@ typedef struct ccsr_cpm {
/* RapidIO Registers */ typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ + u32 didcar; /* 0xc0000 - Device Identity CAR */ + u32 dicar; /* 0xc0004 - Device Information CAR */ + u32 aidcar; /* 0xc0008 - Assembly Identity CAR */ + u32 aicar; /* 0xc000c - Assembly Information CAR */ + u32 pefcar; /* 0xc0010 - Processing Element Features CAR */ + u32 spicar; /* 0xc0014 - Switch Port Information CAR */ + u32 socar; /* 0xc0018 - Source Operations CAR */ + u32 docar; /* 0xc001c - Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* 0xc0040 - Mailbox CSR */ + u32 pwdcsr; /* 0xc0044 - Port-Write and Doorbell CSR */ u8 res2[4]; - u32 pellccsr; /* Processing Element Logic Layer CCSR */ + u32 pellccsr; /* 0xc004c - Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* 0xc005c - Local Configuration Space BACSR */ + u32 bdidcsr; /* 0xc0060 - Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ + u32 hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock CSR */ + u32 ctcsr; /* 0xc006c - Component Tag CSR */ u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ + u32 pmbh0csr; /* 0xc0100 - Port Maintenance Block Header 0 CSR */ u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ + u32 pltoccsr; /* 0xc0120 - Port Link Time-out CCSR */ + u32 prtoccsr; /* 0xc0124 - Port Response Time-out CCSR */ u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ + u32 pgccsr; /* 0xc013c - Port General CSR */ + u32 plmreqcsr; /* 0xc0140 - Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* 0xc0144 - Port Link Maintenance Response CSR */ + u32 plascsr; /* 0xc0148 - Port Local Ackid Status CSR */ u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ + u32 pescsr; /* 0xc0158 - Port Error and Status CSR */ + u32 pccsr; /* 0xc015c - Port Control CSR */ + u8 res9[1184]; + u32 erbh; /* 0xc0600 - Error Reporting Block Header Register */ + u8 res10[4]; + u32 ltledcsr; /* 0xc0608 - Logical/Transport layer error DCSR */ + u32 ltleecsr; /* 0xc060c - Logical/Transport layer error ECSR */ + u8 res11[4]; + u32 ltlaccsr; /* 0xc0614 - Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* 0xc0618 - Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* 0xc061c - Logical/Transport layer control CCSR */ + u8 res12[32]; + u32 edcsr; /* 0xc0640 - Port 0 error detect CSR */ + u32 erecsr; /* 0xc0644 - Port 0 error rate enable CSR */ + u32 ecacsr; /* 0xc0648 - Port 0 error capture attributes CSR */ + u32 pcseccsr0; /* 0xc064c - Port 0 packet/control symbol ECCSR 0 */ + u32 peccsr1; /* 0xc0650 - Port 0 error capture CSR 1 */ + u32 peccsr2; /* 0xc0654 - Port 0 error capture CSR 2 */ + u32 peccsr3; /* 0xc0658 - Port 0 error capture CSR 3 */ u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ + u32 ercsr; /* 0xc0668 - Port 0 error rate CSR */ + u32 ertcsr; /* 0xc066C - Port 0 error rate threshold CSR */ + u8 res14[63892]; + u32 llcr; /* 0xd0004 - Logical Layer Configuration Register */ + u8 res15[8]; + u32 epwisr; /* 0xd0010 - Error / Port-Write Interrupt SR */ u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ + u32 lretcr; /* 0xd0020 - Logical Retry Error Threshold CR */ + u8 res17[92]; + u32 pretcr; /* 0xd0080 - Physical Retry Erorr Threshold CR */ + u8 res18[124]; + u32 adidcsr; /* 0xd0100 - Port 0 Alt. Device ID CSR */ + u8 res19[28]; + u32 ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All CR */ + u8 res20[12]; + u32 iecsr; /* 0xd0130 - Port 0 Implementation Error CSR */ + u8 res21[12]; + u32 pcr; /* 0xd0140 - Port 0 Phsyical Configuration Register */ + u8 res22[20]; + u32 slcsr; /* 0xd0158 - Port 0 Serial Link CSR */ u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ + u32 sleir; /* 0xd0160 - Port 0 Serial Link Error Injection */ + u8 res24[2716]; + u32 rowtar0; /* 0xd0c00 - RapidIO Outbound Window TAR 0 */ + u32 rowtear0; /* 0xd0c04 - RapidIO Outbound Window TEAR 0 */ + u8 res25[8]; + u32 rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + u8 res26[12]; + u32 rowtar1; /* 0xd0c20 - RapidIO Outbound Window TAR 1 */ + u32 rowtear1; /* 0xd0c24 - RapidIO Outbound Window TEAR 1 */ + u32 rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base AR 1 */ u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ + u32 rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + u32 rows1r1; /* 0xd0c34 - RapidIO Outbound Window S 1 R1 */ + u32 rows2r1; /* 0xd0c38 - RapidIO Outbound Window S 2 R 1 */ + u32 rows3r1; /* 0xd0c3c - RapidIO Outbound Window S 3 R 1 */ + u32 rowtar2; /* 0xd0c40 - RapidIO Outbound Window TAR 2 */ + u32 rowtear2; /* 0xd0c44 - RapidIO Outbound Window TEAR 2 */ + u32 rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base AR 2 */ + u8 res28[4]; + u32 rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + u32 rows1r2; /* 0xd0c54 - RapidIO Outbound Window S 1 R 2 */ + u32 rows2r2; /* 0xd0c58 - RapidIO Outbound Window S 2 R 2 */ + u32 rows3r2; /* 0xd0c5c - RapidIO Outbound Window S 3 R 2 */ + u32 rowtar3; /* 0xd0c60 - RapidIO Outbound Window TAR 3 */ + u32 rowtear3; /* 0xd0c64 - RapidIO Outbound Window TEAR 3 */ + u32 rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base AR 3 */ u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ + u32 rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + u32 rows1r3; /* 0xd0c74 - RapidIO Outbound Window S 1 R 3 */ + u32 rows2r3; /* 0xd0c78 - RapidIO Outbound Window S 2 R 3 */ + u32 rows3r3; /* 0xd0c7c - RapidIO Outbound Window S 3 R 3 */ + u32 rowtar4; /* 0xd0c80 - RapidIO Outbound Window TAR 4 */ + u32 rowtear4; /* 0xd0c84 - RapidIO Outbound Window TEAR 4 */ + u32 rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base AR 4 */ u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ + u32 rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + u32 rows1r4; /* 0xd0c94 - RapidIO Outbound Window S 1 R 4 */ + u32 rows2r4; /* 0xd0c98 - RapidIO Outbound Window S 2 R 4 */ + u32 rows3r4; /* 0xd0c9c - RapidIO Outbound Window S 3 R 4 */ + u32 rowtar5; /* 0xd0ca0 - RapidIO Outbound Window TAR 5 */ + u32 rowtear5; /* 0xd0ca4 - RapidIO Outbound Window TEAR 5 */ + u32 rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base AR 5 */ + u8 res31[4]; + u32 rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + u32 rows1r5; /* 0xd0cb4 - RapidIO Outbound Window S 1 R 5 */ + u32 rows2r5; /* 0xd0cb8 - RapidIO Outbound Window S 2 R 5 */ + u32 rows3r5; /* 0xd0cbc - RapidIO Outbound Window S 3 R 5 */ + u32 rowtar6; /* 0xd0cc0 - RapidIO Outbound Window TAR 6 */ + u32 rowtear6; /* 0xd0cc4 - RapidIO Outbound Window TEAR 6 */ + u32 rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base AR 6 */ u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ + u32 rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + u32 rows1r6; /* 0xd0cd4 - RapidIO Outbound Window S 1 R 6 */ + u32 rows2r6; /* 0xd0cd8 - RapidIO Outbound Window S 2 R 6 */ + u32 rows3r6; /* 0xd0cdc - RapidIO Outbound Window S 3 R 6 */ + u32 rowtar7; /* 0xd0ce0 - RapidIO Outbound Window TAR 7 */ + u32 rowtear7; /* 0xd0ce4 - RapidIO Outbound Window TEAR 7 */ + u32 rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base AR 7 */ u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ + u32 rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + u32 rows1r7; /* 0xd0cf4 - RapidIO Outbound Window S 1 R 7 */ + u32 rows2r7; /* 0xd0cf8 - RapidIO Outbound Window S 2 R 7 */ + u32 rows3r7; /* 0xd0cfc - RapidIO Outbound Window S 3 R 7 */ + u32 rowtar8; /* 0xd0d00 - RapidIO Outbound Window TAR 8 */ + u32 rowtear8; /* 0xd0d04 - RapidIO Outbound Window TEAR 8 */ + u32 rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base AR 8 */ + u8 res34[4]; + u32 rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + u32 rows1r8; /* 0xd0d14 - RapidIO Outbound Window S 1 R 8 */ + u32 rows2r8; /* 0xd0d18 - RapidIO Outbound Window S 2 R 8 */ + u32 rows3r8; /* 0xd0d1c - RapidIO Outbound Window S 3 R 8 */ + u8 res35[64]; + u32 riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation AR 4 */ + u8 res59[4]; + u32 riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base AR 4 */ u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ + u32 riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + u8 res37[12]; + u32 riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation AR 3 */ u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ + u32 riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base AR 3 */ u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ + u32 riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ + u32 riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation AR 2 */ u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ + u32 riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base AR 2 */ u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ + u32 riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ + u32 riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation AR 1 */ u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ + u32 riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base AR 1 */ u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ + u32 riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; + u32 riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation AR 0 */ + u8 res47[12]; + u32 riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + u8 res48[12]; + u32 pnfedr; /* 0xd0e00 - Port Notification/Fatal Error DR */ + u32 pnfedir; /* 0xd0e04 - Port Notification/Fatal Error DR */ + u32 pnfeier; /* 0xd0e08 - Port Notification/Fatal Error IER */ + u32 pecr; /* 0xd0e0c - Port Error Control Register */ + u32 pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol 0 */ + u32 pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + u32 pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + u8 res49[4]; + u32 predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + u8 res50[4]; + u32 pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + u32 prtr; /* 0xd0e2c - Port Retry Threshold Register */ + u8 res51[8656]; + u32 omr; /* 0xd3000 - Outbound Mode Register */ + u32 osr; /* 0xd3004 - Outbound Status Register */ + u32 eodqdpar; /* 0xd3008 - Extended Outbound DQ DPAR */ + u32 odqdpar; /* 0xd300c - Outbound Descriptor Queue DPAR */ + u32 eosar; /* 0xd3010 - Extended Outbound Unit Source AR */ + u32 osar; /* 0xd3014 - Outbound Unit Source AR */ + u32 odpr; /* 0xd3018 - Outbound Destination Port Register */ + u32 odatr; /* 0xd301c - Outbound Destination Attributes Register */ + u32 odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + u32 eodqepar; /* 0xd3024 - Extended Outbound DQ EPAR */ + u32 odqepar; /* 0xd3028 - Outbound Descriptor Queue EPAR */ + u32 oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + u32 omgr; /* 0xd3030 - Outbound Multicast Group Register */ + u32 omlr; /* 0xd3034 - Outbound Multicast List Register */ + u8 res52[40]; + u32 imr; /* 0xd3060 - Outbound Mode Register */ + u32 isr; /* 0xd3064 - Inbound Status Register */ + u32 eidqdpar; /* 0xd3068 - Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* 0xd306c - Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* 0xd3070 - Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* 0xd3074 - Inbound Frame Queue EPAR */ + u32 imirir; /* 0xd3078 - Inbound Maximum Interrutp RIR */ + u8 res53[900]; + u32 oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + u32 oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + u8 res54[16]; + u32 oddpr; /* 0xd3418 - Outbound Doorbell Destination Port */ + u32 oddatr; /* 0xd341C - Outbound Doorbell Destination AR */ + u8 res55[12]; + u32 oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold CR */ + u8 res56[48]; + u32 idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + u32 idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + u32 iedqdpar; /* 0xd3468 - Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* 0xd346c - Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* 0xd3470 - Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* 0xd3474 - Inbound Doorbell Queue EPAR */ + u32 idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt RIR */ + u8 res57[100]; + u32 pwmr; /* 0xd34e0 - Port-Write Mode Register */ + u32 pwsr; /* 0xd34e4 - Port-Write Status Register */ + u32 epwqbar; /* 0xd34e8 - Extended Port-Write Queue BAR */ + u32 pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + u8 res58[51984]; } ccsr_rio_t;
/* Quick Engine Block Pin Muxing Registers */
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors:
./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2
There will be a confict if defined CONFIG_ENV_IS_NOWHERE and CONFIG_ENV_IS_IN_FLASH.
Signed-off-by: Liu Gang Gang.Liu@freescale.com --- include/configs/corenet_ds.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95..e38f69d 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -96,6 +96,8 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang Gang.Liu@freescale.com wrote:
There will be a confict if defined CONFIG_ENV_IS_NOWHERE and CONFIG_ENV_IS_IN_FLASH.
This doesn't make any sense. How can the environment be nowhere *and* also in flash, at the same time?
Hi, Timur, Thanks for your comments. Please find my replies inline.
Best Regards,
Liu Gang
-----Original Message----- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 12:48 AM To: Liu Gang-B34182 Cc: u-boot@lists.denx.de; Alexandre.Bounine@idt.com; Gala Kumar-B11780; Zang Roy-R61911 Subject: Re: [U-Boot] [PATCH 2/8] powerpc/env: Correct the compilation errors when defined CONFIG_ENV_IS_NOWHERE
On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang Gang.Liu@freescale.com wrote:
There will be a confict if defined CONFIG_ENV_IS_NOWHERE and CONFIG_ENV_IS_IN_FLASH.
This doesn't make any sense. How can the environment be nowhere *and* also in flash, at the same time?
[Liu Gang-B34182] The environment cannot be nowhere *and* also in flash at the same time! So we should not re-defined CONFIG_ENV_IS_IN_FLASH if the CONFIG_ENV_IS_NOWHERE has been defined. But the code will still define CONFIG_ENV_IS_IN_FLASH if the CONFIG_ENV_IS_NOWHERE has been defined. This will cause a compilation error described in this patch.
-- Timur Tabi Linux kernel developer at Freescale
Dear Liu Gang,
In message 1326195751-20729-2-git-send-email-Gang.Liu@freescale.com you wrote:
When defined CONFIG_ENV_IS_NOWHERE, there will be some compilation errors:
./common/env_nowhere.o: In function `env_relocate_spec': ./common/env_nowhere.c:38: multiple definition of `env_relocate_spec' ./common/env_flash.o: ./common/env_flash.c:326: first defined here ./common/env_nowhere.o: In function `env_get_char_spec': ./common/env_nowhere.c:42: multiple definition of `env_get_char_spec' ./common/env_flash.o:./common/env_flash.c:78: first defined here ./common/env_nowhere.o: In function `env_init': ./common/env_nowhere.c:51: multiple definition of `env_init' ./common/env_flash.o:./common/env_flash.c:237: first defined here make[1]: *** [./common/libcommon.o] Error 1 make[1]: Leaving directory `./common' make: *** [./common/libcommon.o] Error 2
The Subject: says this affects "powerpc/env". Is this really correct? Are _all_ Power architecture systems affected? I don't think so.
If your comment was correct, how comes you change configs/corenet_ds.h only?
Best regards,
Wolfgang Denk
This document describes the implementation of the boot from SRIO, includes the introduction of envionment, an example based on P4080DS platform, an example of the slave's RCW, and the description about how to use this feature.
Signed-off-by: Liu Gang Gang.Liu@freescale.com --- doc/README.srio-boot-mpc85xx | 103 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 103 insertions(+), 0 deletions(-) create mode 100644 doc/README.srio-boot-mpc85xx
diff --git a/doc/README.srio-boot-mpc85xx b/doc/README.srio-boot-mpc85xx new file mode 100644 index 0000000..1c6b0c9 --- /dev/null +++ b/doc/README.srio-boot-mpc85xx @@ -0,0 +1,103 @@ +------------------------------ +SRIO Boot on MPC85xx Platforms +------------------------------ + +For some PowerPC processors with SRIO interface, boot location can be configured +to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot +image, ucode and ENV. All the images can be fetched from another processor's +memory space by SRIO link connected between them. + +This document describes the processes based on an example implemented on P4080DS +platforms and a RCW example with boot from SRIO configuration. + +Environment of the SRIO boot: + a) Master and slave can be SOCs in one board or SOCs in separate boards. + b) They are connected with SRIO links, whether 1x or 4x, and directly or + through switch system. + c) Only Master has NorFlash for booting, and all the Master's and Slave's + U-Boot images, UCodes will be stored in this flash. + d) Slave has its own EEPROM for RCW and PBI. + e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot + location to SRIO, and holdoff all the cores if needed. + + ---------- ----------- ----------- + | | | | | | + | | | | | | + | NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM] + | | | |<===========>| | + | | | | | | + ---------- ----------- ----------- + +The example based on P4080DS platform: + Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO + ports 0 will be connected directly and will be used for the boot from SRIO. + + 1. Slave's RCW example for boot from SRIO port 0 and core 0 not in holdoff. + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 + 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 + 00000020: f400 0000 0100 0000 0000 0000 0000 0000 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 + 00000040: 0000 0000 0000 0000 0813 8040 698b 93fe + + 2. Slave's RCW example for boot from SRIO port 0 and all cores in holdoff. + 00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000 + 00000010: 1818 1818 0000 8888 7440 4000 0000 2000 + 00000020: f440 0000 0100 0000 0000 0000 0000 0000 + 00000030: 0000 0000 0083 0000 0000 0000 0000 0000 + 00000040: 0000 0000 0000 0000 0813 8040 063c 778f + + 3. Sequence in Step by Step. + a) Update RCW for slave with boot from SRIO port 0 configuration. + b) Program slave's U-Boot image, UCode, and ENV parameters into master's + NorFlash. + c) Start up master and it will boot up normally from its NorFlash. + Then, it will finish necessary configurations for slave's boot from + SRIO port 0. + d) Master will set inbound SRIO windows covered slave's U-Boot image stored + in master's NorFlash. + e) Master will set an inbound SRIO window covered slave's UCode stored in + master's NorFlash. + f) Master will set an inbound SRIO window covered slave's ENV stored in + master's NorFlash. + g) If need to release slave's core, master will set outbound SRIO windows + in order to configure slave's registers for the core's releasing. + h) If all cores of slave in holdoff, slave should be powered on before all + the above master's steps, and wait to be released by master. If not all + cores in holdoff, that means core 0 will start up normally, slave should + be powered on after all the above master's steps. In the startup phase + of the slave from SRIO, it will finish some necessary configurations. + i) Slave will set a specific TLB entry for the boot process. + j) Slave will set a LAW entry with the TargetID SRIO port 0 for the boot. + k) Slave will set a specific TLB entry in order to fetch UCode and ENV + from master. + l) Slave will set a LAW entry with the TargetID SRIO port 0 for UCode and ENV. + +How to use this feature: + To use this feature, you need to focus three points. + + 1. Slave's RCW with SRIO boot configurations, and all cores in holdoff + configurations if needed. + Please refer to the examples given above. + + 2. U-Boot image's compilation. + For master, U-Boot image should be generated specifically by + + make xxxx_SRIOBOOT_MASTER_config. + + For example, master U-Boot image used on P4080DS should be compiled with + + make P4080DS_SRIOBOOT_MASTER_config. + + For slave, U-Boot image should be generated specifically by + + make xxxx_SRIOBOOT_SLAVE_config. + + For example, slave U-Boot image used on P4080DS should be compiled with + + make P4080DS_SRIOBOOT_SLAVE_config. + + 3. Necessary modifications based on a specific environment. + For a specific environment, the SRIO port for boot, the addresses of the + slave's U-Boot image, UCode, ENV stored in master's NorFlash, and any other + configurations can be modified in the file: + include/configs/corenet_ds.h.
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements:
master: 1. Nor flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master Nor flash. 3. Normally boot from local Nor flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot.
For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's Nor flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 6 ++- arch/powerpc/cpu/mpc8xxx/srio.c | 42 ++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 61 +++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/immap_85xx.h | 3 ++ boards.cfg | 3 ++ include/configs/corenet_ds.h | 18 ++++++++++ 6 files changed, 131 insertions(+), 2 deletions(-) create mode 100644 arch/powerpc/include/asm/fsl_srio.h
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 9141ba4..42d6475 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -37,6 +37,7 @@ #include <asm/mmu.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h> #include <linux/compiler.h> #include "mp.h" #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND @@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
-extern void srio_init(void); - #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, @@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO srio_init(); +#ifdef CONFIG_SRIOBOOT_MASTER + srio_boot_master(); +#endif #endif
#if defined(CONFIG_MP) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e46d328..e8ce3a3 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -21,6 +21,7 @@ #include <config.h> #include <asm/fsl_law.h> #include <asm/fsl_serdes.h> +#include <asm/fsl_srio.h>
#if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 @@ -84,3 +85,44 @@ void srio_init(void) setbits_be32(&gur->devdisr, _DEVDISR_RMU); } } + +#ifdef CONFIG_SRIOBOOT_MASTER +void srio_boot_master(void) +{ + ccsr_rio_t *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + + /* set port accept-all */ + out_be32((u32)&srio->ptaacr + CONFIG_SRIOBOOT_MASTER_PORT * 0x80, + 0x10000001); + + printf("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* configure inbound window1 for slave's u-boot image */ + printf("SRIOBOOT - MASTER: Inbound window1 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((u32)&srio->riwtar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12); + out_be32((u32)&srio->riwbar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12); + out_be32((u32)&srio->riwar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80f55000 + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window2 for slave's u-boot image */ + printf("SRIOBOOT - MASTER: Inbound window2 for slave's image; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2, + (u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE); + out_be32((u32)&srio->riwtar2 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12); + out_be32((u32)&srio->riwbar2 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12); + out_be32((u32)&srio->riwar2 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80f55000 + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); +} +#endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h new file mode 100644 index 0000000..e4cd9b6 --- /dev/null +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -0,0 +1,61 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _FSL_SRIO_H_ +#define _FSL_SRIO_H_ + +enum atmu_size { + ATMU_SIZE_4K = 0xb, + ATMU_SIZE_8K, + ATMU_SIZE_16K, + ATMU_SIZE_32K, + ATMU_SIZE_64K, + ATMU_SIZE_128K, + ATMU_SIZE_256K, + ATMU_SIZE_512K, + ATMU_SIZE_1M, + ATMU_SIZE_2M, + ATMU_SIZE_4M, + ATMU_SIZE_8M, + ATMU_SIZE_16M, + ATMU_SIZE_32M, + ATMU_SIZE_64M, + ATMU_SIZE_128M, + ATMU_SIZE_256M, + ATMU_SIZE_512M, + ATMU_SIZE_1G, + ATMU_SIZE_2G, + ATMU_SIZE_4G, + ATMU_SIZE_8G, + ATMU_SIZE_16G, + ATMU_SIZE_32G, + ATMU_SIZE_64G, +}; + +#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1) +#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1)) + +extern void srio_init(void); +#ifdef CONFIG_SRIOBOOT_MASTER +extern void srio_boot_master(void); +#endif +#endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 623be17..2f31f96 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2546,6 +2546,7 @@ typedef struct ccsr_snvs_regs {
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) @@ -2619,6 +2620,8 @@ typedef struct ccsr_snvs_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) #define CONFIG_SYS_FSL_FM2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) +#define CONFIG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) diff --git a/boards.cfg b/boards.cfg index dc51211..27f3900 100644 --- a/boards.cfg +++ b/boards.cfg @@ -734,6 +734,7 @@ P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -741,11 +742,13 @@ P4080DS powerpc mpc85xx corenet_ds freesca P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e38f69d..2ef5f1b 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -374,6 +374,24 @@ #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/* + * SRIOBOOT - MASTER + */ +#ifdef CONFIG_SRIOBOOT_MASTER +/* master port for srioboot*/ +#define CONFIG_SRIOBOOT_MASTER_PORT 0 +/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ +/* + *for slave u-boot IMAGE instored in master memory space, + *PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +#endif + +/* * eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI
Dear Liu Gang,
In message 1326195751-20729-4-git-send-email-Gang.Liu@freescale.com you wrote:
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements:
master:
- Nor flash for its own u-boot image, ucode and ENV space.
- Slave's u-boot image in master Nor flash.
- Normally boot from local Nor flash.
Please use "NOR flash" (or "nor flash", if you insist). "Nor" makes no sense. Please fix globally.
- printf("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
CONFIG_SRIOBOOT_MASTER_PORT);- /* configure inbound window1 for slave's u-boot image */
- printf("SRIOBOOT - MASTER: Inbound window1 for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
As mentioned before, this looks a lot like debug code, that should be removed from a production version. Use debug() instead?
- out_be32((u32)&srio->riwtar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);- out_be32((u32)&srio->riwbar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);- out_be32((u32)&srio->riwar1 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
0x80f55000| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
This comment applies to the whole patch series:
- Get rid of the base address + oofset notation. User C structs instead. - Get rid of hard coded magic numbers. #define the needed values in a readable way.
Thanks.
Best regards,
Wolfgang Denk
Dear Wolfgang,
On Wed, 2012-01-11 at 08:31 +0100, Wolfgang Denk wrote:
- Normally boot from local Nor flash.
Please use "NOR flash" (or "nor flash", if you insist). "Nor" makes no sense. Please fix globally.
Thanks, will modify.
- printf("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
CONFIG_SRIOBOOT_MASTER_PORT);- /* configure inbound window1 for slave's u-boot image */
- printf("SRIOBOOT - MASTER: Inbound window1 for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);As mentioned before, this looks a lot like debug code, that should be removed from a production version. Use debug() instead?
These parameters are very important for the boot from srio, for the different productions may should be different values. So I think that would be better to keep these informations. I'll use debug() instead!
This comment applies to the whole patch series:
- Get rid of the base address + oofset notation. User C structs instead.
- Get rid of hard coded magic numbers. #define the needed values in a readable way.
Thanks, will modify.
Best Regards,
Liu Gang
For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements:
master: 1. Nor flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master Nor flash. 3. Normally boot from local Nor flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot.
For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- board/freescale/common/p_corenet/law.c | 9 +++++++++ board/freescale/common/p_corenet/tlb.c | 9 +++++++++ boards.cfg | 3 +++ drivers/net/fm/fm.c | 2 ++ include/configs/corenet_ds.h | 21 +++++++++++++++++++++ 5 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 09ef561..1fbab4d 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -48,6 +48,15 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_NAND_BASE_PHYS SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), +#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) + SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), +#endif +#endif };
int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index 6a0026a..cb4339f 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_1M, 1), +#elif defined(CONFIG_SRIOBOOT_SLAVE) + /* + * *I*G - SRIOBOOT-SLAVE. When slave boot, the address of the + * space is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR, + CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/boards.cfg b/boards.cfg index 27f3900..0ea8988 100644 --- a/boards.cfg +++ b/boards.cfg @@ -735,6 +735,7 @@ P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER +P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P3060QDS powerpc mpc85xx p3060qds freescale P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT @@ -743,12 +744,14 @@ P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER +P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5020DS powerpc mpc85xx corenet_ds freescale P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER +P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 0b8c33f..49c74c2 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg) /* flush cache after read */ flush_cache((ulong)addr, cnt * 512); } +#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE) + void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR; #endif
/* Upload the Fman microcode if it's present */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 2ef5f1b..e4f562c 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -33,6 +33,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif
+#ifdef CONFIG_SRIOBOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR CONFIG_SYS_TEXT_BASE & 0xfff00000 +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -392,6 +401,15 @@ #endif
/* + * SRIOBOOT - SLAVE + */ +#ifdef CONFIG_SRIOBOOT_SLAVE +/* slave port for srioboot*/ +#define CONFIG_SRIOBOOT_SLAVE_PORT0 +/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#endif + +/* * eSPI - Enhanced SPI */ #define CONFIG_FSL_ESPI @@ -511,6 +529,9 @@ #elif defined(CONFIG_NAND) #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang Gang.Liu@freescale.com wrote:
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR Â Â 0
Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it?
-----Original Message----- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 1:11 AM To: Liu Gang-B34182 Cc: u-boot@lists.denx.de; Alexandre.Bounine@idt.com; Gala Kumar-B11780; Zang Roy-R61911; Xie Shaohui-B21989 Subject: Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO
On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang Gang.Liu@freescale.com wrote:
+#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define +CONFIG_SYS_QE_FMAN_FW_ADDR Â Â 0
Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in "[PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO", I'll add descriptions about this definition in PATCH 5/8. The function "fm_init_common" in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE.
-- Timur Tabi Linux kernel developer at Freescale
Liu Gang-B34182 wrote:
Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in "[PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO",
You need to update the README. That's where all the other CONFIG_SYS_QE_FMAN_FW_xxx macros are documented.
I'll add descriptions about this definition in PATCH 5/8. The function "fm_init_common" in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE.
The code which adds CONFIG_SYS_QE_FMAN_FW_IN_REMOTE support should be its own patch. And the patch summary should say "CONFIG_SYS_QE_FMAN_FW_IN_REMOTE".
Thanks very much! I'll update the patch based on your comments.
Best Regards,
Liu Gang
-----Original Message----- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 11:00 AM To: Liu Gang-B34182 Cc: 'u-boot@lists.denx.de'; 'Alexandre.Bounine@idt.com'; Gala Kumar-B11780; Zang Roy-R61911; Xie Shaohui-B21989 Subject: Re: [U-Boot] [PATCH 5/8] powerpc/boot: Slave module for boot from SRIO
Liu Gang-B34182 wrote:
Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in "[PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO",
You need to update the README. That's where all the other CONFIG_SYS_QE_FMAN_FW_xxx macros are documented.
I'll add descriptions about this definition in PATCH 5/8. The function "fm_init_common" in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE.
The code which adds CONFIG_SYS_QE_FMAN_FW_IN_REMOTE support should be its own patch. And the patch summary should say "CONFIG_SYS_QE_FMAN_FW_IN_REMOTE".
-- Timur Tabi Linux kernel developer at Freescale
Dear Liu Gang-B34182,
In message 9A1C2A9ACC704641BC472A1588CE1647164EBD@039-SN1MPN1-005.039d.mgd.msft.net you wrote:
Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in "[PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO", I'll add descriptions about this definition in PATCH 5/8. The function "fm_init_common" in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE.
Please:
- do not full-quote. - restrict your line length to some 70 characters or so - use proper quoting; see http://www.netmeister.org/news/learn2quote.html
Thanks.
Best regards,
Wolfgang Denk
Dear Wolfgang,
On Wed, 2012-01-11 at 08:27 +0100, Wolfgang Denk wrote:
Where is CONFIG_SYS_QE_FMAN_FW_IN_REMOTE documented? And where is the code that uses it? [Liu Gang-B34182] Sorry I documented this definition in "[PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO", I'll add descriptions about this definition in PATCH 5/8. The function "fm_init_common" in the file drivers/net/fm/fm.c uses the CONFIG_SYS_QE_FMAN_FW_IN_REMOTE.
Please:
- do not full-quote.
- restrict your line length to some 70 characters or so
- use proper quoting; see http://www.netmeister.org/news/learn2quote.html
I'm sorry for the late reply because of some e-mail problem of my system. I'm learning the information you provided, it's very useful. Thanks very much!
Best Regards,
Liu Gang
When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface.
Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- arch/powerpc/cpu/mpc8xxx/srio.c | 14 ++++++++++++++ board/freescale/common/p_corenet/law.c | 4 ++++ board/freescale/common/p_corenet/tlb.c | 10 ++++++++++ include/configs/corenet_ds.h | 17 ++++++++++++++++- 4 files changed, 44 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index e8ce3a3..740d28a 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -124,5 +124,19 @@ void srio_boot_master(void) out_be32((u32)&srio->riwar2 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0x80f55000 | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE)); + + /* configure inbound window for slave's ucode */ + printf("SRIOBOOT - MASTER: Inbound window for slave's ucode; " + "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n", + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS, + (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE); + out_be32((u32)&srio->riwtar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12); + out_be32((u32)&srio->riwbar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12); + out_be32((u32)&srio->riwar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80f55000 + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); } #endif diff --git a/board/freescale/common/p_corenet/law.c b/board/freescale/common/p_corenet/law.c index 1fbab4d..c4566dd 100644 --- a/board/freescale/common/p_corenet/law.c +++ b/board/freescale/common/p_corenet/law.c @@ -52,9 +52,13 @@ struct law_entry law_table[] = { #if defined(CONFIG_SRIOBOOT_SLAVE_PORT0) SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_1), #elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1) SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), + SET_LAW(CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + LAW_SIZE_1M, LAW_TRGT_IF_RIO_2), #endif #endif }; diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c index cb4339f..70779f1 100644 --- a/board/freescale/common/p_corenet/tlb.c +++ b/board/freescale/common/p_corenet/tlb.c @@ -147,6 +147,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 16, BOOKE_PAGESZ_1M, 1), #endif +#ifdef CONFIG_SRIOBOOT_SLAVE + /* + * *I*G - SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode + * and ENV from master + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR, + CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 17, BOOKE_PAGESZ_1M, 1), +#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e4f562c..3b2ff15 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -398,6 +398,13 @@ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +/* + *for slave UCODE instored in master memory space, + *PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ #endif
/* @@ -407,6 +414,9 @@ /* slave port for srioboot*/ #define CONFIG_SRIOBOOT_SLAVE_PORT0 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR) #endif
/* @@ -530,8 +540,13 @@ #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIOBOOT_SLAVE) +/* + * slave's ucode is stored in master's Nor flash, the address 0xFFE00000 can be + * mapped from slave TLB->slave LAW->slave SRIO outbound window->master + * inbound window->master LAW->the ucode address in master's Nor flash. + */ #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang Gang.Liu@freescale.com wrote:
When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface.
What kind of ucode is this? Fman or QE?
- /* configure inbound window for slave's ucode */
- printf("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
- "Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
- (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
- CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
- out_be32((u32)&srio->riwtar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
These should be "(void *)" instead of "(u32)".
-----Original Message----- From: Tabi Timur-B04825 Sent: Wednesday, January 11, 2012 1:03 AM To: Liu Gang-B34182 Cc: u-boot@lists.denx.de; Alexandre.Bounine@idt.com; Gala Kumar-B11780; Zang Roy-R61911; Xie Shaohui-B21989 Subject: Re: [U-Boot] [PATCH 6/8] powerpc/boot: Slave uploads ucode when boot from SRIO
On Tue, Jan 10, 2012 at 5:42 AM, Liu Gang Gang.Liu@freescale.com wrote:
When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface.
What kind of ucode is this? Fman or QE? [Liu Gang-B34182] Right now the ucode is for Fman.
- /* configure inbound window for slave's ucode */
- printf("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
- "Local = 0x%llx, Srio = 0x%llx, Size =
- 0x%x\n",
- (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,
- (u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,
- CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
- out_be32((u32)&srio->riwtar3 + CONFIG_SRIOBOOT_MASTER_PORT *
- 0x200,
These should be "(void *)" instead of "(u32)". [Liu Gang-B34182] Thanks very much!
-- Timur Tabi Linux kernel developer at Freescale
Dear Liu Gang,
In message 1326195751-20729-6-git-send-email-Gang.Liu@freescale.com you wrote:
When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface.
...
- /* configure inbound window for slave's ucode */
- printf("SRIOBOOT - MASTER: Inbound window for slave's ucode; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS,(u64)CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS,CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE);
Is this really needed in production code? Or should this be changed into a debug() ?
- out_be32((u32)&srio->riwtar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS >> 12);- out_be32((u32)&srio->riwbar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS >> 12);
NAK. We don't allow base address + offset notation. Please use proper C structs instead.
Please fix globally.
- out_be32((u32)&srio->riwar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200,
0x80f55000
Please don't hard code magic numbers.
Please fix globally.
+#ifdef CONFIG_SRIOBOOT_SLAVE
- /*
* *I*G - SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode* and ENV from master*/
What is this "*I*G - " doing here?
+/*
- *for slave UCODE instored in master memory space,
- *PHYS must be aligned based on the SIZE
- */
Please add a space between the '*' anf the text.
Please fix globally.
Best regards,
Wolfgang Denk
Dear Wolfgang,
On Wed, 2012-01-11 at 08:23 +0100, Wolfgang Denk wrote:
+#ifdef CONFIG_SRIOBOOT_SLAVE
- /*
* *I*G - SRIOBOOT-SLAVE. 1M space from 0xffe00000 for fetching ucode* and ENV from master*/What is this "*I*G - " doing here?
This means that the TLB entry will be set with attribute "MAS2_I" and "MAS2_G".
This follows the existing style of the file.
+/*
- *for slave UCODE instored in master memory space,
- *PHYS must be aligned based on the SIZE
- */
Please add a space between the '*' anf the text.
Please fix globally.
Thanks, will add.
Best Regards,
Liu Gang
When boot from SRIO, slave's ENV can be stored in master's memory space, then slave can fetch the ENV through SRIO interface.
NOTE: Because the slave can not erase, write master's Norflash by SRIO interface, so it can not modify the ENV parameters stored in master's Norflash using "saveenv" or other commands.
Master needs to: 1. Put the slave's ENV into it's own memory space. 2. Set an inbound SRIO window covered slave's ENV stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode and ENV from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode and ENV.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- arch/powerpc/cpu/mpc8xxx/srio.c | 14 +++++++ common/Makefile | 1 + common/cmd_nvedit.c | 3 +- common/env_remote.c | 78 +++++++++++++++++++++++++++++++++++++++ include/configs/corenet_ds.h | 14 +++++++ 5 files changed, 109 insertions(+), 1 deletions(-) create mode 100644 common/env_remote.c
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 740d28a..c899480 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -138,5 +138,19 @@ void srio_boot_master(void) out_be32((u32)&srio->riwar3 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0x80f55000 | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE)); + + /* configure inbound window for slave's ENV */ + printf("SRIOBOOT - MASTER: Inbound window for slave's ENV; " + "Local = 0x%llx, Siro = 0x%llx, Size = 0x%x\n", + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS, + CONFIG_SRIOBOOT_SLAVE_ENV_SIZE); + out_be32((u32)&srio->riwtar4 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS >> 12); + out_be32((u32)&srio->riwbar4 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS >> 12); + out_be32((u32)&srio->riwar4 + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80f55000 + | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } #endif diff --git a/common/Makefile b/common/Makefile index 1b672ad..5c99450 100644 --- a/common/Makefile +++ b/common/Makefile @@ -61,6 +61,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o +COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 5995354..d8372fd 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -65,9 +65,10 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CONFIG_ENV_IS_IN_NVRAM) && \ !defined(CONFIG_ENV_IS_IN_ONENAND) && \ !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \ + !defined(CONFIG_ENV_IS_IN_REMOTE) && \ !defined(CONFIG_ENV_IS_NOWHERE) # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\ -SPI_FLASH|MG_DISK|NVRAM|MMC} or CONFIG_ENV_IS_NOWHERE +SPI_FLASH|MG_DISK|NVRAM|MMC|REMOTE} or CONFIG_ENV_IS_NOWHERE #endif
#define XMK_STR(x) #x diff --git a/common/env_remote.c b/common/env_remote.c new file mode 100644 index 0000000..4c6b781 --- /dev/null +++ b/common/env_remote.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <environment.h> +#include <linux/stddef.h> + +char *env_name_spec = "Remote"; + +#ifdef ENV_IS_EMBEDDED +env_t *env_ptr = &environment; +#else /* ! ENV_IS_EMBEDDED */ +env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; +#endif /* ENV_IS_EMBEDDED */ + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET 0 +#endif + +uchar env_get_char_spec(int index) +{ + return *((uchar *)(gd->env_addr + index)); +} + +int env_init(void) +{ + if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) { + gd->env_addr = (ulong)&(env_ptr->data); + gd->env_valid = 1; + return 0; + } + + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; + return 0; +} + +#ifdef CONFIG_CMD_SAVEENV +int saveenv(void) +{ +#ifdef CONFIG_SRIOBOOT_SLAVE + printf("Can not support the 'saveenv' when boot from SRIO!\n"); + return 1; +#endif + return 0; +} +#endif /* CONFIG_CMD_SAVEENV */ + +void env_relocate_spec(void) +{ +#if !defined(ENV_IS_EMBEDDED) + env_import((char *)env_ptr, 1); +#endif +} diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 3b2ff15..f974630 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -77,7 +77,9 @@ #define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_SRIOBOOT_SLAVE #define CONFIG_ENV_IS_NOWHERE +#endif #else #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -105,6 +107,11 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #elif defined(CONFIG_ENV_IS_NOWHERE) #define CONFIG_ENV_SIZE 0x2000 #else @@ -405,6 +412,13 @@ #define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull #define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull #define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ +/* + *for slave ENV instored in master memory space, + *PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ #endif
/*
When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface.
Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 + arch/powerpc/cpu/mpc8xxx/srio.c | 114 +++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 3 + include/configs/corenet_ds.h | 4 + 4 files changed, 124 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 42d6475..9284e443 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -444,6 +444,9 @@ skip_l2: srio_init(); #ifdef CONFIG_SRIOBOOT_MASTER srio_boot_master(); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF + srio_boot_master_release_slave(); +#endif #endif #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c899480..66ecf0b 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -23,6 +23,11 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h>
+#define RIO_LCSBA1CSR_OFFSET 0x5c +#define RIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ +#define RIO_RW_WIN_SIZE 0x100000 /* 1M */ +#define RIO_LCSBA1CSR 0x60000000 + #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 @@ -153,4 +158,113 @@ void srio_boot_master(void) 0x80f55000 | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } + +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +void srio_boot_master_release_slave(void) +{ + ccsr_rio_t *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + u32 escsr; + + printf("SRIOBOOT - MASTER: " + "Check the port status and release slave core ...\n"); + + escsr = in_be32((u32)&srio->pescsr + + CONFIG_SRIOBOOT_MASTER_PORT * 0x20); + if (escsr & 0x2) { + if (escsr & 0x10100) { + printf("SRIOBOOT - MASTER: Port [ %d ] is error.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + } else { + printf("SRIOBOOT - MASTER: " + "Port [ %d ] is ready, now release slave's core ...\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* + * configure outbound window + * with maintenance attribute to set slave's LCSBA1CSR + */ + out_be32((u32)&srio->rowtar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0); + out_be32((u32)&srio->rowtear1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((u32)&srio->rowbar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + else + out_be32((u32)&srio->rowbar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + out_be32((u32)&srio->rowar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80077000 + | atmu_size_mask(RIO_MAINT_WIN_SIZE)); + + /* + * configure outbound window + * with R/W attribute to set slave's BRR + */ + out_be32((u32)&srio->rowtar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + RIO_LCSBA1CSR >> 9); + out_be32((u32)&srio->rowtear2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((u32)&srio->rowbar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + (CONFIG_SYS_SRIO2_MEM_PHYS + + RIO_MAINT_WIN_SIZE) >> 12); + else + out_be32((u32)&srio->rowbar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + (CONFIG_SYS_SRIO1_MEM_PHYS + + RIO_MAINT_WIN_SIZE) >> 12); + out_be32((u32)&srio->rowar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80045000 + | atmu_size_mask(RIO_RW_WIN_SIZE)); + + /* + * Set the LCSBA1CSR register in slave + * by the maint-outbound window + */ + if (CONFIG_SRIOBOOT_MASTER_PORT) { + out_be32(CONFIG_SYS_SRIO2_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET, + RIO_LCSBA1CSR); + while (in_be32(CONFIG_SYS_SRIO2_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET) + != RIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32(CONFIG_SYS_SRIO2_MEM_VIRT + + RIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } else { + out_be32(CONFIG_SYS_SRIO1_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET, RIO_LCSBA1CSR); + while (in_be32(CONFIG_SYS_SRIO1_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET) + != RIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32(CONFIG_SYS_SRIO1_MEM_VIRT + + RIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } + printf("SRIOBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } + } else + printf("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", + CONFIG_SRIOBOOT_MASTER_PORT); +} +#endif #endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index e4cd9b6..a905a26 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -57,5 +57,8 @@ enum atmu_size { extern void srio_init(void); #ifdef CONFIG_SRIOBOOT_MASTER extern void srio_boot_master(void); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +extern void srio_boot_master_release_slave(void); +#endif #endif #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f974630..f34dffd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -419,6 +419,10 @@ #define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +/* slave core release by master*/ +#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF +#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ #endif
/*
Dear Liu Gang,
In message 1326195751-20729-1-git-send-email-Gang.Liu@freescale.com you wrote:
Many registers were not defined in the struct ccsr_rio_t in the file arch/powerpc/include/asm/immap_85xx.h. For example it lacks registers from offset 0xc0600 to 0xd0160. Accordingly, some register's offset need to be modified in the struct.
Your Subject line is way too long, make it shorter.
Also, it is not correct - the registers may be missing for some extensions you will add, but that has not been an error so foar, so this patch is an extension, but not a correction.
/* RapidIO Registers */ typedef struct ccsr_rio {
- u32 didcar; /* Device Identity Capability */
- u32 dicar; /* Device Information Capability */
- u32 aidcar; /* Assembly Identity Capability */
- u32 aicar; /* Assembly Information Capability */
- u32 pefcar; /* Processing Element Features Capability */
- u32 spicar; /* Switch Port Information Capability */
- u32 socar; /* Source Operations Capability */
- u32 docar; /* Destination Operations Capability */
- u32 didcar; /* 0xc0000 - Device Identity CAR */
- u32 dicar; /* 0xc0004 - Device Information CAR */
- u32 aidcar; /* 0xc0008 - Assembly Identity CAR */
- u32 aicar; /* 0xc000c - Assembly Information CAR */
- u32 pefcar; /* 0xc0010 - Processing Element Features CAR */
- u32 spicar; /* 0xc0014 - Switch Port Information CAR */
- u32 socar; /* 0xc0018 - Source Operations CAR */
- u32 docar; /* 0xc001c - Destination Operations CAR */
NAK. We don't include offsets into the header files. Please keep this consistent with the rest of this file, and with other, similar files.
Restrict your patch on adding any new fields, and foillow the exiting style.
Best regards,
Wolfgang Denk
Hi, Kumar,
On Thu, 2012-01-12 at 10:47 -0600, Kumar Gala wrote:
On Jan 10, 2012, at 5:42 AM, Liu Gang wrote:
- u32 didcar; /* 0xc0000 - Device Identity CAR */
Drop the '0xc' prefix in the comment, same comment for all registers.
Thanks, I'll rewrite this struct.
Best Regards,
Liu Gang
participants (5)
-
Kumar Gala -
Liu Gang -
Liu Gang-B34182 -
Tabi Timur-B04825 -
Wolfgang Denk