[U-Boot] [PATCH 1/2] mtd: nand: am335x_spl_bch.c: Fix problem with NAND_CMD_RNDOUT
From: Marek Belisko marek.belisko@gmail.com
On some NAND devices (e.g. Hynix H27U2G8F2CTR-BI on Siemens DXR2 / Draco boards) the SPL issues the following bit-flip error messages:
nand: bit-flip corrected @oob=0 ...
This patch makes sure that only the required address cycles are sent to the NAND chip.
The same issue has been reported by Bacem Daassi:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/259699.aspx
" The issue is mainly due to a NAND protocol violation in the omap driver since the Random Data Output command (05h-E0h) expects to see only the column address that should be addressed within the already loaded read page into the read buffer. Only 2 address cycles with ALE active should be provided between the 05h and E0h commands. The Page read command expects the full address footprint (2bytes for column address + 3bytes for row address), but once the page is loaded into the read buffer, Random Data Output should be used with only 2bytes for column address. "
Signed-off-by: Marek Belisko marek.belisko@gmail.com Signed-off-by: Stefan Roese sr@denx.de Tested-by: Samuel Egli samuel.egli@siemens.com Cc: Pekon Gupta pekon@ti.com Cc: Scott Wood scottwood@freescale.com --- drivers/mtd/nand/am335x_spl_bch.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index c84851b..dd76149 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -64,14 +64,18 @@ static int nand_command(int block, int page, uint32_t offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(&mtd, ((page_addr >> 8) & 0xff), + + if (cmd != NAND_CMD_RNDOUT) { + hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ + hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE - /* One more address cycle for devices > 128MiB */ - hwctrl(&mtd, (page_addr >> 16) & 0x0f, + /* One more address cycle for devices > 128MiB */ + hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif + } + hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
if (cmd == NAND_CMD_READ0) {
From: Pekon Gupta pekon@ti.com
On some NAND devices (e.g. Hynix H27U2G8F2CTR-BI on Siemens DXR2 / Draco boards) the SPL issues the following bit-flip error messages:
nand: bit-flip corrected @oob=0 ...
This patch makes sure that only the required address cycles are sent to the NAND chip.
The same issue has been reported by Bacem Daassi:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/259699.aspx
" The issue is mainly due to a NAND protocol violation in the omap driver since the Random Data Output command (05h-E0h) expects to see only the column address that should be addressed within the already loaded read page into the read buffer. Only 2 address cycles with ALE active should be provided between the 05h and E0h commands. The Page read command expects the full address footprint (2bytes for column address + 3bytes for row address), but once the page is loaded into the read buffer, Random Data Output should be used with only 2bytes for column address. "
Signed-off-by: Pekon Gupta pekon@ti.com Signed-off-by: Stefan Roese sr@denx.de Tested-by: Samuel Egli samuel.egli@siemens.com Cc: Marek Belisko marek.belisko@gmail.com Cc: Scott Wood scottwood@freescale.com --- drivers/mtd/nand/nand_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 1ce55fd..f11fce4 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -674,7 +674,7 @@ static void nand_command_lp(struct mtd_info *mtd, unsigned int command, ctrl &= ~NAND_CTRL_CHANGE; chip->cmd_ctrl(mtd, column >> 8, ctrl); } - if (page_addr != -1) { + if (page_addr != -1 && command != NAND_CMD_RNDOUT) { chip->cmd_ctrl(mtd, page_addr, ctrl); chip->cmd_ctrl(mtd, page_addr >> 8, NAND_NCE | NAND_ALE);
From: Stefan Roese [mailto:sr@denx.de]
From: Marek Belisko marek.belisko@gmail.com
On some NAND devices (e.g. Hynix H27U2G8F2CTR-BI on Siemens DXR2 / Draco boards) the SPL issues the following bit-flip error messages:
nand: bit-flip corrected @oob=0 ...
This patch makes sure that only the required address cycles are sent to the NAND chip.
The same issue has been reported by Bacem Daassi:
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/259699.aspx
" The issue is mainly due to a NAND protocol violation in the omap driver since the Random Data Output command (05h-E0h) expects to see only the column address that should be addressed within the already loaded read page into the read buffer. Only 2 address cycles with ALE active should be provided between the 05h and E0h commands. The Page read command expects the full address footprint (2bytes for column address + 3bytes for row address), but once the page is loaded into the read buffer, Random Data Output should be used with only 2bytes for column address. "
Signed-off-by: Marek Belisko marek.belisko@gmail.com Signed-off-by: Stefan Roese sr@denx.de Tested-by: Samuel Egli samuel.egli@siemens.com Cc: Pekon Gupta pekon@ti.com Cc: Scott Wood scottwood@freescale.com
Thanks Stefan,
I was just about to re-send same patch with Marek's authorship. But as this is change in common code, can you please add below reference to datasheets from other NAND device vendors, in you commit message.
"NAND_CMD_RNDOUT (05h-E0h) needs only two cycles of column address to access data from different column within the same page. So expected sequence on NAND data-bus is <05h> <column-addr-byte1> <column-address-byte2> <E0h>
References in datasheets of parts from different NAND vendors +--------+------------------------+--------------------------------------------- |Vendor | Datasheet/Part# | Reference +--------+------------------------+--------------------------------------------- |Spansion| S34ML{01|02|04}G2 | Figure 6.12 Random Data Output In a Page |Micron | MT29F{16|32|64|128}G08A| Figure 47: CHANGE READ COLUMN (05h-E0h) Operation |Macronix| MX30LF1G08AA | Figure 10. AC Waveforms for Random Data Output |Toshiba | TC58NVG1S3ETAI0 | Figure Column Address Change in Read Cycle Timing Diagram (2/2) +--------+------------------------+---------------------------------------------
Though most NAND Devices mentioned above tend to work even if extra cycles of page-address is issued between <05h> .... <E0h> command. But Spansion devices break on this non-compliance. This patch fixes chip->cmdfunc() for all devices, as datasheet of all mentioned vendor expect same sequence."
Also, same change is required in drivers/mtd/nand/nand_spl_simple.c So, you can as well just put both in same patch.
with regards, Pekon
participants (2)
-
Gupta, Pekon -
Stefan Roese