[U-Boot] [PATCH] imx: i.MX8MQ: clear ocotp error bit

In case ocotp error bit is set, clear it.
Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/mach-imx/imx8m/soc.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 11251c5f9a..7ec39b3e47 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -169,6 +169,7 @@ static void imx_set_wdog_powerdown(bool enable)
int arch_cpu_init(void) { + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; /* * Init timer at very early state, because sscg pll setting * will use it @@ -180,6 +181,12 @@ int arch_cpu_init(void) imx_set_wdog_powerdown(false); }
+ if (is_imx8mq()) { + clock_enable(CCGR_OCOTP, 1); + if (readl(&ocotp->ctrl) & 0x200) + writel(0x200, &ocotp->ctrl_clr); + } + return 0; }

From: Ye Li ye.li@nxp.com
On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to Redundancy mode not ECC, so they can support to program different bits of a word in multiple times.
Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/misc/mxc_ocotp.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index f84fe88db1..33ea31135c 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -354,13 +354,17 @@ static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
/* Only bank 0 and 1 are redundancy mode, others are ECC mode */ if (bank != 0 && bank != 1) { - ret = fuse_sense(bank, word, &val); - if (ret) - return ret; - - if (val != 0) { - printf("mxc_ocotp: The word has been programmed, no more write\n"); - return -EPERM; + if ((soc_rev() < CHIP_REV_2_0) || + ((soc_rev() >= CHIP_REV_2_0) && + bank != 9 && bank != 10 && bank != 28)) { + ret = fuse_sense(bank, word, &val); + if (ret) + return ret; + + if (val != 0) { + printf("mxc_ocotp: The word has been programmed, no more write\n"); + return -EPERM; + } } } #endif

From: Ye Li ye.li@nxp.com On mx7ulp B0, beside bank 0 and 1, the fuse bank 9, 10, 28 are changed to Redundancy mode not ECC, so they can support to program different bits of a word in multiple times. Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic

From: Ye Li ye.li@nxp.com
On iMX8MQ Rev B1, reading from fuse box is not allowed. The OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa for chip rev. So u-boot has to disable the fuse sense function for it.
Signed-off-by: Ye Li ye.li@nxp.com Tested-by: Anson Huang Anson.Huang@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/misc/mxc_ocotp.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 33ea31135c..1b945e9727 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -321,6 +321,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val) struct ocotp_regs *regs; int ret;
+ if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) { + printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__); + return -EPERM; + } + ret = prepare_read(®s, bank, word, val, __func__); if (ret) return ret;

From: Ye Li ye.li@nxp.com On iMX8MQ Rev B1, reading from fuse box is not allowed. The OCOTP_READ_FUSE_DATA register is tied to magic number 0xff0055aa for chip rev. So u-boot has to disable the fuse sense function for it. Signed-off-by: Ye Li ye.li@nxp.com Tested-by: Anson Huang Anson.Huang@nxp.com Signed-off-by: Peng Fan peng.fan@nxp.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic

In case ocotp error bit is set, clear it. Signed-off-by: Peng Fan peng.fan@nxp.com
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (2)
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Peng Fan
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sbabic@denx.de