[U-Boot] [PATCH 1/8] mips: ath79: Fix ar71xx_regs.h indent
The indent in this file triggers my OCD, so fix it. Replace multiple spaces with tabs and align the values in one column.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 2103 ++++++++++++----------- 1 file changed, 1069 insertions(+), 1034 deletions(-)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index 893dedc..bff9d05 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -16,709 +16,744 @@ #include <linux/bitops.h> #else #ifndef BIT -#define BIT(nr) (1 << (nr)) +#define BIT(nr) (1 << (nr)) #endif #endif
-#define AR71XX_APB_BASE 0x18000000 -#define AR71XX_GE0_BASE 0x19000000 -#define AR71XX_GE0_SIZE 0x10000 -#define AR71XX_GE1_BASE 0x1a000000 -#define AR71XX_GE1_SIZE 0x10000 -#define AR71XX_EHCI_BASE 0x1b000000 -#define AR71XX_EHCI_SIZE 0x1000 -#define AR71XX_OHCI_BASE 0x1c000000 -#define AR71XX_OHCI_SIZE 0x1000 -#define AR71XX_SPI_BASE 0x1f000000 -#define AR71XX_SPI_SIZE 0x01000000 - -#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) -#define AR71XX_DDR_CTRL_SIZE 0x100 -#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) -#define AR71XX_UART_SIZE 0x100 -#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -#define AR71XX_USB_CTRL_SIZE 0x100 -#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -#define AR71XX_GPIO_SIZE 0x100 -#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -#define AR71XX_PLL_SIZE 0x100 -#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) -#define AR71XX_RESET_SIZE 0x100 -#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -#define AR71XX_MII_SIZE 0x100 - -#define AR71XX_PCI_MEM_BASE 0x10000000 -#define AR71XX_PCI_MEM_SIZE 0x07000000 - -#define AR71XX_PCI_WIN0_OFFS 0x10000000 -#define AR71XX_PCI_WIN1_OFFS 0x11000000 -#define AR71XX_PCI_WIN2_OFFS 0x12000000 -#define AR71XX_PCI_WIN3_OFFS 0x13000000 -#define AR71XX_PCI_WIN4_OFFS 0x14000000 -#define AR71XX_PCI_WIN5_OFFS 0x15000000 -#define AR71XX_PCI_WIN6_OFFS 0x16000000 -#define AR71XX_PCI_WIN7_OFFS 0x07000000 +#define AR71XX_APB_BASE 0x18000000 +#define AR71XX_GE0_BASE 0x19000000 +#define AR71XX_GE0_SIZE 0x10000 +#define AR71XX_GE1_BASE 0x1a000000 +#define AR71XX_GE1_SIZE 0x10000 +#define AR71XX_EHCI_BASE 0x1b000000 +#define AR71XX_EHCI_SIZE 0x1000 +#define AR71XX_OHCI_BASE 0x1c000000 +#define AR71XX_OHCI_SIZE 0x1000 +#define AR71XX_SPI_BASE 0x1f000000 +#define AR71XX_SPI_SIZE 0x01000000 + +#define AR71XX_DDR_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00000000) +#define AR71XX_DDR_CTRL_SIZE 0x100 +#define AR71XX_UART_BASE \ + (AR71XX_APB_BASE + 0x00020000) +#define AR71XX_UART_SIZE 0x100 +#define AR71XX_USB_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00030000) +#define AR71XX_USB_CTRL_SIZE 0x100 +#define AR71XX_GPIO_BASE \ + (AR71XX_APB_BASE + 0x00040000) +#define AR71XX_GPIO_SIZE 0x100 +#define AR71XX_PLL_BASE \ + (AR71XX_APB_BASE + 0x00050000) +#define AR71XX_PLL_SIZE 0x100 +#define AR71XX_RESET_BASE \ + (AR71XX_APB_BASE + 0x00060000) +#define AR71XX_RESET_SIZE 0x100 +#define AR71XX_MII_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR71XX_MII_SIZE 0x100 + +#define AR71XX_PCI_MEM_BASE 0x10000000 +#define AR71XX_PCI_MEM_SIZE 0x07000000 + +#define AR71XX_PCI_WIN0_OFFS 0x10000000 +#define AR71XX_PCI_WIN1_OFFS 0x11000000 +#define AR71XX_PCI_WIN2_OFFS 0x12000000 +#define AR71XX_PCI_WIN3_OFFS 0x13000000 +#define AR71XX_PCI_WIN4_OFFS 0x14000000 +#define AR71XX_PCI_WIN5_OFFS 0x15000000 +#define AR71XX_PCI_WIN6_OFFS 0x16000000 +#define AR71XX_PCI_WIN7_OFFS 0x07000000
#define AR71XX_PCI_CFG_BASE \ (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000) -#define AR71XX_PCI_CFG_SIZE 0x100 - -#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -#define AR7240_USB_CTRL_SIZE 0x100 -#define AR7240_OHCI_BASE 0x1b000000 -#define AR7240_OHCI_SIZE 0x1000 - -#define AR724X_PCI_MEM_BASE 0x10000000 -#define AR724X_PCI_MEM_SIZE 0x04000000 - -#define AR724X_PCI_CFG_BASE 0x14000000 -#define AR724X_PCI_CFG_SIZE 0x1000 -#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000c0000) -#define AR724X_PCI_CRP_SIZE 0x1000 -#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000f0000) -#define AR724X_PCI_CTRL_SIZE 0x100 - -#define AR724X_EHCI_BASE 0x1b000000 -#define AR724X_EHCI_SIZE 0x1000 - -#define AR913X_EHCI_BASE 0x1b000000 -#define AR913X_EHCI_SIZE 0x1000 -#define AR913X_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) -#define AR913X_WMAC_SIZE 0x30000 - -#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000) -#define AR933X_UART_SIZE 0x14 -#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define AR933X_GMAC_SIZE 0x04 -#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define AR933X_WMAC_SIZE 0x20000 -#define AR933X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) -#define AR933X_RTC_SIZE 0x1000 -#define AR933X_EHCI_BASE 0x1b000000 -#define AR933X_EHCI_SIZE 0x1000 -#define AR933X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -#define AR933X_SRIF_SIZE 0x1000 - -#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define AR934X_GMAC_SIZE 0x14 -#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define AR934X_WMAC_SIZE 0x20000 -#define AR934X_EHCI_BASE 0x1b000000 -#define AR934X_EHCI_SIZE 0x200 -#define AR934X_NFC_BASE 0x1b000200 -#define AR934X_NFC_SIZE 0xb8 -#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -#define AR934X_SRIF_SIZE 0x1000 - -#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define QCA953X_GMAC_SIZE 0x14 -#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define QCA953X_WMAC_SIZE 0x20000 -#define QCA953X_RTC_BASE (AR71XX_APB_BASE + 0x00107000) -#define QCA953X_RTC_SIZE 0x1000 -#define QCA953X_EHCI_BASE 0x1b000000 -#define QCA953X_EHCI_SIZE 0x200 -#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000) -#define QCA953X_SRIF_SIZE 0x1000 - -#define QCA953X_PCI_CFG_BASE0 0x14000000 -#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -#define QCA953X_PCI_MEM_BASE0 0x10000000 -#define QCA953X_PCI_MEM_SIZE 0x02000000 - -#define QCA955X_PCI_MEM_BASE0 0x10000000 -#define QCA955X_PCI_MEM_BASE1 0x12000000 -#define QCA955X_PCI_MEM_SIZE 0x02000000 -#define QCA955X_PCI_CFG_BASE0 0x14000000 -#define QCA955X_PCI_CFG_BASE1 0x16000000 -#define QCA955X_PCI_CFG_SIZE 0x1000 -#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000) -#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -#define QCA955X_PCI_CRP_SIZE 0x1000 -#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000) -#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -#define QCA955X_PCI_CTRL_SIZE 0x100 - -#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define QCA955X_GMAC_SIZE 0x40 -#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define QCA955X_WMAC_SIZE 0x20000 -#define QCA955X_EHCI0_BASE 0x1b000000 -#define QCA955X_EHCI1_BASE 0x1b400000 -#define QCA955X_EHCI_SIZE 0x1000 -#define QCA955X_NFC_BASE 0x1b800200 -#define QCA955X_NFC_SIZE 0xb8 - -#define QCA956X_PCI_MEM_BASE1 0x12000000 -#define QCA956X_PCI_MEM_SIZE 0x02000000 -#define QCA956X_PCI_CFG_BASE1 0x16000000 -#define QCA956X_PCI_CFG_SIZE 0x1000 -#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000) -#define QCA956X_PCI_CRP_SIZE 0x1000 -#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000) -#define QCA956X_PCI_CTRL_SIZE 0x100 - -#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000) -#define QCA956X_WMAC_SIZE 0x20000 -#define QCA956X_EHCI0_BASE 0x1b000000 -#define QCA956X_EHCI1_BASE 0x1b400000 -#define QCA956X_EHCI_SIZE 0x200 -#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) -#define QCA956X_GMAC_SIZE 0x64 +#define AR71XX_PCI_CFG_SIZE 0x100 + +#define AR7240_USB_CTRL_BASE \ + (AR71XX_APB_BASE + 0x00030000) +#define AR7240_USB_CTRL_SIZE 0x100 +#define AR7240_OHCI_BASE 0x1b000000 +#define AR7240_OHCI_SIZE 0x1000 + +#define AR724X_PCI_MEM_BASE 0x10000000 +#define AR724X_PCI_MEM_SIZE 0x04000000 + +#define AR724X_PCI_CFG_BASE 0x14000000 +#define AR724X_PCI_CFG_SIZE 0x1000 +#define AR724X_PCI_CRP_BASE \ + (AR71XX_APB_BASE + 0x000c0000) +#define AR724X_PCI_CRP_SIZE 0x1000 +#define AR724X_PCI_CTRL_BASE \ + (AR71XX_APB_BASE + 0x000f0000) +#define AR724X_PCI_CTRL_SIZE 0x100 + +#define AR724X_EHCI_BASE 0x1b000000 +#define AR724X_EHCI_SIZE 0x1000 + +#define AR913X_EHCI_BASE 0x1b000000 +#define AR913X_EHCI_SIZE 0x1000 +#define AR913X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x000C0000) +#define AR913X_WMAC_SIZE 0x30000 + +#define AR933X_UART_BASE \ + (AR71XX_APB_BASE + 0x00020000) +#define AR933X_UART_SIZE 0x14 +#define AR933X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR933X_GMAC_SIZE 0x04 +#define AR933X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define AR933X_WMAC_SIZE 0x20000 +#define AR933X_RTC_BASE \ + (AR71XX_APB_BASE + 0x00107000) +#define AR933X_RTC_SIZE 0x1000 +#define AR933X_EHCI_BASE 0x1b000000 +#define AR933X_EHCI_SIZE 0x1000 +#define AR933X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define AR933X_SRIF_SIZE 0x1000 + +#define AR934X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define AR934X_GMAC_SIZE 0x14 +#define AR934X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define AR934X_WMAC_SIZE 0x20000 +#define AR934X_EHCI_BASE 0x1b000000 +#define AR934X_EHCI_SIZE 0x200 +#define AR934X_NFC_BASE 0x1b000200 +#define AR934X_NFC_SIZE 0xb8 +#define AR934X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define AR934X_SRIF_SIZE 0x1000 + +#define QCA953X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA953X_GMAC_SIZE 0x14 +#define QCA953X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA953X_WMAC_SIZE 0x20000 +#define QCA953X_RTC_BASE \ + (AR71XX_APB_BASE + 0x00107000) +#define QCA953X_RTC_SIZE 0x1000 +#define QCA953X_EHCI_BASE 0x1b000000 +#define QCA953X_EHCI_SIZE 0x200 +#define QCA953X_SRIF_BASE \ + (AR71XX_APB_BASE + 0x00116000) +#define QCA953X_SRIF_SIZE 0x1000 + +#define QCA953X_PCI_CFG_BASE0 0x14000000 +#define QCA953X_PCI_CTRL_BASE0 \ + (AR71XX_APB_BASE + 0x000f0000) +#define QCA953X_PCI_CRP_BASE0 \ + (AR71XX_APB_BASE + 0x000c0000) +#define QCA953X_PCI_MEM_BASE0 0x10000000 +#define QCA953X_PCI_MEM_SIZE 0x02000000 + +#define QCA955X_PCI_MEM_BASE0 0x10000000 +#define QCA955X_PCI_MEM_BASE1 0x12000000 +#define QCA955X_PCI_MEM_SIZE 0x02000000 +#define QCA955X_PCI_CFG_BASE0 0x14000000 +#define QCA955X_PCI_CFG_BASE1 0x16000000 +#define QCA955X_PCI_CFG_SIZE 0x1000 +#define QCA955X_PCI_CRP_BASE0 \ + (AR71XX_APB_BASE + 0x000c0000) +#define QCA955X_PCI_CRP_BASE1 \ + (AR71XX_APB_BASE + 0x00250000) +#define QCA955X_PCI_CRP_SIZE 0x1000 +#define QCA955X_PCI_CTRL_BASE0 \ + (AR71XX_APB_BASE + 0x000f0000) +#define QCA955X_PCI_CTRL_BASE1 \ + (AR71XX_APB_BASE + 0x00280000) +#define QCA955X_PCI_CTRL_SIZE 0x100 + +#define QCA955X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA955X_GMAC_SIZE 0x40 +#define QCA955X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA955X_WMAC_SIZE 0x20000 +#define QCA955X_EHCI0_BASE 0x1b000000 +#define QCA955X_EHCI1_BASE 0x1b400000 +#define QCA955X_EHCI_SIZE 0x1000 +#define QCA955X_NFC_BASE 0x1b800200 +#define QCA955X_NFC_SIZE 0xb8 + +#define QCA956X_PCI_MEM_BASE1 0x12000000 +#define QCA956X_PCI_MEM_SIZE 0x02000000 +#define QCA956X_PCI_CFG_BASE1 0x16000000 +#define QCA956X_PCI_CFG_SIZE 0x1000 +#define QCA956X_PCI_CRP_BASE1 \ + (AR71XX_APB_BASE + 0x00250000) +#define QCA956X_PCI_CRP_SIZE 0x1000 +#define QCA956X_PCI_CTRL_BASE1 \ + (AR71XX_APB_BASE + 0x00280000) +#define QCA956X_PCI_CTRL_SIZE 0x100 + +#define QCA956X_WMAC_BASE \ + (AR71XX_APB_BASE + 0x00100000) +#define QCA956X_WMAC_SIZE 0x20000 +#define QCA956X_EHCI0_BASE 0x1b000000 +#define QCA956X_EHCI1_BASE 0x1b400000 +#define QCA956X_EHCI_SIZE 0x200 +#define QCA956X_GMAC_BASE \ + (AR71XX_APB_BASE + 0x00070000) +#define QCA956X_GMAC_SIZE 0x64
/* * DDR_CTRL block */ -#define AR71XX_DDR_REG_CONFIG 0x00 -#define AR71XX_DDR_REG_CONFIG2 0x04 -#define AR71XX_DDR_REG_MODE 0x08 -#define AR71XX_DDR_REG_EMR 0x0c -#define AR71XX_DDR_REG_CONTROL 0x10 -#define AR71XX_DDR_REG_REFRESH 0x14 -#define AR71XX_DDR_REG_RD_CYCLE 0x18 -#define AR71XX_DDR_REG_TAP_CTRL0 0x1c -#define AR71XX_DDR_REG_TAP_CTRL1 0x20 - -#define AR71XX_DDR_REG_PCI_WIN0 0x7c -#define AR71XX_DDR_REG_PCI_WIN1 0x80 -#define AR71XX_DDR_REG_PCI_WIN2 0x84 -#define AR71XX_DDR_REG_PCI_WIN3 0x88 -#define AR71XX_DDR_REG_PCI_WIN4 0x8c -#define AR71XX_DDR_REG_PCI_WIN5 0x90 -#define AR71XX_DDR_REG_PCI_WIN6 0x94 -#define AR71XX_DDR_REG_PCI_WIN7 0x98 -#define AR71XX_DDR_REG_FLUSH_GE0 0x9c -#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 -#define AR71XX_DDR_REG_FLUSH_USB 0xa4 -#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 - -#define AR724X_DDR_REG_FLUSH_GE0 0x7c -#define AR724X_DDR_REG_FLUSH_GE1 0x80 -#define AR724X_DDR_REG_FLUSH_USB 0x84 -#define AR724X_DDR_REG_FLUSH_PCIE 0x88 - -#define AR913X_DDR_REG_FLUSH_GE0 0x7c -#define AR913X_DDR_REG_FLUSH_GE1 0x80 -#define AR913X_DDR_REG_FLUSH_USB 0x84 -#define AR913X_DDR_REG_FLUSH_WMAC 0x88 - -#define AR933X_DDR_REG_FLUSH_GE0 0x7c -#define AR933X_DDR_REG_FLUSH_GE1 0x80 -#define AR933X_DDR_REG_FLUSH_USB 0x84 -#define AR933X_DDR_REG_FLUSH_WMAC 0x88 -#define AR933X_DDR_REG_DDR2_CONFIG 0x8c -#define AR933X_DDR_REG_EMR2 0x90 -#define AR933X_DDR_REG_EMR3 0x94 -#define AR933X_DDR_REG_BURST 0x98 -#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c -#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c -#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c - -#define AR934X_DDR_REG_FLUSH_GE0 0x9c -#define AR934X_DDR_REG_FLUSH_GE1 0xa0 -#define AR934X_DDR_REG_FLUSH_USB 0xa4 -#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 -#define AR934X_DDR_REG_FLUSH_WMAC 0xac - -#define QCA953X_DDR_REG_FLUSH_GE0 0x9c -#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 -#define QCA953X_DDR_REG_FLUSH_USB 0xa4 -#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 -#define QCA953X_DDR_REG_FLUSH_WMAC 0xac -#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 -#define QCA953X_DDR_REG_BURST 0xc4 -#define QCA953X_DDR_REG_BURST2 0xc8 -#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc -#define QCA953X_DDR_REG_CTL_CONF 0x108 -#define QCA953X_DDR_REG_CONFIG3 0x15c +#define AR71XX_DDR_REG_CONFIG 0x00 +#define AR71XX_DDR_REG_CONFIG2 0x04 +#define AR71XX_DDR_REG_MODE 0x08 +#define AR71XX_DDR_REG_EMR 0x0c +#define AR71XX_DDR_REG_CONTROL 0x10 +#define AR71XX_DDR_REG_REFRESH 0x14 +#define AR71XX_DDR_REG_RD_CYCLE 0x18 +#define AR71XX_DDR_REG_TAP_CTRL0 0x1c +#define AR71XX_DDR_REG_TAP_CTRL1 0x20 + +#define AR71XX_DDR_REG_PCI_WIN0 0x7c +#define AR71XX_DDR_REG_PCI_WIN1 0x80 +#define AR71XX_DDR_REG_PCI_WIN2 0x84 +#define AR71XX_DDR_REG_PCI_WIN3 0x88 +#define AR71XX_DDR_REG_PCI_WIN4 0x8c +#define AR71XX_DDR_REG_PCI_WIN5 0x90 +#define AR71XX_DDR_REG_PCI_WIN6 0x94 +#define AR71XX_DDR_REG_PCI_WIN7 0x98 +#define AR71XX_DDR_REG_FLUSH_GE0 0x9c +#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 +#define AR71XX_DDR_REG_FLUSH_USB 0xa4 +#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + +#define AR724X_DDR_REG_FLUSH_GE0 0x7c +#define AR724X_DDR_REG_FLUSH_GE1 0x80 +#define AR724X_DDR_REG_FLUSH_USB 0x84 +#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + +#define AR913X_DDR_REG_FLUSH_GE0 0x7c +#define AR913X_DDR_REG_FLUSH_GE1 0x80 +#define AR913X_DDR_REG_FLUSH_USB 0x84 +#define AR913X_DDR_REG_FLUSH_WMAC 0x88 + +#define AR933X_DDR_REG_FLUSH_GE0 0x7c +#define AR933X_DDR_REG_FLUSH_GE1 0x80 +#define AR933X_DDR_REG_FLUSH_USB 0x84 +#define AR933X_DDR_REG_FLUSH_WMAC 0x88 +#define AR933X_DDR_REG_DDR2_CONFIG 0x8c +#define AR933X_DDR_REG_EMR2 0x90 +#define AR933X_DDR_REG_EMR3 0x94 +#define AR933X_DDR_REG_BURST 0x98 +#define AR933X_DDR_REG_TIMEOUT_MAX 0x9c +#define AR933X_DDR_REG_TIMEOUT_CNT 0x9c +#define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c + +#define AR934X_DDR_REG_FLUSH_GE0 0x9c +#define AR934X_DDR_REG_FLUSH_GE1 0xa0 +#define AR934X_DDR_REG_FLUSH_USB 0xa4 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac + +#define QCA953X_DDR_REG_FLUSH_GE0 0x9c +#define QCA953X_DDR_REG_FLUSH_GE1 0xa0 +#define QCA953X_DDR_REG_FLUSH_USB 0xa4 +#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8 +#define QCA953X_DDR_REG_FLUSH_WMAC 0xac +#define QCA953X_DDR_REG_DDR2_CONFIG 0xb8 +#define QCA953X_DDR_REG_BURST 0xc4 +#define QCA953X_DDR_REG_BURST2 0xc8 +#define QCA953X_DDR_REG_TIMEOUT_MAX 0xcc +#define QCA953X_DDR_REG_CTL_CONF 0x108 +#define QCA953X_DDR_REG_CONFIG3 0x15c
/* * PLL block */ -#define AR71XX_PLL_REG_CPU_CONFIG 0x00 -#define AR71XX_PLL_REG_SEC_CONFIG 0x04 -#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 -#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 - -#define AR71XX_PLL_DIV_SHIFT 3 -#define AR71XX_PLL_DIV_MASK 0x1f -#define AR71XX_CPU_DIV_SHIFT 16 -#define AR71XX_CPU_DIV_MASK 0x3 -#define AR71XX_DDR_DIV_SHIFT 18 -#define AR71XX_DDR_DIV_MASK 0x3 -#define AR71XX_AHB_DIV_SHIFT 20 -#define AR71XX_AHB_DIV_MASK 0x7 - -#define AR71XX_ETH0_PLL_SHIFT 17 -#define AR71XX_ETH1_PLL_SHIFT 19 - -#define AR724X_PLL_REG_CPU_CONFIG 0x00 -#define AR724X_PLL_REG_PCIE_CONFIG 0x18 - -#define AR724X_PLL_DIV_SHIFT 0 -#define AR724X_PLL_DIV_MASK 0x3ff -#define AR724X_PLL_REF_DIV_SHIFT 10 -#define AR724X_PLL_REF_DIV_MASK 0xf -#define AR724X_AHB_DIV_SHIFT 19 -#define AR724X_AHB_DIV_MASK 0x1 -#define AR724X_DDR_DIV_SHIFT 22 -#define AR724X_DDR_DIV_MASK 0x3 - -#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c - -#define AR913X_PLL_REG_CPU_CONFIG 0x00 -#define AR913X_PLL_REG_ETH_CONFIG 0x04 -#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 -#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 - -#define AR913X_PLL_DIV_SHIFT 0 -#define AR913X_PLL_DIV_MASK 0x3ff -#define AR913X_DDR_DIV_SHIFT 22 -#define AR913X_DDR_DIV_MASK 0x3 -#define AR913X_AHB_DIV_SHIFT 19 -#define AR913X_AHB_DIV_MASK 0x1 - -#define AR913X_ETH0_PLL_SHIFT 20 -#define AR913X_ETH1_PLL_SHIFT 22 - -#define AR933X_PLL_CPU_CONFIG_REG 0x00 -#define AR933X_PLL_CLK_CTRL_REG 0x08 -#define AR933X_PLL_DITHER_FRAC_REG 0x10 - -#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 -#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 -#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 -#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 - -#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) -#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 -#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 -#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 - -#define AR934X_PLL_CPU_CONFIG_REG 0x00 -#define AR934X_PLL_DDR_CONFIG_REG 0x04 -#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 -#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c - -#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 -#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 - -#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 -#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f -#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) - -#define QCA953X_PLL_CPU_CONFIG_REG 0x00 -#define QCA953X_PLL_DDR_CONFIG_REG 0x04 -#define QCA953X_PLL_CLK_CTRL_REG 0x08 -#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 -#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c -#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 -#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 - -#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 -#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 - -#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 -#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f -#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define QCA953X_PLL_CONFIG_PWD BIT(30) - -#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 -#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f -#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 -#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f -#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 -#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f -#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 -#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f - -#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 -#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff -#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 -#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff -#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 -#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f -#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 -#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f - -#define QCA953X_PLL_DIT_FRAC_EN BIT(31) - -#define QCA955X_PLL_CPU_CONFIG_REG 0x00 -#define QCA955X_PLL_DDR_CONFIG_REG 0x04 -#define QCA955X_PLL_CLK_CTRL_REG 0x08 -#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 -#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 - -#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 -#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f -#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 -#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f -#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 - -#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 -#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff -#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 -#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f -#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) -#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) -#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) - -#define QCA956X_PLL_CPU_CONFIG_REG 0x00 -#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 -#define QCA956X_PLL_DDR_CONFIG_REG 0x08 -#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c -#define QCA956X_PLL_CLK_CTRL_REG 0x10 - -#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 -#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f -#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 -#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 - -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff -#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 -#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff - -#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 -#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f -#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 -#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 - -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff -#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 -#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff - -#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) -#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) -#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) -#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 -#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f -#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 -#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f -#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 -#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f -#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) -#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) -#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) +#define AR71XX_PLL_REG_CPU_CONFIG 0x00 +#define AR71XX_PLL_REG_SEC_CONFIG 0x04 +#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 +#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + +#define AR71XX_PLL_DIV_SHIFT 3 +#define AR71XX_PLL_DIV_MASK 0x1f +#define AR71XX_CPU_DIV_SHIFT 16 +#define AR71XX_CPU_DIV_MASK 0x3 +#define AR71XX_DDR_DIV_SHIFT 18 +#define AR71XX_DDR_DIV_MASK 0x3 +#define AR71XX_AHB_DIV_SHIFT 20 +#define AR71XX_AHB_DIV_MASK 0x7 + +#define AR71XX_ETH0_PLL_SHIFT 17 +#define AR71XX_ETH1_PLL_SHIFT 19 + +#define AR724X_PLL_REG_CPU_CONFIG 0x00 +#define AR724X_PLL_REG_PCIE_CONFIG 0x18 + +#define AR724X_PLL_DIV_SHIFT 0 +#define AR724X_PLL_DIV_MASK 0x3ff +#define AR724X_PLL_REF_DIV_SHIFT 10 +#define AR724X_PLL_REF_DIV_MASK 0xf +#define AR724X_AHB_DIV_SHIFT 19 +#define AR724X_AHB_DIV_MASK 0x1 +#define AR724X_DDR_DIV_SHIFT 22 +#define AR724X_DDR_DIV_MASK 0x3 + +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c + +#define AR913X_PLL_REG_CPU_CONFIG 0x00 +#define AR913X_PLL_REG_ETH_CONFIG 0x04 +#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14 +#define AR913X_PLL_REG_ETH1_INT_CLOCK 0x18 + +#define AR913X_PLL_DIV_SHIFT 0 +#define AR913X_PLL_DIV_MASK 0x3ff +#define AR913X_DDR_DIV_SHIFT 22 +#define AR913X_DDR_DIV_MASK 0x3 +#define AR913X_AHB_DIV_SHIFT 19 +#define AR913X_AHB_DIV_MASK 0x1 + +#define AR913X_ETH0_PLL_SHIFT 20 +#define AR913X_ETH1_PLL_SHIFT 22 + +#define AR933X_PLL_CPU_CONFIG_REG 0x00 +#define AR933X_PLL_CLK_CTRL_REG 0x08 +#define AR933X_PLL_DITHER_FRAC_REG 0x10 + +#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 +#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16 +#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23 +#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define AR933X_PLL_CLK_CTRL_BYPASS BIT(2) +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x3 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x7 + +#define AR934X_PLL_CPU_CONFIG_REG 0x00 +#define AR934X_PLL_DDR_CONFIG_REG 0x04 +#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c + +#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6) + +#define QCA953X_PLL_CPU_CONFIG_REG 0x00 +#define QCA953X_PLL_DDR_CONFIG_REG 0x04 +#define QCA953X_PLL_CLK_CTRL_REG 0x08 +#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 +#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define QCA953X_PLL_DDR_DIT_FRAC_REG 0x44 +#define QCA953X_PLL_CPU_DIT_FRAC_REG 0x48 + +#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA953X_PLL_CONFIG_PWD BIT(30) + +#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define QCA953X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define QCA953X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define QCA953X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define QCA953X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_SHIFT 9 +#define QCA953X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define QCA953X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define QCA953X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define QCA953X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f + +#define QCA953X_PLL_DIT_FRAC_EN BIT(31) + +#define QCA955X_PLL_CPU_CONFIG_REG 0x00 +#define QCA955X_PLL_DDR_CONFIG_REG 0x04 +#define QCA955X_PLL_CLK_CTRL_REG 0x08 +#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28 +#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48 + +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 + +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20) +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21) +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + +#define QCA956X_PLL_CPU_CONFIG_REG 0x00 +#define QCA956X_PLL_CPU_CONFIG1_REG 0x04 +#define QCA956X_PLL_DDR_CONFIG_REG 0x08 +#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c +#define QCA956X_PLL_CLK_CTRL_REG 0x10 + +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 + +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4) +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20) +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21) +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
/* * USB_CONFIG block */ -#define AR71XX_USB_CTRL_REG_FLADJ 0x00 -#define AR71XX_USB_CTRL_REG_CONFIG 0x04 +#define AR71XX_USB_CTRL_REG_FLADJ 0x00 +#define AR71XX_USB_CTRL_REG_CONFIG 0x04
/* * RESET block */ -#define AR71XX_RESET_REG_TIMER 0x00 -#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 -#define AR71XX_RESET_REG_WDOG_CTRL 0x08 -#define AR71XX_RESET_REG_WDOG 0x0c -#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 -#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 -#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 -#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c -#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 -#define AR71XX_RESET_REG_RESET_MODULE 0x24 -#define AR71XX_RESET_REG_PERFC_CTRL 0x2c -#define AR71XX_RESET_REG_PERFC0 0x30 -#define AR71XX_RESET_REG_PERFC1 0x34 -#define AR71XX_RESET_REG_REV_ID 0x90 - -#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 -#define AR913X_RESET_REG_RESET_MODULE 0x1c -#define AR913X_RESET_REG_PERF_CTRL 0x20 -#define AR913X_RESET_REG_PERFC0 0x24 -#define AR913X_RESET_REG_PERFC1 0x28 - -#define AR724X_RESET_REG_RESET_MODULE 0x1c - -#define AR933X_RESET_REG_RESET_MODULE 0x1c -#define AR933X_RESET_REG_BOOTSTRAP 0xac - -#define AR934X_RESET_REG_RESET_MODULE 0x1c -#define AR934X_RESET_REG_BOOTSTRAP 0xb0 -#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -#define QCA953X_RESET_REG_RESET_MODULE 0x1c -#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 -#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac - -#define QCA955X_RESET_REG_RESET_MODULE 0x1c -#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 -#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac - -#define QCA956X_RESET_REG_RESET_MODULE 0x1c -#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 -#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac - -#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) -#define MISC_INT_ETHSW BIT(12) -#define MISC_INT_TIMER4 BIT(10) -#define MISC_INT_TIMER3 BIT(9) -#define MISC_INT_TIMER2 BIT(8) -#define MISC_INT_DMA BIT(7) -#define MISC_INT_OHCI BIT(6) -#define MISC_INT_PERFC BIT(5) -#define MISC_INT_WDOG BIT(4) -#define MISC_INT_UART BIT(3) -#define MISC_INT_GPIO BIT(2) -#define MISC_INT_ERROR BIT(1) -#define MISC_INT_TIMER BIT(0) - -#define AR71XX_RESET_EXTERNAL BIT(28) -#define AR71XX_RESET_FULL_CHIP BIT(24) -#define AR71XX_RESET_CPU_NMI BIT(21) -#define AR71XX_RESET_CPU_COLD BIT(20) -#define AR71XX_RESET_DMA BIT(19) -#define AR71XX_RESET_SLIC BIT(18) -#define AR71XX_RESET_STEREO BIT(17) -#define AR71XX_RESET_DDR BIT(16) -#define AR71XX_RESET_GE1_MAC BIT(13) -#define AR71XX_RESET_GE1_PHY BIT(12) -#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) -#define AR71XX_RESET_GE0_MAC BIT(9) -#define AR71XX_RESET_GE0_PHY BIT(8) -#define AR71XX_RESET_USB_OHCI_DLL BIT(6) -#define AR71XX_RESET_USB_HOST BIT(5) -#define AR71XX_RESET_USB_PHY BIT(4) -#define AR71XX_RESET_PCI_BUS BIT(1) -#define AR71XX_RESET_PCI_CORE BIT(0) - -#define AR7240_RESET_USB_HOST BIT(5) -#define AR7240_RESET_OHCI_DLL BIT(3) - -#define AR724X_RESET_GE1_MDIO BIT(23) -#define AR724X_RESET_GE0_MDIO BIT(22) -#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) -#define AR724X_RESET_PCIE_PHY BIT(7) -#define AR724X_RESET_PCIE BIT(6) -#define AR724X_RESET_USB_HOST BIT(5) -#define AR724X_RESET_USB_PHY BIT(4) -#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) - -#define AR913X_RESET_AMBA2WMAC BIT(22) -#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) -#define AR913X_RESET_USB_HOST BIT(5) -#define AR913X_RESET_USB_PHY BIT(4) - -#define AR933X_RESET_GE1_MDIO BIT(23) -#define AR933X_RESET_GE0_MDIO BIT(22) -#define AR933X_RESET_GE1_MAC BIT(13) -#define AR933X_RESET_WMAC BIT(11) -#define AR933X_RESET_GE0_MAC BIT(9) -#define AR933X_RESET_USB_HOST BIT(5) -#define AR933X_RESET_USB_PHY BIT(4) -#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) - -#define AR934X_RESET_HOST BIT(31) -#define AR934X_RESET_SLIC BIT(30) -#define AR934X_RESET_HDMA BIT(29) -#define AR934X_RESET_EXTERNAL BIT(28) -#define AR934X_RESET_RTC BIT(27) -#define AR934X_RESET_PCIE_EP_INT BIT(26) -#define AR934X_RESET_CHKSUM_ACC BIT(25) -#define AR934X_RESET_FULL_CHIP BIT(24) -#define AR934X_RESET_GE1_MDIO BIT(23) -#define AR934X_RESET_GE0_MDIO BIT(22) -#define AR934X_RESET_CPU_NMI BIT(21) -#define AR934X_RESET_CPU_COLD BIT(20) -#define AR934X_RESET_HOST_RESET_INT BIT(19) -#define AR934X_RESET_PCIE_EP BIT(18) -#define AR934X_RESET_UART1 BIT(17) -#define AR934X_RESET_DDR BIT(16) -#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -#define AR934X_RESET_NANDF BIT(14) -#define AR934X_RESET_GE1_MAC BIT(13) -#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) -#define AR934X_RESET_USB_PHY_ANALOG BIT(11) -#define AR934X_RESET_HOST_DMA_INT BIT(10) -#define AR934X_RESET_GE0_MAC BIT(9) -#define AR934X_RESET_ETH_SWITCH BIT(8) -#define AR934X_RESET_PCIE_PHY BIT(7) -#define AR934X_RESET_PCIE BIT(6) -#define AR934X_RESET_USB_HOST BIT(5) -#define AR934X_RESET_USB_PHY BIT(4) -#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) -#define AR934X_RESET_LUT BIT(2) -#define AR934X_RESET_MBOX BIT(1) -#define AR934X_RESET_I2S BIT(0) - -#define QCA953X_RESET_USB_EXT_PWR BIT(29) -#define QCA953X_RESET_EXTERNAL BIT(28) -#define QCA953X_RESET_RTC BIT(27) -#define QCA953X_RESET_FULL_CHIP BIT(24) -#define QCA953X_RESET_GE1_MDIO BIT(23) -#define QCA953X_RESET_GE0_MDIO BIT(22) -#define QCA953X_RESET_CPU_NMI BIT(21) -#define QCA953X_RESET_CPU_COLD BIT(20) -#define QCA953X_RESET_DDR BIT(16) -#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -#define QCA953X_RESET_GE1_MAC BIT(13) -#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) -#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) -#define QCA953X_RESET_GE0_MAC BIT(9) -#define QCA953X_RESET_ETH_SWITCH BIT(8) -#define QCA953X_RESET_PCIE_PHY BIT(7) -#define QCA953X_RESET_PCIE BIT(6) -#define QCA953X_RESET_USB_HOST BIT(5) -#define QCA953X_RESET_USB_PHY BIT(4) -#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) - -#define QCA955X_RESET_HOST BIT(31) -#define QCA955X_RESET_SLIC BIT(30) -#define QCA955X_RESET_HDMA BIT(29) -#define QCA955X_RESET_EXTERNAL BIT(28) -#define QCA955X_RESET_RTC BIT(27) -#define QCA955X_RESET_PCIE_EP_INT BIT(26) -#define QCA955X_RESET_CHKSUM_ACC BIT(25) -#define QCA955X_RESET_FULL_CHIP BIT(24) -#define QCA955X_RESET_GE1_MDIO BIT(23) -#define QCA955X_RESET_GE0_MDIO BIT(22) -#define QCA955X_RESET_CPU_NMI BIT(21) -#define QCA955X_RESET_CPU_COLD BIT(20) -#define QCA955X_RESET_HOST_RESET_INT BIT(19) -#define QCA955X_RESET_PCIE_EP BIT(18) -#define QCA955X_RESET_UART1 BIT(17) -#define QCA955X_RESET_DDR BIT(16) -#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) -#define QCA955X_RESET_NANDF BIT(14) -#define QCA955X_RESET_GE1_MAC BIT(13) -#define QCA955X_RESET_SGMII_ANALOG BIT(12) -#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) -#define QCA955X_RESET_HOST_DMA_INT BIT(10) -#define QCA955X_RESET_GE0_MAC BIT(9) -#define QCA955X_RESET_SGMII BIT(8) -#define QCA955X_RESET_PCIE_PHY BIT(7) -#define QCA955X_RESET_PCIE BIT(6) -#define QCA955X_RESET_USB_HOST BIT(5) -#define QCA955X_RESET_USB_PHY BIT(4) -#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) -#define QCA955X_RESET_LUT BIT(2) -#define QCA955X_RESET_MBOX BIT(1) -#define QCA955X_RESET_I2S BIT(0) - -#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) -#define AR933X_BOOTSTRAP_DDR2 BIT(13) -#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) -#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) - -#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) -#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) -#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) -#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) -#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) -#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) -#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) -#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) -#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) -#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) -#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) -#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) -#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) -#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -#define AR934X_BOOTSTRAP_DDR1 BIT(0) - -#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) -#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) -#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) -#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) -#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) -#define QCA953X_BOOTSTRAP_DDR1 BIT(0) - -#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) - -#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) - -#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) -#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) -#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define AR71XX_RESET_REG_TIMER 0x00 +#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 +#define AR71XX_RESET_REG_WDOG_CTRL 0x08 +#define AR71XX_RESET_REG_WDOG 0x0c +#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 +#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 +#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 +#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c +#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 +#define AR71XX_RESET_REG_RESET_MODULE 0x24 +#define AR71XX_RESET_REG_PERFC_CTRL 0x2c +#define AR71XX_RESET_REG_PERFC0 0x30 +#define AR71XX_RESET_REG_PERFC1 0x34 +#define AR71XX_RESET_REG_REV_ID 0x90 + +#define AR913X_RESET_REG_GLOBAL_INT_STATUS 0x18 +#define AR913X_RESET_REG_RESET_MODULE 0x1c +#define AR913X_RESET_REG_PERF_CTRL 0x20 +#define AR913X_RESET_REG_PERFC0 0x24 +#define AR913X_RESET_REG_PERFC1 0x28 + +#define AR724X_RESET_REG_RESET_MODULE 0x1c + +#define AR933X_RESET_REG_RESET_MODULE 0x1c +#define AR933X_RESET_REG_BOOTSTRAP 0xac + +#define AR934X_RESET_REG_RESET_MODULE 0x1c +#define AR934X_RESET_REG_BOOTSTRAP 0xb0 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA953X_RESET_REG_RESET_MODULE 0x1c +#define QCA953X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac + +#define QCA955X_RESET_REG_RESET_MODULE 0x1c +#define QCA955X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac + +#define QCA956X_RESET_REG_RESET_MODULE 0x1c +#define QCA956X_RESET_REG_BOOTSTRAP 0xb0 +#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac + +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28) +#define MISC_INT_ETHSW BIT(12) +#define MISC_INT_TIMER4 BIT(10) +#define MISC_INT_TIMER3 BIT(9) +#define MISC_INT_TIMER2 BIT(8) +#define MISC_INT_DMA BIT(7) +#define MISC_INT_OHCI BIT(6) +#define MISC_INT_PERFC BIT(5) +#define MISC_INT_WDOG BIT(4) +#define MISC_INT_UART BIT(3) +#define MISC_INT_GPIO BIT(2) +#define MISC_INT_ERROR BIT(1) +#define MISC_INT_TIMER BIT(0) + +#define AR71XX_RESET_EXTERNAL BIT(28) +#define AR71XX_RESET_FULL_CHIP BIT(24) +#define AR71XX_RESET_CPU_NMI BIT(21) +#define AR71XX_RESET_CPU_COLD BIT(20) +#define AR71XX_RESET_DMA BIT(19) +#define AR71XX_RESET_SLIC BIT(18) +#define AR71XX_RESET_STEREO BIT(17) +#define AR71XX_RESET_DDR BIT(16) +#define AR71XX_RESET_GE1_MAC BIT(13) +#define AR71XX_RESET_GE1_PHY BIT(12) +#define AR71XX_RESET_USBSUS_OVERRIDE BIT(10) +#define AR71XX_RESET_GE0_MAC BIT(9) +#define AR71XX_RESET_GE0_PHY BIT(8) +#define AR71XX_RESET_USB_OHCI_DLL BIT(6) +#define AR71XX_RESET_USB_HOST BIT(5) +#define AR71XX_RESET_USB_PHY BIT(4) +#define AR71XX_RESET_PCI_BUS BIT(1) +#define AR71XX_RESET_PCI_CORE BIT(0) + +#define AR7240_RESET_USB_HOST BIT(5) +#define AR7240_RESET_OHCI_DLL BIT(3) + +#define AR724X_RESET_GE1_MDIO BIT(23) +#define AR724X_RESET_GE0_MDIO BIT(22) +#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) +#define AR724X_RESET_PCIE_PHY BIT(7) +#define AR724X_RESET_PCIE BIT(6) +#define AR724X_RESET_USB_HOST BIT(5) +#define AR724X_RESET_USB_PHY BIT(4) +#define AR724X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR913X_RESET_AMBA2WMAC BIT(22) +#define AR913X_RESET_USBSUS_OVERRIDE BIT(10) +#define AR913X_RESET_USB_HOST BIT(5) +#define AR913X_RESET_USB_PHY BIT(4) + +#define AR933X_RESET_GE1_MDIO BIT(23) +#define AR933X_RESET_GE0_MDIO BIT(22) +#define AR933X_RESET_GE1_MAC BIT(13) +#define AR933X_RESET_WMAC BIT(11) +#define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_USB_HOST BIT(5) +#define AR933X_RESET_USB_PHY BIT(4) +#define AR933X_RESET_USBSUS_OVERRIDE BIT(3) + +#define AR934X_RESET_HOST BIT(31) +#define AR934X_RESET_SLIC BIT(30) +#define AR934X_RESET_HDMA BIT(29) +#define AR934X_RESET_EXTERNAL BIT(28) +#define AR934X_RESET_RTC BIT(27) +#define AR934X_RESET_PCIE_EP_INT BIT(26) +#define AR934X_RESET_CHKSUM_ACC BIT(25) +#define AR934X_RESET_FULL_CHIP BIT(24) +#define AR934X_RESET_GE1_MDIO BIT(23) +#define AR934X_RESET_GE0_MDIO BIT(22) +#define AR934X_RESET_CPU_NMI BIT(21) +#define AR934X_RESET_CPU_COLD BIT(20) +#define AR934X_RESET_HOST_RESET_INT BIT(19) +#define AR934X_RESET_PCIE_EP BIT(18) +#define AR934X_RESET_UART1 BIT(17) +#define AR934X_RESET_DDR BIT(16) +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define AR934X_RESET_NANDF BIT(14) +#define AR934X_RESET_GE1_MAC BIT(13) +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define AR934X_RESET_USB_PHY_ANALOG BIT(11) +#define AR934X_RESET_HOST_DMA_INT BIT(10) +#define AR934X_RESET_GE0_MAC BIT(9) +#define AR934X_RESET_ETH_SWITCH BIT(8) +#define AR934X_RESET_PCIE_PHY BIT(7) +#define AR934X_RESET_PCIE BIT(6) +#define AR934X_RESET_USB_HOST BIT(5) +#define AR934X_RESET_USB_PHY BIT(4) +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3) +#define AR934X_RESET_LUT BIT(2) +#define AR934X_RESET_MBOX BIT(1) +#define AR934X_RESET_I2S BIT(0) + +#define QCA953X_RESET_USB_EXT_PWR BIT(29) +#define QCA953X_RESET_EXTERNAL BIT(28) +#define QCA953X_RESET_RTC BIT(27) +#define QCA953X_RESET_FULL_CHIP BIT(24) +#define QCA953X_RESET_GE1_MDIO BIT(23) +#define QCA953X_RESET_GE0_MDIO BIT(22) +#define QCA953X_RESET_CPU_NMI BIT(21) +#define QCA953X_RESET_CPU_COLD BIT(20) +#define QCA953X_RESET_DDR BIT(16) +#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA953X_RESET_GE1_MAC BIT(13) +#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12) +#define QCA953X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA953X_RESET_GE0_MAC BIT(9) +#define QCA953X_RESET_ETH_SWITCH BIT(8) +#define QCA953X_RESET_PCIE_PHY BIT(7) +#define QCA953X_RESET_PCIE BIT(6) +#define QCA953X_RESET_USB_HOST BIT(5) +#define QCA953X_RESET_USB_PHY BIT(4) +#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3) + +#define QCA955X_RESET_HOST BIT(31) +#define QCA955X_RESET_SLIC BIT(30) +#define QCA955X_RESET_HDMA BIT(29) +#define QCA955X_RESET_EXTERNAL BIT(28) +#define QCA955X_RESET_RTC BIT(27) +#define QCA955X_RESET_PCIE_EP_INT BIT(26) +#define QCA955X_RESET_CHKSUM_ACC BIT(25) +#define QCA955X_RESET_FULL_CHIP BIT(24) +#define QCA955X_RESET_GE1_MDIO BIT(23) +#define QCA955X_RESET_GE0_MDIO BIT(22) +#define QCA955X_RESET_CPU_NMI BIT(21) +#define QCA955X_RESET_CPU_COLD BIT(20) +#define QCA955X_RESET_HOST_RESET_INT BIT(19) +#define QCA955X_RESET_PCIE_EP BIT(18) +#define QCA955X_RESET_UART1 BIT(17) +#define QCA955X_RESET_DDR BIT(16) +#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15) +#define QCA955X_RESET_NANDF BIT(14) +#define QCA955X_RESET_GE1_MAC BIT(13) +#define QCA955X_RESET_SGMII_ANALOG BIT(12) +#define QCA955X_RESET_USB_PHY_ANALOG BIT(11) +#define QCA955X_RESET_HOST_DMA_INT BIT(10) +#define QCA955X_RESET_GE0_MAC BIT(9) +#define QCA955X_RESET_SGMII BIT(8) +#define QCA955X_RESET_PCIE_PHY BIT(7) +#define QCA955X_RESET_PCIE BIT(6) +#define QCA955X_RESET_USB_HOST BIT(5) +#define QCA955X_RESET_USB_PHY BIT(4) +#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3) +#define QCA955X_RESET_LUT BIT(2) +#define QCA955X_RESET_MBOX BIT(1) +#define QCA955X_RESET_I2S BIT(0) + +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18) +#define AR933X_BOOTSTRAP_DDR2 BIT(13) +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4) +#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0) + +#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23) +#define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22) +#define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21) +#define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20) +#define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19) +#define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18) +#define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17) +#define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16) +#define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7) +#define AR934X_BOOTSTRAP_PCIE_RC BIT(6) +#define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2) +#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define AR934X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12) +#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11) +#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5) +#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4) +#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1) +#define QCA953X_BOOTSTRAP_DDR1 BIT(0) + +#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4) + +#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2) + +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) #define AR934X_PCIE_WMAC_INT_WMAC_ALL \ (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \ AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP) @@ -728,15 +763,15 @@ AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \ AR934X_PCIE_WMAC_INT_PCIE_RC3)
-#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) -#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) -#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) -#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) -#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) +#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0) +#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2) +#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7) +#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8) #define QCA953X_PCIE_WMAC_INT_WMAC_ALL \ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP) @@ -746,22 +781,22 @@ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
-#define QCA955X_EXT_INT_WMAC_MISC BIT(0) -#define QCA955X_EXT_INT_WMAC_TX BIT(1) -#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) -#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) -#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) -#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) -#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) -#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) -#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) -#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) -#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) -#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) -#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) -#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) -#define QCA955X_EXT_INT_USB1 BIT(24) -#define QCA955X_EXT_INT_USB2 BIT(28) +#define QCA955X_EXT_INT_WMAC_MISC BIT(0) +#define QCA955X_EXT_INT_WMAC_TX BIT(1) +#define QCA955X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA955X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA955X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA955X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA955X_EXT_INT_USB1 BIT(24) +#define QCA955X_EXT_INT_USB2 BIT(28)
#define QCA955X_EXT_INT_WMAC_ALL \ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \ @@ -777,22 +812,22 @@ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \ QCA955X_EXT_INT_PCIE_RC2_INT3)
-#define QCA956X_EXT_INT_WMAC_MISC BIT(0) -#define QCA956X_EXT_INT_WMAC_TX BIT(1) -#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) -#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) -#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) -#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) -#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) -#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) -#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) -#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) -#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) -#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) -#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) -#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) -#define QCA956X_EXT_INT_USB1 BIT(24) -#define QCA956X_EXT_INT_USB2 BIT(28) +#define QCA956X_EXT_INT_WMAC_MISC BIT(0) +#define QCA956X_EXT_INT_WMAC_TX BIT(1) +#define QCA956X_EXT_INT_WMAC_RXLP BIT(2) +#define QCA956X_EXT_INT_WMAC_RXHP BIT(3) +#define QCA956X_EXT_INT_PCIE_RC1 BIT(4) +#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5) +#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6) +#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7) +#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8) +#define QCA956X_EXT_INT_PCIE_RC2 BIT(12) +#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13) +#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14) +#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15) +#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16) +#define QCA956X_EXT_INT_USB1 BIT(24) +#define QCA956X_EXT_INT_USB2 BIT(28)
#define QCA956X_EXT_INT_WMAC_ALL \ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \ @@ -808,377 +843,377 @@ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \ QCA956X_EXT_INT_PCIE_RC2_INT3)
-#define REV_ID_MAJOR_MASK 0xfff0 -#define REV_ID_MAJOR_AR71XX 0x00a0 -#define REV_ID_MAJOR_AR913X 0x00b0 -#define REV_ID_MAJOR_AR7240 0x00c0 -#define REV_ID_MAJOR_AR7241 0x0100 -#define REV_ID_MAJOR_AR7242 0x1100 -#define REV_ID_MAJOR_AR9330 0x0110 -#define REV_ID_MAJOR_AR9331 0x1110 -#define REV_ID_MAJOR_AR9341 0x0120 -#define REV_ID_MAJOR_AR9342 0x1120 -#define REV_ID_MAJOR_AR9344 0x2120 -#define REV_ID_MAJOR_QCA9533 0x0140 -#define REV_ID_MAJOR_QCA9533_V2 0x0160 -#define REV_ID_MAJOR_QCA9556 0x0130 -#define REV_ID_MAJOR_QCA9558 0x1130 -#define REV_ID_MAJOR_TP9343 0x0150 -#define REV_ID_MAJOR_QCA9561 0x1150 - -#define AR71XX_REV_ID_MINOR_MASK 0x3 -#define AR71XX_REV_ID_MINOR_AR7130 0x0 -#define AR71XX_REV_ID_MINOR_AR7141 0x1 -#define AR71XX_REV_ID_MINOR_AR7161 0x2 -#define AR913X_REV_ID_MINOR_AR9130 0x0 -#define AR913X_REV_ID_MINOR_AR9132 0x1 - -#define AR71XX_REV_ID_REVISION_MASK 0x3 -#define AR71XX_REV_ID_REVISION_SHIFT 2 -#define AR71XX_REV_ID_REVISION2_MASK 0xf +#define REV_ID_MAJOR_MASK 0xfff0 +#define REV_ID_MAJOR_AR71XX 0x00a0 +#define REV_ID_MAJOR_AR913X 0x00b0 +#define REV_ID_MAJOR_AR7240 0x00c0 +#define REV_ID_MAJOR_AR7241 0x0100 +#define REV_ID_MAJOR_AR7242 0x1100 +#define REV_ID_MAJOR_AR9330 0x0110 +#define REV_ID_MAJOR_AR9331 0x1110 +#define REV_ID_MAJOR_AR9341 0x0120 +#define REV_ID_MAJOR_AR9342 0x1120 +#define REV_ID_MAJOR_AR9344 0x2120 +#define REV_ID_MAJOR_QCA9533 0x0140 +#define REV_ID_MAJOR_QCA9533_V2 0x0160 +#define REV_ID_MAJOR_QCA9556 0x0130 +#define REV_ID_MAJOR_QCA9558 0x1130 +#define REV_ID_MAJOR_TP9343 0x0150 +#define REV_ID_MAJOR_QCA9561 0x1150 + +#define AR71XX_REV_ID_MINOR_MASK 0x3 +#define AR71XX_REV_ID_MINOR_AR7130 0x0 +#define AR71XX_REV_ID_MINOR_AR7141 0x1 +#define AR71XX_REV_ID_MINOR_AR7161 0x2 +#define AR913X_REV_ID_MINOR_AR9130 0x0 +#define AR913X_REV_ID_MINOR_AR9132 0x1 + +#define AR71XX_REV_ID_REVISION_MASK 0x3 +#define AR71XX_REV_ID_REVISION_SHIFT 2 +#define AR71XX_REV_ID_REVISION2_MASK 0xf
/* * RTC block */ -#define AR933X_RTC_REG_RESET 0x40 -#define AR933X_RTC_REG_STATUS 0x44 -#define AR933X_RTC_REG_DERIVED 0x48 -#define AR933X_RTC_REG_FORCE_WAKE 0x4c -#define AR933X_RTC_REG_INT_CAUSE 0x50 -#define AR933X_RTC_REG_CAUSE_CLR 0x50 -#define AR933X_RTC_REG_INT_ENABLE 0x54 -#define AR933X_RTC_REG_INT_MASKE 0x58 - -#define QCA953X_RTC_REG_SYNC_RESET 0x40 -#define QCA953X_RTC_REG_SYNC_STATUS 0x44 +#define AR933X_RTC_REG_RESET 0x40 +#define AR933X_RTC_REG_STATUS 0x44 +#define AR933X_RTC_REG_DERIVED 0x48 +#define AR933X_RTC_REG_FORCE_WAKE 0x4c +#define AR933X_RTC_REG_INT_CAUSE 0x50 +#define AR933X_RTC_REG_CAUSE_CLR 0x50 +#define AR933X_RTC_REG_INT_ENABLE 0x54 +#define AR933X_RTC_REG_INT_MASKE 0x58 + +#define QCA953X_RTC_REG_SYNC_RESET 0x40 +#define QCA953X_RTC_REG_SYNC_STATUS 0x44
/* * SPI block */ -#define AR71XX_SPI_REG_FS 0x00 -#define AR71XX_SPI_REG_CTRL 0x04 -#define AR71XX_SPI_REG_IOC 0x08 -#define AR71XX_SPI_REG_RDS 0x0c - -#define AR71XX_SPI_FS_GPIO BIT(0) - -#define AR71XX_SPI_CTRL_RD BIT(6) -#define AR71XX_SPI_CTRL_DIV_MASK 0x3f - -#define AR71XX_SPI_IOC_DO BIT(0) -#define AR71XX_SPI_IOC_CLK BIT(8) -#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) -#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) -#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) -#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) +#define AR71XX_SPI_REG_FS 0x00 +#define AR71XX_SPI_REG_CTRL 0x04 +#define AR71XX_SPI_REG_IOC 0x08 +#define AR71XX_SPI_REG_RDS 0x0c + +#define AR71XX_SPI_FS_GPIO BIT(0) + +#define AR71XX_SPI_CTRL_RD BIT(6) +#define AR71XX_SPI_CTRL_DIV_MASK 0x3f + +#define AR71XX_SPI_IOC_DO BIT(0) +#define AR71XX_SPI_IOC_CLK BIT(8) +#define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) +#define AR71XX_SPI_IOC_CS0 AR71XX_SPI_IOC_CS(0) +#define AR71XX_SPI_IOC_CS1 AR71XX_SPI_IOC_CS(1) +#define AR71XX_SPI_IOC_CS2 AR71XX_SPI_IOC_CS(2) #define AR71XX_SPI_IOC_CS_ALL \ (AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1 | AR71XX_SPI_IOC_CS2)
/* * GPIO block */ -#define AR71XX_GPIO_REG_OE 0x00 -#define AR71XX_GPIO_REG_IN 0x04 -#define AR71XX_GPIO_REG_OUT 0x08 -#define AR71XX_GPIO_REG_SET 0x0c -#define AR71XX_GPIO_REG_CLEAR 0x10 -#define AR71XX_GPIO_REG_INT_MODE 0x14 -#define AR71XX_GPIO_REG_INT_TYPE 0x18 -#define AR71XX_GPIO_REG_INT_POLARITY 0x1c -#define AR71XX_GPIO_REG_INT_PENDING 0x20 -#define AR71XX_GPIO_REG_INT_ENABLE 0x24 -#define AR71XX_GPIO_REG_FUNC 0x28 -#define AR933X_GPIO_REG_FUNC 0x30 - -#define AR934X_GPIO_REG_OUT_FUNC0 0x2c -#define AR934X_GPIO_REG_OUT_FUNC1 0x30 -#define AR934X_GPIO_REG_OUT_FUNC2 0x34 -#define AR934X_GPIO_REG_OUT_FUNC3 0x38 -#define AR934X_GPIO_REG_OUT_FUNC4 0x3c -#define AR934X_GPIO_REG_OUT_FUNC5 0x40 -#define AR934X_GPIO_REG_FUNC 0x6c - -#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c -#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 -#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 -#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 -#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c -#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 -#define QCA953X_GPIO_REG_FUNC 0x6c - -#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c -#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 -#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 -#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 -#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c -#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 -#define QCA955X_GPIO_REG_FUNC 0x6c - -#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c -#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 -#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 -#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 -#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c -#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 -#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 -#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 -#define QCA956X_GPIO_REG_FUNC 0x6c - -#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) - -#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -#define AR724X_GPIO_FUNC_UART_EN BIT(1) -#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) - -#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) -#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) -#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) -#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) -#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) -#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) -#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -#define AR913X_GPIO_FUNC_UART_EN BIT(8) -#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) - -#define AR933X_GPIO(x) BIT(x) -#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) -#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) -#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) -#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) -#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) -#define AR933X_GPIO_FUNC_SPI_EN BIT(18) -#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) -#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -#define AR933X_GPIO_FUNC_UART_EN BIT(1) -#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) - -#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) -#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) -#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) -#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) -#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) -#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) -#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) -#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) -#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) - -#define AR934X_GPIO_OUT_GPIO 0 -#define AR934X_GPIO_OUT_SPI_CS1 7 -#define AR934X_GPIO_OUT_LED_LINK0 41 -#define AR934X_GPIO_OUT_LED_LINK1 42 -#define AR934X_GPIO_OUT_LED_LINK2 43 -#define AR934X_GPIO_OUT_LED_LINK3 44 -#define AR934X_GPIO_OUT_LED_LINK4 45 -#define AR934X_GPIO_OUT_EXT_LNA0 46 -#define AR934X_GPIO_OUT_EXT_LNA1 47 - -#define QCA953X_GPIO(x) BIT(x) -#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) -#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 -#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 -#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 -#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 -#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 -#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 -#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 -#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 -#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 -#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 -#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 - -#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 -#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 - -#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 -#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 - -#define AR71XX_GPIO_COUNT 16 -#define AR7240_GPIO_COUNT 18 -#define AR7241_GPIO_COUNT 20 -#define AR913X_GPIO_COUNT 22 -#define AR933X_GPIO_COUNT 30 -#define AR934X_GPIO_COUNT 23 -#define QCA953X_GPIO_COUNT 18 -#define QCA955X_GPIO_COUNT 24 -#define QCA956X_GPIO_COUNT 23 +#define AR71XX_GPIO_REG_OE 0x00 +#define AR71XX_GPIO_REG_IN 0x04 +#define AR71XX_GPIO_REG_OUT 0x08 +#define AR71XX_GPIO_REG_SET 0x0c +#define AR71XX_GPIO_REG_CLEAR 0x10 +#define AR71XX_GPIO_REG_INT_MODE 0x14 +#define AR71XX_GPIO_REG_INT_TYPE 0x18 +#define AR71XX_GPIO_REG_INT_POLARITY 0x1c +#define AR71XX_GPIO_REG_INT_PENDING 0x20 +#define AR71XX_GPIO_REG_INT_ENABLE 0x24 +#define AR71XX_GPIO_REG_FUNC 0x28 +#define AR933X_GPIO_REG_FUNC 0x30 + +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c +#define AR934X_GPIO_REG_OUT_FUNC1 0x30 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c +#define AR934X_GPIO_REG_OUT_FUNC5 0x40 +#define AR934X_GPIO_REG_FUNC 0x6c + +#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA953X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA953X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA953X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA953X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA953X_GPIO_REG_FUNC 0x6c + +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c + +#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA956X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA956X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA956X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA956X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA956X_GPIO_REG_IN_ENABLE0 0x44 +#define QCA956X_GPIO_REG_IN_ENABLE3 0x50 +#define QCA956X_GPIO_REG_FUNC 0x6c + +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) +#define AR71XX_GPIO_FUNC_UART_EN BIT(8) +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) +#define AR724X_GPIO_FUNC_SPI_EN BIT(18) +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR724X_GPIO_FUNC_UART_EN BIT(1) +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22) +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20) +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19) +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18) +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17) +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16) +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9) +#define AR913X_GPIO_FUNC_UART_EN BIT(8) +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4) + +#define AR933X_GPIO(x) BIT(x) +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31) +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30) +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29) +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27) +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23) +#define AR933X_GPIO_FUNC_SPI_EN BIT(18) +#define AR933X_GPIO_FUNC_RES_TRUE BIT(15) +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14) +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13) +#define AR933X_GPIO_FUNC_XLNA_EN BIT(12) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) +#define AR933X_GPIO_FUNC_UART_EN BIT(1) +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0) + +#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9) +#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8) +#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7) +#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6) +#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5) +#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4) +#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3) +#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2) +#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1) + +#define AR934X_GPIO_OUT_GPIO 0 +#define AR934X_GPIO_OUT_SPI_CS1 7 +#define AR934X_GPIO_OUT_LED_LINK0 41 +#define AR934X_GPIO_OUT_LED_LINK1 42 +#define AR934X_GPIO_OUT_LED_LINK2 43 +#define AR934X_GPIO_OUT_LED_LINK3 44 +#define AR934X_GPIO_OUT_LED_LINK4 45 +#define AR934X_GPIO_OUT_EXT_LNA0 46 +#define AR934X_GPIO_OUT_EXT_LNA1 47 + +#define QCA953X_GPIO(x) BIT(x) +#define QCA953X_GPIO_MUX_MASK(x) (0xff << (x)) +#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10 +#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11 +#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9 +#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8 +#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12 +#define QCA953X_GPIO_OUT_MUX_UART0_SOUT 22 +#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41 +#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42 +#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43 +#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44 +#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45 + +#define QCA953X_GPIO_IN_MUX_UART0_SIN 9 +#define QCA953X_GPIO_IN_MUX_SPI_DATA_IN 8 + +#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33 + +#define AR71XX_GPIO_COUNT 16 +#define AR7240_GPIO_COUNT 18 +#define AR7241_GPIO_COUNT 20 +#define AR913X_GPIO_COUNT 22 +#define AR933X_GPIO_COUNT 30 +#define AR934X_GPIO_COUNT 23 +#define QCA953X_GPIO_COUNT 18 +#define QCA955X_GPIO_COUNT 24 +#define QCA956X_GPIO_COUNT 23
/* * SRIF block */ -#define AR933X_SRIF_DDR_DPLL1_REG 0x240 -#define AR933X_SRIF_DDR_DPLL2_REG 0x244 -#define AR933X_SRIF_DDR_DPLL3_REG 0x248 -#define AR933X_SRIF_DDR_DPLL4_REG 0x24c +#define AR933X_SRIF_DDR_DPLL1_REG 0x240 +#define AR933X_SRIF_DDR_DPLL2_REG 0x244 +#define AR933X_SRIF_DDR_DPLL3_REG 0x248 +#define AR933X_SRIF_DDR_DPLL4_REG 0x24c
-#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 -#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 -#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 +#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 +#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 +#define AR934X_SRIF_CPU_DPLL3_REG 0x1c8
-#define AR934X_SRIF_DDR_DPLL1_REG 0x240 -#define AR934X_SRIF_DDR_DPLL2_REG 0x244 -#define AR934X_SRIF_DDR_DPLL3_REG 0x248 +#define AR934X_SRIF_DDR_DPLL1_REG 0x240 +#define AR934X_SRIF_DDR_DPLL2_REG 0x244 +#define AR934X_SRIF_DDR_DPLL3_REG 0x248
-#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 -#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f -#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 -#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff -#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff +#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define AR934X_SRIF_DPLL1_NINT_SHIFT 18 +#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff +#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
-#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) -#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 -#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7 +#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
-#define QCA953X_SRIF_BB_DPLL1_REG 0x180 -#define QCA953X_SRIF_BB_DPLL2_REG 0x184 -#define QCA953X_SRIF_BB_DPLL3_REG 0x188 +#define QCA953X_SRIF_BB_DPLL1_REG 0x180 +#define QCA953X_SRIF_BB_DPLL2_REG 0x184 +#define QCA953X_SRIF_BB_DPLL3_REG 0x188
-#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 -#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 -#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8 +#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0 +#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4 +#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
-#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 -#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 -#define QCA953X_SRIF_DDR_DPLL3_REG 0x248 +#define QCA953X_SRIF_DDR_DPLL1_REG 0x240 +#define QCA953X_SRIF_DDR_DPLL2_REG 0x244 +#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
-#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 -#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 -#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08 +#define QCA953X_SRIF_PCIE_DPLL1_REG 0xc00 +#define QCA953X_SRIF_PCIE_DPLL2_REG 0xc04 +#define QCA953X_SRIF_PCIE_DPLL3_REG 0xc08
-#define QCA953X_SRIF_PMU1_REG 0xc40 -#define QCA953X_SRIF_PMU2_REG 0xc44 +#define QCA953X_SRIF_PMU1_REG 0xc40 +#define QCA953X_SRIF_PMU2_REG 0xc44
-#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 -#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f +#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27 +#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
-#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 -#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff -#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff +#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18 +#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff +#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
-#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30) +#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
-#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 -#define QCA953X_SRIF_DPLL2_KI_MASK 0x3 +#define QCA953X_SRIF_DPLL2_KI_SHIFT 29 +#define QCA953X_SRIF_DPLL2_KI_MASK 0x3
-#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 -#define QCA953X_SRIF_DPLL2_KD_MASK 0xf +#define QCA953X_SRIF_DPLL2_KD_SHIFT 25 +#define QCA953X_SRIF_DPLL2_KD_MASK 0xf
-#define QCA953X_SRIF_DPLL2_PWD BIT(22) +#define QCA953X_SRIF_DPLL2_PWD BIT(22)
-#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 -#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7 +#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13 +#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
/* * MII_CTRL block */ -#define AR71XX_MII_REG_MII0_CTRL 0x00 -#define AR71XX_MII_REG_MII1_CTRL 0x04 +#define AR71XX_MII_REG_MII0_CTRL 0x00 +#define AR71XX_MII_REG_MII1_CTRL 0x04
-#define AR71XX_MII_CTRL_IF_MASK 3 -#define AR71XX_MII_CTRL_SPEED_SHIFT 4 -#define AR71XX_MII_CTRL_SPEED_MASK 3 -#define AR71XX_MII_CTRL_SPEED_10 0 -#define AR71XX_MII_CTRL_SPEED_100 1 -#define AR71XX_MII_CTRL_SPEED_1000 2 +#define AR71XX_MII_CTRL_IF_MASK 3 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4 +#define AR71XX_MII_CTRL_SPEED_MASK 3 +#define AR71XX_MII_CTRL_SPEED_10 0 +#define AR71XX_MII_CTRL_SPEED_100 1 +#define AR71XX_MII_CTRL_SPEED_1000 2
-#define AR71XX_MII0_CTRL_IF_GMII 0 -#define AR71XX_MII0_CTRL_IF_MII 1 -#define AR71XX_MII0_CTRL_IF_RGMII 2 -#define AR71XX_MII0_CTRL_IF_RMII 3 +#define AR71XX_MII0_CTRL_IF_GMII 0 +#define AR71XX_MII0_CTRL_IF_MII 1 +#define AR71XX_MII0_CTRL_IF_RGMII 2 +#define AR71XX_MII0_CTRL_IF_RMII 3
-#define AR71XX_MII1_CTRL_IF_RGMII 0 -#define AR71XX_MII1_CTRL_IF_RMII 1 +#define AR71XX_MII1_CTRL_IF_RGMII 0 +#define AR71XX_MII1_CTRL_IF_RMII 1
/* * AR933X GMAC interface */ -#define AR933X_GMAC_REG_ETH_CFG 0x00 - -#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) -#define AR933X_ETH_CFG_MII_GE0 BIT(1) -#define AR933X_ETH_CFG_GMII_GE0 BIT(2) -#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) -#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) -#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) -#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) -#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) -#define AR933X_ETH_CFG_RMII_GE0 BIT(9) -#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 -#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10) +#define AR933X_GMAC_REG_ETH_CFG 0x00 + +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0) +#define AR933X_ETH_CFG_MII_GE0 BIT(1) +#define AR933X_ETH_CFG_GMII_GE0 BIT(2) +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3) +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4) +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5) +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8) +#define AR933X_ETH_CFG_RMII_GE0 BIT(9) +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
/* * AR934X GMAC Interface */ -#define AR934X_GMAC_REG_ETH_CFG 0x00 - -#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) -#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) -#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) -#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) -#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) -#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) -#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) -#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) -#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) -#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) -#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) -#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) -#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) -#define AR934X_ETH_CFG_RXD_DELAY BIT(14) -#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 -#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 -#define AR934X_ETH_CFG_RDV_DELAY BIT(16) -#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 -#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16 +#define AR934X_GMAC_REG_ETH_CFG 0x00 + +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0) +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1) +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2) +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3) +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4) +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5) +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10) +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11) +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12) +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define AR934X_ETH_CFG_RXD_DELAY BIT(14) +#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14 +#define AR934X_ETH_CFG_RDV_DELAY BIT(16) +#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3 +#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
/* * QCA953X GMAC Interface */ -#define QCA953X_GMAC_REG_ETH_CFG 0x00 +#define QCA953X_GMAC_REG_ETH_CFG 0x00
-#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) -#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) -#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) -#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13) +#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6) +#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7) +#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9) +#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
/* * QCA955X GMAC Interface */
-#define QCA955X_GMAC_REG_ETH_CFG 0x00 +#define QCA955X_GMAC_REG_ETH_CFG 0x00
-#define QCA955X_ETH_CFG_RGMII_EN BIT(0) -#define QCA955X_ETH_CFG_GE0_SGMII BIT(6) +#define QCA955X_ETH_CFG_RGMII_EN BIT(0) +#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
#endif /* __ASM_AR71XX_H */
The assignment const T var; var = value; is illegal, since var is constant. Drop the const to fix the compiler warning.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/mach-ath79/reset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index 2ea2f8d..ba38609 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -46,7 +46,7 @@ void _machine_restart(void)
u32 get_bootstrap(void) { - const void __iomem *base; + void __iomem *base; u32 reg = 0;
base = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
Add generic EHCI node for the ChipIdea EHCI controller in the ath79.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/dts/ar933x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi index 11f60a2..2e124a4 100644 --- a/arch/mips/dts/ar933x.dtsi +++ b/arch/mips/dts/ar933x.dtsi @@ -59,6 +59,13 @@ #address-cells = <1>; #size-cells = <1>;
+ ehci0: ehci@1b000100 { + compatible = "generic-ehci"; + reg = <0x1b000100 0x100>; + + status = "disabled"; + }; + uart0: uart@18020000 { compatible = "qca,ar9330-uart"; reg = <0x18020000 0x20>;
Add code to ungate the USB controller on ar933x and ar934x .
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/mach-ath79/include/mach/ath79.h | 2 + arch/mips/mach-ath79/reset.c | 61 +++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 90d80b8..682b6a2 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -140,4 +140,6 @@ static inline int soc_is_qca956x(void) return soc_is_tp9343() || soc_is_qca9561(); }
+int ath79_usb_reset(void); + #endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index ba38609..bf4bc3b 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -5,6 +5,7 @@ */
#include <common.h> +#include <asm/errno.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> @@ -69,3 +70,63 @@ u32 get_bootstrap(void)
return 0; } + +static int usb_reset_ar933x(void __iomem *reset_regs) +{ + /* Ungate the USB block */ + setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, + AR933X_RESET_USBSUS_OVERRIDE); + mdelay(1); + clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, + AR933X_RESET_USB_HOST); + mdelay(1); + clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE, + AR933X_RESET_USB_PHY); + mdelay(1); + + return 0; +} + +static int usb_reset_ar934x(void __iomem *reset_regs) +{ + /* Ungate the USB block */ + setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USBSUS_OVERRIDE); + mdelay(1); + clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USB_PHY); + mdelay(1); + clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USB_PHY_ANALOG); + mdelay(1); + clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE, + AR934X_RESET_USB_HOST); + mdelay(1); + + return 0; +} + +int ath79_usb_reset(void) +{ + void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE, + AR71XX_USB_CTRL_SIZE, MAP_NOCACHE); + void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, MAP_NOCACHE); + + if (!usbc_regs || !reset_regs) + return -EINVAL; + + /* + * Turn on the Buff and Desc swap bits. + * NOTE: This write into an undocumented register in mandatory to + * get the USB controller operational in BigEndian mode. + */ + writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG); + + if (soc_is_ar933x()) + return usb_reset_ar933x(reset_regs); + if (soc_is_ar934x()) + return usb_reset_ar934x(reset_regs); + + return -EINVAL; +}
Am 05.05.2016 um 20:14 schrieb Marek Vasut:
Add code to ungate the USB controller on ar933x and ar934x .
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com
arch/mips/mach-ath79/include/mach/ath79.h | 2 + arch/mips/mach-ath79/reset.c | 61 +++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
there are checkpatch.pl warnings:
warning: arch/mips/mach-ath79/reset.c,112: line over 80 characters
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 90d80b8..682b6a2 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -140,4 +140,6 @@ static inline int soc_is_qca956x(void) return soc_is_tp9343() || soc_is_qca9561(); }
+int ath79_usb_reset(void);
#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index ba38609..bf4bc3b 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -5,6 +5,7 @@ */
#include <common.h> +#include <asm/errno.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> @@ -69,3 +70,63 @@ u32 get_bootstrap(void)
return 0; }
+static int usb_reset_ar933x(void __iomem *reset_regs) +{
- /* Ungate the USB block */
- setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
AR933X_RESET_USBSUS_OVERRIDE);- mdelay(1);
- clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
AR933X_RESET_USB_HOST);- mdelay(1);
- clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
AR933X_RESET_USB_PHY);- mdelay(1);
- return 0;
+}
+static int usb_reset_ar934x(void __iomem *reset_regs) +{
- /* Ungate the USB block */
- setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USBSUS_OVERRIDE);- mdelay(1);
- clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USB_PHY);- mdelay(1);
- clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USB_PHY_ANALOG);- mdelay(1);
- clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USB_HOST);- mdelay(1);
- return 0;
+}
+int ath79_usb_reset(void) +{
- void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
AR71XX_USB_CTRL_SIZE, MAP_NOCACHE);- void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE, MAP_NOCACHE);- if (!usbc_regs || !reset_regs)
return -EINVAL;
those checks are not necessary
- /*
* Turn on the Buff and Desc swap bits.* NOTE: This write into an undocumented register in mandatory to* get the USB controller operational in BigEndian mode.*/- writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
- if (soc_is_ar933x())
return usb_reset_ar933x(reset_regs);- if (soc_is_ar934x())
return usb_reset_ar934x(reset_regs);- return -EINVAL;
+}
On 05/06/2016 01:34 PM, Daniel Schwierzeck wrote:
Am 05.05.2016 um 20:14 schrieb Marek Vasut:
Add code to ungate the USB controller on ar933x and ar934x .
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com
arch/mips/mach-ath79/include/mach/ath79.h | 2 + arch/mips/mach-ath79/reset.c | 61 +++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)
there are checkpatch.pl warnings:
warning: arch/mips/mach-ath79/reset.c,112: line over 80 characters
Hm ok, off-by-one character error. Fixed.
diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 90d80b8..682b6a2 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -140,4 +140,6 @@ static inline int soc_is_qca956x(void) return soc_is_tp9343() || soc_is_qca9561(); }
+int ath79_usb_reset(void);
#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index ba38609..bf4bc3b 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -5,6 +5,7 @@ */
#include <common.h> +#include <asm/errno.h> #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> @@ -69,3 +70,63 @@ u32 get_bootstrap(void)
return 0; }
+static int usb_reset_ar933x(void __iomem *reset_regs) +{
- /* Ungate the USB block */
- setbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
AR933X_RESET_USBSUS_OVERRIDE);- mdelay(1);
- clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
AR933X_RESET_USB_HOST);- mdelay(1);
- clrbits_be32(reset_regs + AR933X_RESET_REG_RESET_MODULE,
AR933X_RESET_USB_PHY);- mdelay(1);
- return 0;
+}
+static int usb_reset_ar934x(void __iomem *reset_regs) +{
- /* Ungate the USB block */
- setbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USBSUS_OVERRIDE);- mdelay(1);
- clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USB_PHY);- mdelay(1);
- clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USB_PHY_ANALOG);- mdelay(1);
- clrbits_be32(reset_regs + AR934X_RESET_REG_RESET_MODULE,
AR934X_RESET_USB_HOST);- mdelay(1);
- return 0;
+}
+int ath79_usb_reset(void) +{
- void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
AR71XX_USB_CTRL_SIZE, MAP_NOCACHE);- void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE, MAP_NOCACHE);- if (!usbc_regs || !reset_regs)
return -EINVAL;those checks are not necessary
OK, dropped.
- /*
* Turn on the Buff and Desc swap bits.* NOTE: This write into an undocumented register in mandatory to* get the USB controller operational in BigEndian mode.*/- writel(0xf0000, usbc_regs + AR71XX_USB_CTRL_REG_CONFIG);
- if (soc_is_ar933x())
return usb_reset_ar933x(reset_regs);- if (soc_is_ar934x())
return usb_reset_ar934x(reset_regs);- return -EINVAL;
+}
Add nodes for both ethernet controllers in the ath79 MIPS.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/dts/ar933x.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/mips/dts/ar933x.dtsi b/arch/mips/dts/ar933x.dtsi index 2e124a4..f86f4a9 100644 --- a/arch/mips/dts/ar933x.dtsi +++ b/arch/mips/dts/ar933x.dtsi @@ -73,6 +73,22 @@
status = "disabled"; }; + + gmac0: eth@0x19000000 { + compatible = "qca,ag7240-mac"; + reg = <0x19000000 0x200>; + phy-mode = "rmii"; + + status = "disabled"; + }; + + gmac1: eth@0x1a000000 { + compatible = "qca,ag7240-mac"; + reg = <0x1a000000 0x200>; + phy-mode = "rgmii"; + + status = "disabled"; + }; };
spi0: spi@1f000000 {
Add code to ungate the ethernet controller on ar933x and ar934x .
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 + arch/mips/mach-ath79/include/mach/ath79.h | 1 + arch/mips/mach-ath79/reset.c | 84 +++++++++++++++++++++++++ 3 files changed, 86 insertions(+)
diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index bff9d05..a9630c0 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -622,6 +622,7 @@ #define AR933X_RESET_GE1_MAC BIT(13) #define AR933X_RESET_WMAC BIT(11) #define AR933X_RESET_GE0_MAC BIT(9) +#define AR933X_RESET_ETH_SWITCH BIT(8) #define AR933X_RESET_USB_HOST BIT(5) #define AR933X_RESET_USB_PHY BIT(4) #define AR933X_RESET_USBSUS_OVERRIDE BIT(3) diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 682b6a2..2c6c118 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -140,6 +140,7 @@ static inline int soc_is_qca956x(void) return soc_is_tp9343() || soc_is_qca9561(); }
+int ath79_eth_reset(void); int ath79_usb_reset(void);
#endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index bf4bc3b..e2daf4d 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -71,6 +71,90 @@ u32 get_bootstrap(void) return 0; }
+static int eth_init_ar933x(void) +{ + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + void __iomem *gregs = map_physmem(AR933X_GMAC_BASE, AR933X_GMAC_SIZE, + MAP_NOCACHE); + const u32 mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | + AR933X_RESET_GE1_MAC | AR933X_RESET_GE1_MDIO | + AR933X_RESET_ETH_SWITCH; + + if (!rregs || !pregs || !gregs) + return -EINVAL; + + /* Clear MDIO slave EN bit. */ + clrbits_be32(rregs + AR933X_RESET_REG_BOOTSTRAP, BIT(17)); + mdelay(10); + + /* Get Atheros S26 PHY out of reset. */ + clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG, + 0x1f, 0x10); + mdelay(10); + + setbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask); + mdelay(10); + clrbits_be32(rregs + AR933X_RESET_REG_RESET_MODULE, mask); + mdelay(10); + + /* Configure AR93xx GMAC register. */ + clrsetbits_be32(gregs + AR933X_GMAC_REG_ETH_CFG, + AR933X_ETH_CFG_MII_GE0_MASTER | + AR933X_ETH_CFG_MII_GE0_SLAVE, + AR933X_ETH_CFG_MII_GE0_SLAVE); + return 0; +} + +static int eth_init_ar934x(void) +{ + void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE, + MAP_NOCACHE); + void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + void __iomem *gregs = map_physmem(AR934X_GMAC_BASE, AR934X_GMAC_SIZE, + MAP_NOCACHE); + const u32 mask = AR934X_RESET_GE0_MAC | AR934X_RESET_GE0_MDIO | + AR934X_RESET_GE1_MAC | AR934X_RESET_GE1_MDIO | + AR934X_RESET_ETH_SWITCH_ANALOG; + u32 reg; + + if (!rregs || !pregs || !gregs) + return -EINVAL; + + reg = readl(rregs + AR934X_RESET_REG_BOOTSTRAP); + if (reg & AR934X_BOOTSTRAP_REF_CLK_40) + writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + else + writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); + writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG); + + setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); + mdelay(1); + clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask); + mdelay(1); + + /* Configure AR934x GMAC register. */ + writel(AR934X_ETH_CFG_RGMII_GMAC0, gregs + AR934X_GMAC_REG_ETH_CFG); + return 0; +} + +int ath79_eth_reset(void) +{ + /* + * Un-reset ethernet. DM still doesn't have any notion of reset + * framework, so we do it by hand here. + */ + if (soc_is_ar933x()) + return eth_init_ar933x(); + if (soc_is_ar934x()) + return eth_init_ar934x(); + + return -EINVAL; +} + static int usb_reset_ar933x(void __iomem *reset_regs) { /* Ungate the USB block */
Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/dts/ar934x.dtsi | 94 +++++++ arch/mips/mach-ath79/Kconfig | 9 + arch/mips/mach-ath79/Makefile | 3 +- arch/mips/mach-ath79/ar934x/Makefile | 7 + arch/mips/mach-ath79/ar934x/clk.c | 336 ++++++++++++++++++++++++ arch/mips/mach-ath79/ar934x/cpu.c | 10 + arch/mips/mach-ath79/ar934x/ddr.c | 165 ++++++++++++ arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 43 +++ arch/mips/mach-ath79/include/mach/ath79.h | 3 + 9 files changed, 669 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/ar934x.dtsi create mode 100644 arch/mips/mach-ath79/ar934x/Makefile create mode 100644 arch/mips/mach-ath79/ar934x/clk.c create mode 100644 arch/mips/mach-ath79/ar934x/cpu.c create mode 100644 arch/mips/mach-ath79/ar934x/ddr.c
diff --git a/arch/mips/dts/ar934x.dtsi b/arch/mips/dts/ar934x.dtsi new file mode 100644 index 0000000..d62c447 --- /dev/null +++ b/arch/mips/dts/ar934x.dtsi @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" + +/ { + compatible = "qca,ar934x"; + + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "mips,mips74Kc"; + reg = <0>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-output-names = "xtal"; + }; + }; + + ahb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + ranges; + + #address-cells = <1>; + #size-cells = <1>; + + ehci0: ehci@1b000100 { + compatible = "generic-ehci"; + reg = <0x1b000100 0x100>; + + status = "disabled"; + }; + + uart0: uart@18020000 { + compatible = "ns16550"; + reg = <0x18020000 0x20>; + reg-shift = <2>; + + status = "disabled"; + }; + + gmac0: eth@0x19000000 { + compatible = "qca,ag934x-mac"; + reg = <0x19000000 0x200>; + phy-mode = "rgmii"; + + status = "disabled"; + }; + + gmac1: eth@0x1a000000 { + compatible = "qca,ag934x-mac"; + reg = <0x1a000000 0x200>; + phy-mode = "rgmii"; + + status = "disabled"; + }; + }; + + spi0: spi@1f000000 { + compatible = "qca,ar7100-spi"; + reg = <0x1f000000 0x10>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index f45403b..527960f 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -13,6 +13,15 @@ config SOC_AR933X help This supports QCA/Atheros ar933x family SOCs.
+config SOC_AR934X + bool + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select MIPS_TUNE_74KC + help + This supports QCA/Atheros ar934x family SOCs. + config SOC_QCA953X bool select SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile index 160dfaa..d7e2666 100644 --- a/arch/mips/mach-ath79/Makefile +++ b/arch/mips/mach-ath79/Makefile @@ -7,4 +7,5 @@ obj-y += cpu.o obj-y += dram.o
obj-$(CONFIG_SOC_AR933X) += ar933x/ -obj-$(CONFIG_SOC_QCA953X) += qca953x/ \ No newline at end of file +obj-$(CONFIG_SOC_AR934X) += ar934x/ +obj-$(CONFIG_SOC_QCA953X) += qca953x/ diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile new file mode 100644 index 0000000..348c65b --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += clk.o +obj-y += ddr.o diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c new file mode 100644 index 0000000..6611b8d --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -0,0 +1,336 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> +#include <wait_bit.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The math for calculating PLL: + * NFRAC * 2^8 + * NINT + ------------- + * XTAL [MHz] 2^(18 - 1) + * PLL [MHz] = ------------ * ---------------------- + * REFDIV 2^OUTDIV + * + * Unfortunatelly, there is no way to reliably compute the variables. + * The vendor U-Boot port contains macros for various combinations of + * CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern + * in those numbers. + */ +struct ar934x_pll_config { + u8 range; + u8 refdiv; + u8 outdiv; + /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */ + u8 nint[2]; +}; + +struct ar934x_clock_config { + u16 cpu_freq; + u16 ddr_freq; + u16 ahb_freq; + + struct ar934x_pll_config cpu_pll; + struct ar934x_pll_config ddr_pll; +}; + +static const struct ar934x_clock_config ar934x_clock_config[] = { + { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } }, + { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } }, + { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } }, + { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } }, + { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } }, + { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } }, + { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } }, + { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } }, + { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } }, + { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } }, + { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } }, + { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } }, + { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } }, + { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, + { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } }, + { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } }, + { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, + { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } }, + { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } }, + { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } }, + { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } }, + { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } }, + { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } }, + { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } }, + { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } }, + { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } }, + { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } }, + { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } }, +}; + +static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) +{ + u32 reg; + do { + writel(0x10810f00, pll_reg_base + 0x4); + writel(srif_val, pll_reg_base + 0x0); + writel(0xd0810f00, pll_reg_base + 0x4); + writel(0x03000000, pll_reg_base + 0x8); + writel(0xd0800f00, pll_reg_base + 0x4); + + clrbits_be32(pll_reg_base + 0x8, BIT(30)); + udelay(5); + setbits_be32(pll_reg_base + 0x8, BIT(30)); + udelay(5); + + wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0); + + clrbits_be32(pll_reg_base + 0x8, BIT(30)); + udelay(5); + + /* Check if CPU SRIF PLL locked. */ + reg = readl(pll_reg_base + 0x8); + reg = (reg & 0x7ffff8) >> 3; + } while (reg >= 0x40000); +} + +void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{ + void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, + AR934X_SRIF_SIZE, MAP_NOCACHE); + void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE, + AR71XX_RESET_SIZE, MAP_NOCACHE); + void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, + AR71XX_PLL_SIZE, MAP_NOCACHE); + const struct ar934x_pll_config *pll_cfg; + int i, xtal_40 = 0; + u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif; + + /* Register remap failed, hang. */ + if (!srif_regs || !reset_regs || !pll_regs) + hang(); + + /* Configure SRIF PLL with initial values. */ + writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG); + writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG); + writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG); + writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG); + writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */ + + /* Test for 40MHz XTAL */ + reg = get_bootstrap(); + if (reg & AR934X_BOOTSTRAP_REF_CLK_40) { + xtal_40 = 1; + cpu_srif = 0x41c00000; + ddr_srif = 0x41680000; + } else { + xtal_40 = 0; + cpu_srif = 0x29c00000; + ddr_srif = 0x29680000; + } + + /* Locate CPU/DDR PLL configuration */ + for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) { + if (cpu_mhz != ar934x_clock_config[i].cpu_freq) + continue; + if (ddr_mhz != ar934x_clock_config[i].ddr_freq) + continue; + if (ahb_mhz != ar934x_clock_config[i].ahb_freq) + continue; + + /* Entry found */ + pll_cfg = &ar934x_clock_config[i].cpu_pll; + cpu_pll = + (pll_cfg->nint[xtal_40] << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) | + (pll_cfg->refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) | + (pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) | + (pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT); + + pll_cfg = &ar934x_clock_config[i].ddr_pll; + ddr_pll = + (pll_cfg->nint[xtal_40] << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) | + (pll_cfg->refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) | + (pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) | + (pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT); + break; + } + + /* PLL configuration not found, hang. */ + if (i == ARRAY_SIZE(ar934x_clock_config)) + hang(); + + /* Set PLL Bypass */ + setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS); + setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); + setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS); + + /* Configure CPU PLL */ + writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD, + pll_regs + AR934X_PLL_CPU_CONFIG_REG); + /* Configure DDR PLL */ + writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD, + pll_regs + AR934X_PLL_DDR_CONFIG_REG); + /* Configure PLL routing */ + writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS | + AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS | + AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS | + (0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) | + (0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) | + (1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) | + AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL | + AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL | + AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL, + pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + + /* Configure SRIF PLLs, which is completely undocumented :-) */ + ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif); + ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif); + + /* Unset PLL Bypass */ + clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS); + clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS); + clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, + AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS); + + /* Enable PLL dithering */ + writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) | + (0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT), + pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG); + writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT, + pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG); +} + +static u32 ar934x_get_xtal(void) +{ + u32 val; + + val = get_bootstrap(); + if (val & AR934X_BOOTSTRAP_REF_CLK_40) + return 40000000; + else + return 25000000; +} + +int get_serial_clock(void) +{ + return ar934x_get_xtal(); +} + +static u32 ar934x_cpupll_to_hz(const u32 regval) +{ + const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_OUTDIV_MASK; + const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_CPU_CONFIG_REFDIV_MASK; + const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & + AR934X_PLL_CPU_CONFIG_NINT_MASK; + const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_CPU_CONFIG_NFRAC_MASK; + const u32 xtal = ar934x_get_xtal(); + + return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); +} + +static u32 ar934x_ddrpll_to_hz(const u32 regval) +{ + const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_OUTDIV_MASK; + const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & + AR934X_PLL_DDR_CONFIG_REFDIV_MASK; + const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & + AR934X_PLL_DDR_CONFIG_NINT_MASK; + const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & + AR934X_PLL_DDR_CONFIG_NFRAC_MASK; + const u32 xtal = ar934x_get_xtal(); + + return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); +} + +static void ar934x_update_clock(void) +{ + void __iomem *regs; + u32 ctrl, cpu, cpupll, ddr, ddrpll; + u32 cpudiv, ddrdiv, busdiv; + u32 cpuclk, ddrclk, busclk; + + regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, + MAP_NOCACHE); + + cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG); + ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG); + ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); + + cpupll = ar934x_cpupll_to_hz(cpu); + ddrpll = ar934x_ddrpll_to_hz(ddr); + + if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS) + cpuclk = ar934x_get_xtal(); + else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL) + cpuclk = cpupll; + else + cpuclk = ddrpll; + + if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS) + ddrclk = ar934x_get_xtal(); + else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL) + ddrclk = ddrpll; + else + ddrclk = cpupll; + + if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS) + busclk = ar934x_get_xtal(); + else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) + busclk = ddrpll; + else + busclk = cpupll; + + cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & + AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK; + ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & + AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK; + busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & + AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK; + + gd->cpu_clk = cpuclk / (cpudiv + 1); + gd->mem_clk = ddrclk / (ddrdiv + 1); + gd->bus_clk = busclk / (busdiv + 1); +} + +ulong get_bus_freq(ulong dummy) +{ + ar934x_update_clock(); + return gd->bus_clk; +} + +ulong get_ddr_freq(ulong dummy) +{ + ar934x_update_clock(); + return gd->mem_clk; +} + +int do_ar934x_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + ar934x_update_clock(); + printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000); + printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000); + printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000); + return 0; +} + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclocks, + "display clocks", + "" +); diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c new file mode 100644 index 0000000..8fcdf65 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/cpu.c @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +/* The lowlevel_init() is not needed on AR934x */ +void lowlevel_init(void) {} diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c new file mode 100644 index 0000000..175ffa5 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/ddr.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * Based on RAM init sequence by Piotr Dymacz pepe2k@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum { + AR934X_SDRAM = 0, + AR934X_DDR1, + AR934X_DDR2, +}; + +struct ar934x_mem_config { + u32 config1; + u32 config2; + u32 mode; + u32 extmode; + u32 tap; +}; + +static const struct ar934x_mem_config ar934x_mem_config[] = { + [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f }, + [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 }, + [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 }, +}; + +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{ + void __iomem *ddr_regs; + const struct ar934x_mem_config *memcfg; + int memtype; + u32 reg, cycle, ctl; + + ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, + MAP_NOCACHE); + + reg = get_bootstrap(); + if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */ + if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */ + memtype = AR934X_DDR1; + cycle = 0xffff; + } else { /* DDR 2 */ + memtype = AR934X_DDR2; + if (gd->arch.rev) { + ctl = BIT(6); /* Undocumented bit :-( */ + if (reg & BIT(3)) + cycle = 0xff; + else + cycle = 0xffff; + } else { + /* Force DDR2/x16 configuratio on old chips. */ + ctl = 0; + cycle = 0xffff; /* DDR2 16bit */ + } + + writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG); + udelay(100); + + writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF); + udelay(10); + } + } else { /* SDRAM */ + memtype = AR934X_SDRAM; + cycle = 0xffffffff; + + writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF); + udelay(100); + + /* Undocumented register */ + writel(0x13b, ddr_regs + 0x118); + udelay(100); + } + + memcfg = &ar934x_mem_config[memtype]; + + writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG); + udelay(100); + + writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2); + udelay(100); + + writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE); + mdelay(1); + + writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + if (memtype == AR934X_DDR2) { + writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR); + udelay(100); + + writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + } + + if (memtype != AR934X_SDRAM) + writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR); + + udelay(100); + + writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE); + udelay(100); + + writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL); + udelay(10); + + writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH); + udelay(100); + + writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0); + writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1); + + if (memtype != AR934X_SDRAM) { + if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) { + writel(memcfg->tap, ddr_regs + AR934X_DDR_REG_TAP_CTRL2); + writel(memcfg->tap, ddr_regs + AR934X_DDR_REG_TAP_CTRL3); + } + } + + writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE); + udelay(100); + + writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST); + udelay(100); + + writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2); + udelay(100); + + writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX); + udelay(100); + + // FIXME PMU2 ddr ldo tune +// ar7240_reg_rmw_set(0xb8116c44, (0x3 << 19)); +// udelay(100); +} + +void ddr_tap_tuning(void) +{ +} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index a9630c0..a8e51cb 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -250,11 +250,22 @@ #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c
+#define AR934X_DDR_REG_TAP_CTRL2 0x24 +#define AR934X_DDR_REG_TAP_CTRL3 0x28 #define AR934X_DDR_REG_FLUSH_GE0 0x9c #define AR934X_DDR_REG_FLUSH_GE1 0xa0 #define AR934X_DDR_REG_FLUSH_USB 0xa4 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 #define AR934X_DDR_REG_FLUSH_WMAC 0xac +#define AR934X_DDR_REG_FLUSH_SRC1 0xb0 +#define AR934X_DDR_REG_FLUSH_SRC2 0xb4 +#define AR934X_DDR_REG_DDR2_CONFIG 0xb8 +#define AR934X_DDR_REG_EMR2 0xbc +#define AR934X_DDR_REG_EMR3 0xc0 +#define AR934X_DDR_REG_BURST 0xc4 +#define AR934X_DDR_REG_BURST2 0xc8 +#define AR934X_DDR_REG_TIMEOUT_MAX 0xcc +#define AR934X_DDR_REG_CTL_CONF 0x108
#define QCA953X_DDR_REG_FLUSH_GE0 0x9c #define QCA953X_DDR_REG_FLUSH_GE1 0xa0 @@ -341,6 +352,8 @@ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define AR934X_PLL_DDR_DIT_FRAC_REG 0x44 +#define AR934X_PLL_CPU_DIT_FRAC_REG 0x48
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f @@ -348,8 +361,12 @@ #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17 +#define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 +#define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30) +#define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff @@ -357,8 +374,12 @@ #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21 +#define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 +#define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30) +#define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) @@ -375,6 +396,26 @@
#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6)
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10 +#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f +#define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31) + +#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f +#define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31) + #define QCA953X_PLL_CPU_CONFIG_REG 0x00 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 #define QCA953X_PLL_CLK_CTRL_REG 0x08 @@ -1081,10 +1122,12 @@ #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 +#define AR934X_SRIF_CPU_DPLL4_REG 0x1cc
#define AR934X_SRIF_DDR_DPLL1_REG 0x240 #define AR934X_SRIF_DDR_DPLL2_REG 0x244 #define AR934X_SRIF_DDR_DPLL3_REG 0x248 +#define AR934X_SRIF_DDR_DPLL4_REG 0x24c
#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 2c6c118..17af082 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -143,4 +143,7 @@ static inline int soc_is_qca956x(void) int ath79_eth_reset(void); int ath79_usb_reset(void);
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); + #endif /* __ASM_MACH_ATH79_H */
Am 05.05.2016 um 20:14 schrieb Marek Vasut:
Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com
arch/mips/dts/ar934x.dtsi | 94 +++++++ arch/mips/mach-ath79/Kconfig | 9 + arch/mips/mach-ath79/Makefile | 3 +- arch/mips/mach-ath79/ar934x/Makefile | 7 + arch/mips/mach-ath79/ar934x/clk.c | 336 ++++++++++++++++++++++++ arch/mips/mach-ath79/ar934x/cpu.c | 10 + arch/mips/mach-ath79/ar934x/ddr.c | 165 ++++++++++++ arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 43 +++ arch/mips/mach-ath79/include/mach/ath79.h | 3 + 9 files changed, 669 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/ar934x.dtsi create mode 100644 arch/mips/mach-ath79/ar934x/Makefile create mode 100644 arch/mips/mach-ath79/ar934x/clk.c create mode 100644 arch/mips/mach-ath79/ar934x/cpu.c create mode 100644 arch/mips/mach-ath79/ar934x/ddr.c
there are checkpatch.pl warnings:
warning: arch/mips/mach-ath79/ar934x/clk.c,151: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,152: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,158: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,159: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,323: line over 80 characters warning: arch/mips/mach-ath79/ar934x/ddr.c,141: line over 80 characters warning: arch/mips/mach-ath79/ar934x/ddr.c,142: line over 80 characters error: arch/mips/mach-ath79/ar934x/ddr.c,158: do not use C99 // comments error: arch/mips/mach-ath79/ar934x/ddr.c,159: do not use C99 // comments error: arch/mips/mach-ath79/ar934x/ddr.c,160: do not use C99 // comments
checkpatch.pl found 3 error(s), 8 warning(s), 0 checks(s)
diff --git a/arch/mips/dts/ar934x.dtsi b/arch/mips/dts/ar934x.dtsi new file mode 100644 index 0000000..d62c447 --- /dev/null +++ b/arch/mips/dts/ar934x.dtsi @@ -0,0 +1,94 @@ +/*
- Copyright (C) 2016 Marek Vasut marex@denx.de
- SPDX-License-Identifier: GPL-2.0+
- */
+#include "skeleton.dtsi"
+/ {
- compatible = "qca,ar934x";
- #address-cells = <1>;
- #size-cells = <1>;
- cpus {
#address-cells = <1>;#size-cells = <0>;cpu@0 {device_type = "cpu";compatible = "mips,mips74Kc";reg = <0>;};- };
- clocks {
#address-cells = <1>;#size-cells = <1>;ranges;xtal: xtal {#clock-cells = <0>;compatible = "fixed-clock";clock-output-names = "xtal";};- };
- ahb {
compatible = "simple-bus";ranges;#address-cells = <1>;#size-cells = <1>;apb {compatible = "simple-bus";ranges;#address-cells = <1>;#size-cells = <1>;ehci0: ehci@1b000100 {compatible = "generic-ehci";reg = <0x1b000100 0x100>;status = "disabled";};uart0: uart@18020000 {compatible = "ns16550";reg = <0x18020000 0x20>;reg-shift = <2>;status = "disabled";};gmac0: eth@0x19000000 {compatible = "qca,ag934x-mac";reg = <0x19000000 0x200>;phy-mode = "rgmii";status = "disabled";};gmac1: eth@0x1a000000 {compatible = "qca,ag934x-mac";reg = <0x1a000000 0x200>;phy-mode = "rgmii";status = "disabled";};};spi0: spi@1f000000 {compatible = "qca,ar7100-spi";reg = <0x1f000000 0x10>;status = "disabled";#address-cells = <1>;#size-cells = <0>;};- };
+}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index f45403b..527960f 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -13,6 +13,15 @@ config SOC_AR933X help This supports QCA/Atheros ar933x family SOCs.
+config SOC_AR934X
- bool
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select MIPS_TUNE_74KC
MIPS_TUNE_74KC doesn't exist yet in arch/mips/Makefile and arch/mips/Kconfig. You should add it with an extra patch.
- help
This supports QCA/Atheros ar934x family SOCs.config SOC_QCA953X bool select SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile index 160dfaa..d7e2666 100644 --- a/arch/mips/mach-ath79/Makefile +++ b/arch/mips/mach-ath79/Makefile @@ -7,4 +7,5 @@ obj-y += cpu.o obj-y += dram.o
obj-$(CONFIG_SOC_AR933X) += ar933x/ -obj-$(CONFIG_SOC_QCA953X) += qca953x/ \ No newline at end of file +obj-$(CONFIG_SOC_AR934X) += ar934x/ +obj-$(CONFIG_SOC_QCA953X) += qca953x/ diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile new file mode 100644 index 0000000..348c65b --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += cpu.o +obj-y += clk.o +obj-y += ddr.o diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c new file mode 100644 index 0000000..6611b8d --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -0,0 +1,336 @@ +/*
- Copyright (C) 2016 Marek Vasut marex@denx.de
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> +#include <wait_bit.h>
+DECLARE_GLOBAL_DATA_PTR;
+/*
- The math for calculating PLL:
NFRAC * 2^8
NINT + -------------
XTAL [MHz] 2^(18 - 1)
- PLL [MHz] = ------------ * ----------------------
REFDIV 2^OUTDIV
- Unfortunatelly, there is no way to reliably compute the variables.
- The vendor U-Boot port contains macros for various combinations of
- CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
- in those numbers.
- */
+struct ar934x_pll_config {
- u8 range;
- u8 refdiv;
- u8 outdiv;
- /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
- u8 nint[2];
+};
+struct ar934x_clock_config {
- u16 cpu_freq;
- u16 ddr_freq;
- u16 ahb_freq;
- struct ar934x_pll_config cpu_pll;
- struct ar934x_pll_config ddr_pll;
+};
+static const struct ar934x_clock_config ar934x_clock_config[] = {
- { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
- { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
- { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
- { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
- { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
- { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
- { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
- { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
- { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
- { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
- { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
- { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
- { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
- { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
- { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
- { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
- { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
- { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
- { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
- { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
- { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
- { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
- { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
- { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
- { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
- { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
- { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
- { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
+};
+static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) +{
- u32 reg;
- do {
writel(0x10810f00, pll_reg_base + 0x4);writel(srif_val, pll_reg_base + 0x0);writel(0xd0810f00, pll_reg_base + 0x4);writel(0x03000000, pll_reg_base + 0x8);writel(0xd0800f00, pll_reg_base + 0x4);clrbits_be32(pll_reg_base + 0x8, BIT(30));udelay(5);setbits_be32(pll_reg_base + 0x8, BIT(30));udelay(5);wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);clrbits_be32(pll_reg_base + 0x8, BIT(30));udelay(5);/* Check if CPU SRIF PLL locked. */reg = readl(pll_reg_base + 0x8);reg = (reg & 0x7ffff8) >> 3;- } while (reg >= 0x40000);
+}
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{
- void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
AR934X_SRIF_SIZE, MAP_NOCACHE);- void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE, MAP_NOCACHE);- void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE, MAP_NOCACHE);- const struct ar934x_pll_config *pll_cfg;
- int i, xtal_40 = 0;
- u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
- /* Register remap failed, hang. */
- if (!srif_regs || !reset_regs || !pll_regs)
hang();
map_physmem() is never NULL unless you implement plat_ioremap(). Thus those checks aren't necessary.
- /* Configure SRIF PLL with initial values. */
- writel(0x13210f00, srif_regs + AR934X_SRIF_CPU_DPLL2_REG);
- writel(0x03000000, srif_regs + AR934X_SRIF_CPU_DPLL3_REG);
- writel(0x13210f00, srif_regs + AR934X_SRIF_DDR_DPLL2_REG);
- writel(0x03000000, srif_regs + AR934X_SRIF_DDR_DPLL3_REG);
- writel(0x03000000, srif_regs + 0x188); /* Undocumented reg :-) */
- /* Test for 40MHz XTAL */
- reg = get_bootstrap();
- if (reg & AR934X_BOOTSTRAP_REF_CLK_40) {
xtal_40 = 1;cpu_srif = 0x41c00000;ddr_srif = 0x41680000;- } else {
xtal_40 = 0;cpu_srif = 0x29c00000;ddr_srif = 0x29680000;- }
- /* Locate CPU/DDR PLL configuration */
- for (i = 0; i < ARRAY_SIZE(ar934x_clock_config); i++) {
if (cpu_mhz != ar934x_clock_config[i].cpu_freq)continue;if (ddr_mhz != ar934x_clock_config[i].ddr_freq)continue;if (ahb_mhz != ar934x_clock_config[i].ahb_freq)continue;/* Entry found */pll_cfg = &ar934x_clock_config[i].cpu_pll;cpu_pll =(pll_cfg->nint[xtal_40] << AR934X_PLL_CPU_CONFIG_NINT_SHIFT) |(pll_cfg->refdiv << AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) |(pll_cfg->range << AR934X_PLL_CPU_CONFIG_RANGE_SHIFT) |(pll_cfg->outdiv << AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT);pll_cfg = &ar934x_clock_config[i].ddr_pll;ddr_pll =(pll_cfg->nint[xtal_40] << AR934X_PLL_DDR_CONFIG_NINT_SHIFT) |(pll_cfg->refdiv << AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) |(pll_cfg->range << AR934X_PLL_DDR_CONFIG_RANGE_SHIFT) |(pll_cfg->outdiv << AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT);break;- }
- /* PLL configuration not found, hang. */
- if (i == ARRAY_SIZE(ar934x_clock_config))
hang();- /* Set PLL Bypass */
- setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);- setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);- setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);- /* Configure CPU PLL */
- writel(cpu_pll | AR934X_PLL_CPU_CONFIG_PLLPWD,
pll_regs + AR934X_PLL_CPU_CONFIG_REG);- /* Configure DDR PLL */
- writel(ddr_pll | AR934X_PLL_DDR_CONFIG_PLLPWD,
pll_regs + AR934X_PLL_DDR_CONFIG_REG);- /* Configure PLL routing */
- writel(AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS |
AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS |AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS |(0 << AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) |(0 << AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) |(1 << AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) |AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL |AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL |AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL,pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);- /* Configure SRIF PLLs, which is completely undocumented :-) */
- ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_CPU_DPLL1_REG, cpu_srif);
- ar934x_srif_pll_cfg(srif_regs + AR934X_SRIF_DDR_DPLL1_REG, ddr_srif);
- /* Unset PLL Bypass */
- clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS);- clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS);- clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG,
AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS);- /* Enable PLL dithering */
- writel((1 << AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT) |
(0xf << AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT),pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG);- writel(48 << AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT,
pll_regs + AR934X_PLL_CPU_DIT_FRAC_REG);+}
+static u32 ar934x_get_xtal(void) +{
- u32 val;
- val = get_bootstrap();
- if (val & AR934X_BOOTSTRAP_REF_CLK_40)
return 40000000;- else
return 25000000;+}
+int get_serial_clock(void) +{
- return ar934x_get_xtal();
+}
+static u32 ar934x_cpupll_to_hz(const u32 regval) +{
- const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;- const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_REFDIV_MASK;- const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
AR934X_PLL_CPU_CONFIG_NINT_MASK;- const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
AR934X_PLL_CPU_CONFIG_NFRAC_MASK;- const u32 xtal = ar934x_get_xtal();
- return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+static u32 ar934x_ddrpll_to_hz(const u32 regval) +{
- const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;- const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_REFDIV_MASK;- const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
AR934X_PLL_DDR_CONFIG_NINT_MASK;- const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
AR934X_PLL_DDR_CONFIG_NFRAC_MASK;- const u32 xtal = ar934x_get_xtal();
- return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv));
+}
+static void ar934x_update_clock(void) +{
- void __iomem *regs;
- u32 ctrl, cpu, cpupll, ddr, ddrpll;
- u32 cpudiv, ddrdiv, busdiv;
- u32 cpuclk, ddrclk, busclk;
- regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
MAP_NOCACHE);- cpu = readl(regs + AR934X_PLL_CPU_CONFIG_REG);
- ddr = readl(regs + AR934X_PLL_DDR_CONFIG_REG);
- ctrl = readl(regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
- cpupll = ar934x_cpupll_to_hz(cpu);
- ddrpll = ar934x_ddrpll_to_hz(ddr);
- if (ctrl & AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpuclk = ar934x_get_xtal();- else if (ctrl & AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
cpuclk = cpupll;- else
cpuclk = ddrpll;- if (ctrl & AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddrclk = ar934x_get_xtal();- else if (ctrl & AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
ddrclk = ddrpll;- else
ddrclk = cpupll;- if (ctrl & AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
busclk = ar934x_get_xtal();- else if (ctrl & AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
busclk = ddrpll;- else
busclk = cpupll;- cpudiv = (ctrl >> AR934X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
AR934X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;- ddrdiv = (ctrl >> AR934X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
AR934X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;- busdiv = (ctrl >> AR934X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
AR934X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;- gd->cpu_clk = cpuclk / (cpudiv + 1);
- gd->mem_clk = ddrclk / (ddrdiv + 1);
- gd->bus_clk = busclk / (busdiv + 1);
+}
+ulong get_bus_freq(ulong dummy) +{
- ar934x_update_clock();
- return gd->bus_clk;
+}
+ulong get_ddr_freq(ulong dummy) +{
- ar934x_update_clock();
- return gd->mem_clk;
+}
+int do_ar934x_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{
- ar934x_update_clock();
- printf("CPU: %8ld MHz\n", gd->cpu_clk / 1000000);
- printf("Memory: %8ld MHz\n", gd->mem_clk / 1000000);
- printf("AHB: %8ld MHz\n", gd->bus_clk / 1000000);
- return 0;
+}
+U_BOOT_CMD(
- clocks, CONFIG_SYS_MAXARGS, 1, do_ar934x_showclocks,
- "display clocks",
- ""
+); diff --git a/arch/mips/mach-ath79/ar934x/cpu.c b/arch/mips/mach-ath79/ar934x/cpu.c new file mode 100644 index 0000000..8fcdf65 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/cpu.c @@ -0,0 +1,10 @@ +/*
- Copyright (C) 2016 Marek Vasut marex@denx.de
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h>
+/* The lowlevel_init() is not needed on AR934x */ +void lowlevel_init(void) {} diff --git a/arch/mips/mach-ath79/ar934x/ddr.c b/arch/mips/mach-ath79/ar934x/ddr.c new file mode 100644 index 0000000..175ffa5 --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/ddr.c @@ -0,0 +1,165 @@ +/*
- Copyright (C) 2016 Marek Vasut marex@denx.de
- Based on RAM init sequence by Piotr Dymacz pepe2k@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h>
+DECLARE_GLOBAL_DATA_PTR;
+enum {
- AR934X_SDRAM = 0,
- AR934X_DDR1,
- AR934X_DDR2,
+};
+struct ar934x_mem_config {
- u32 config1;
- u32 config2;
- u32 mode;
- u32 extmode;
- u32 tap;
+};
+static const struct ar934x_mem_config ar934x_mem_config[] = {
- [AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
- [AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
- [AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
+};
+void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{
- void __iomem *ddr_regs;
- const struct ar934x_mem_config *memcfg;
- int memtype;
- u32 reg, cycle, ctl;
- ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);- reg = get_bootstrap();
- if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */memtype = AR934X_DDR1;cycle = 0xffff;} else { /* DDR 2 */memtype = AR934X_DDR2;if (gd->arch.rev) {ctl = BIT(6); /* Undocumented bit :-( */if (reg & BIT(3))cycle = 0xff;elsecycle = 0xffff;} else {/* Force DDR2/x16 configuratio on old chips. */ctl = 0;cycle = 0xffff; /* DDR2 16bit */}writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);udelay(100);writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);udelay(10);writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);udelay(10);writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);udelay(10);}- } else { /* SDRAM */
memtype = AR934X_SDRAM;cycle = 0xffffffff;writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);udelay(100);/* Undocumented register */writel(0x13b, ddr_regs + 0x118);udelay(100);- }
- memcfg = &ar934x_mem_config[memtype];
- writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
- udelay(100);
- writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
- udelay(100);
- writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
- udelay(10);
- writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
- mdelay(1);
- writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
- udelay(10);
- if (memtype == AR934X_DDR2) {
writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);udelay(100);writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);udelay(10);- }
- if (memtype != AR934X_SDRAM)
writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);- udelay(100);
- writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
- udelay(10);
- writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
- udelay(10);
- writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
- udelay(100);
- writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
- udelay(10);
- writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
- udelay(100);
- writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
- writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
- if (memtype != AR934X_SDRAM) {
if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {writel(memcfg->tap, ddr_regs + AR934X_DDR_REG_TAP_CTRL2);writel(memcfg->tap, ddr_regs + AR934X_DDR_REG_TAP_CTRL3);}- }
- writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
- udelay(100);
- writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
- udelay(100);
- writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
- udelay(100);
- writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
- udelay(100);
- // FIXME PMU2 ddr ldo tune
+// ar7240_reg_rmw_set(0xb8116c44, (0x3 << 19)); +// udelay(100); +}
+void ddr_tap_tuning(void) +{ +} diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index a9630c0..a8e51cb 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -250,11 +250,22 @@ #define AR933X_DDR_REG_TIMEOUT_CNT 0x9c #define AR933X_DDR_REG_TIMEOUT_ADDR 0x9c
+#define AR934X_DDR_REG_TAP_CTRL2 0x24 +#define AR934X_DDR_REG_TAP_CTRL3 0x28 #define AR934X_DDR_REG_FLUSH_GE0 0x9c #define AR934X_DDR_REG_FLUSH_GE1 0xa0 #define AR934X_DDR_REG_FLUSH_USB 0xa4 #define AR934X_DDR_REG_FLUSH_PCIE 0xa8 #define AR934X_DDR_REG_FLUSH_WMAC 0xac +#define AR934X_DDR_REG_FLUSH_SRC1 0xb0 +#define AR934X_DDR_REG_FLUSH_SRC2 0xb4 +#define AR934X_DDR_REG_DDR2_CONFIG 0xb8 +#define AR934X_DDR_REG_EMR2 0xbc +#define AR934X_DDR_REG_EMR3 0xc0 +#define AR934X_DDR_REG_BURST 0xc4 +#define AR934X_DDR_REG_BURST2 0xc8 +#define AR934X_DDR_REG_TIMEOUT_MAX 0xcc +#define AR934X_DDR_REG_CTL_CONF 0x108
#define QCA953X_DDR_REG_FLUSH_GE0 0x9c #define QCA953X_DDR_REG_FLUSH_GE1 0xa0 @@ -341,6 +352,8 @@ #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 #define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c +#define AR934X_PLL_DDR_DIT_FRAC_REG 0x44 +#define AR934X_PLL_CPU_DIT_FRAC_REG 0x48
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f @@ -348,8 +361,12 @@ #define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_CPU_CONFIG_RANGE_SHIFT 17 +#define AR934X_PLL_CPU_CONFIG_RANGE_MASK 0x3 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3 +#define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30) +#define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff @@ -357,8 +374,12 @@ #define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f +#define AR934X_PLL_DDR_CONFIG_RANGE_SHIFT 21 +#define AR934X_PLL_DDR_CONFIG_RANGE_MASK 0x3 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7 +#define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30) +#define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
#define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2) #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3) @@ -375,6 +396,26 @@
#define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6)
+#define AR934X_PLL_DDR_DIT_FRAC_MAX_SHIFT 0 +#define AR934X_PLL_DDR_DIT_FRAC_MAX_MASK 0x3ff +#define AR934X_PLL_DDR_DIT_FRAC_MIN_SHIFT 10 +#define AR934X_PLL_DDR_DIT_FRAC_MIN_MASK 0x3ff +#define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20 +#define AR934X_PLL_DDR_DIT_FRAC_STEP_MASK 0x3f +#define AR934X_PLL_DDR_DIT_UPD_CNT_SHIFT 27 +#define AR934X_PLL_DDR_DIT_UPD_CNT_MASK 0x3f +#define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31)
+#define AR934X_PLL_CPU_DIT_FRAC_MAX_SHIFT 0 +#define AR934X_PLL_CPU_DIT_FRAC_MAX_MASK 0x3f +#define AR934X_PLL_CPU_DIT_FRAC_MIN_SHIFT 6 +#define AR934X_PLL_CPU_DIT_FRAC_MIN_MASK 0x3f +#define AR934X_PLL_CPU_DIT_FRAC_STEP_SHIFT 12 +#define AR934X_PLL_CPU_DIT_FRAC_STEP_MASK 0x3f +#define AR934X_PLL_CPU_DIT_UPD_CNT_SHIFT 18 +#define AR934X_PLL_CPU_DIT_UPD_CNT_MASK 0x3f +#define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31)
#define QCA953X_PLL_CPU_CONFIG_REG 0x00 #define QCA953X_PLL_DDR_CONFIG_REG 0x04 #define QCA953X_PLL_CLK_CTRL_REG 0x08 @@ -1081,10 +1122,12 @@ #define AR934X_SRIF_CPU_DPLL1_REG 0x1c0 #define AR934X_SRIF_CPU_DPLL2_REG 0x1c4 #define AR934X_SRIF_CPU_DPLL3_REG 0x1c8 +#define AR934X_SRIF_CPU_DPLL4_REG 0x1cc
#define AR934X_SRIF_DDR_DPLL1_REG 0x240 #define AR934X_SRIF_DDR_DPLL2_REG 0x244 #define AR934X_SRIF_DDR_DPLL3_REG 0x248 +#define AR934X_SRIF_DDR_DPLL4_REG 0x24c
#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27 #define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index 2c6c118..17af082 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -143,4 +143,7 @@ static inline int soc_is_qca956x(void) int ath79_eth_reset(void); int ath79_usb_reset(void);
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); +void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz);
#endif /* __ASM_MACH_ATH79_H */
On 05/06/2016 01:32 PM, Daniel Schwierzeck wrote:
Am 05.05.2016 um 20:14 schrieb Marek Vasut:
Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com
arch/mips/dts/ar934x.dtsi | 94 +++++++ arch/mips/mach-ath79/Kconfig | 9 + arch/mips/mach-ath79/Makefile | 3 +- arch/mips/mach-ath79/ar934x/Makefile | 7 + arch/mips/mach-ath79/ar934x/clk.c | 336 ++++++++++++++++++++++++ arch/mips/mach-ath79/ar934x/cpu.c | 10 + arch/mips/mach-ath79/ar934x/ddr.c | 165 ++++++++++++ arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 43 +++ arch/mips/mach-ath79/include/mach/ath79.h | 3 + 9 files changed, 669 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/ar934x.dtsi create mode 100644 arch/mips/mach-ath79/ar934x/Makefile create mode 100644 arch/mips/mach-ath79/ar934x/clk.c create mode 100644 arch/mips/mach-ath79/ar934x/cpu.c create mode 100644 arch/mips/mach-ath79/ar934x/ddr.c
there are checkpatch.pl warnings:
warning: arch/mips/mach-ath79/ar934x/clk.c,151: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,152: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,158: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,159: line over 80 characters warning: arch/mips/mach-ath79/ar934x/clk.c,323: line over 80 characters warning: arch/mips/mach-ath79/ar934x/ddr.c,141: line over 80 characters warning: arch/mips/mach-ath79/ar934x/ddr.c,142: line over 80 characters
Hm, I'm not fond of fixing lines which are 81 lines long and fixing them makes the code only more cryptic, but fixed.
error: arch/mips/mach-ath79/ar934x/ddr.c,158: do not use C99 // comments error: arch/mips/mach-ath79/ar934x/ddr.c,159: do not use C99 // comments error: arch/mips/mach-ath79/ar934x/ddr.c,160: do not use C99 // comments
Oops, these should really be removed. Thanks for spotting that.
checkpatch.pl found 3 error(s), 8 warning(s), 0 checks(s)
diff --git a/arch/mips/dts/ar934x.dtsi b/arch/mips/dts/ar934x.dtsi new file mode 100644 index 0000000..d62c447 --- /dev/null +++ b/arch/mips/dts/ar934x.dtsi @@ -0,0 +1,94 @@ +/*
- Copyright (C) 2016 Marek Vasut marex@denx.de
- SPDX-License-Identifier: GPL-2.0+
- */
+#include "skeleton.dtsi"
+/ {
- compatible = "qca,ar934x";
- #address-cells = <1>;
- #size-cells = <1>;
- cpus {
#address-cells = <1>;#size-cells = <0>;cpu@0 {device_type = "cpu";compatible = "mips,mips74Kc";reg = <0>;};- };
- clocks {
#address-cells = <1>;#size-cells = <1>;ranges;xtal: xtal {#clock-cells = <0>;compatible = "fixed-clock";clock-output-names = "xtal";};- };
- ahb {
compatible = "simple-bus";ranges;#address-cells = <1>;#size-cells = <1>;apb {compatible = "simple-bus";ranges;#address-cells = <1>;#size-cells = <1>;ehci0: ehci@1b000100 {compatible = "generic-ehci";reg = <0x1b000100 0x100>;status = "disabled";};uart0: uart@18020000 {compatible = "ns16550";reg = <0x18020000 0x20>;reg-shift = <2>;status = "disabled";};gmac0: eth@0x19000000 {compatible = "qca,ag934x-mac";reg = <0x19000000 0x200>;phy-mode = "rgmii";status = "disabled";};gmac1: eth@0x1a000000 {compatible = "qca,ag934x-mac";reg = <0x1a000000 0x200>;phy-mode = "rgmii";status = "disabled";};};spi0: spi@1f000000 {compatible = "qca,ar7100-spi";reg = <0x1f000000 0x10>;status = "disabled";#address-cells = <1>;#size-cells = <0>;};- };
+}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index f45403b..527960f 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -13,6 +13,15 @@ config SOC_AR933X help This supports QCA/Atheros ar933x family SOCs.
+config SOC_AR934X
- bool
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select MIPS_TUNE_74KC
MIPS_TUNE_74KC doesn't exist yet in arch/mips/Makefile and arch/mips/Kconfig. You should add it with an extra patch.
Done
- help
This supports QCA/Atheros ar934x family SOCs.config SOC_QCA953X bool select SUPPORTS_BIG_ENDIAN diff --git a/arch/mips/mach-ath79/Makefile b/arch/mips/mach-ath79/Makefile index 160dfaa..d7e2666 100644 --- a/arch/mips/mach-ath79/Makefile +++ b/arch/mips/mach-ath79/Makefile @@ -7,4 +7,5 @@ obj-y += cpu.o obj-y += dram.o
obj-$(CONFIG_SOC_AR933X) += ar933x/ -obj-$(CONFIG_SOC_QCA953X) += qca953x/ \ No newline at end of file +obj-$(CONFIG_SOC_AR934X) += ar934x/ +obj-$(CONFIG_SOC_QCA953X) += qca953x/ diff --git a/arch/mips/mach-ath79/ar934x/Makefile b/arch/mips/mach-ath79/ar934x/Makefile new file mode 100644 index 0000000..348c65b --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/Makefile @@ -0,0 +1,7 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += cpu.o +obj-y += clk.o +obj-y += ddr.o diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c new file mode 100644 index 0000000..6611b8d --- /dev/null +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -0,0 +1,336 @@ +/*
- Copyright (C) 2016 Marek Vasut marex@denx.de
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ar71xx_regs.h> +#include <mach/reset.h> +#include <wait_bit.h>
+DECLARE_GLOBAL_DATA_PTR;
+/*
- The math for calculating PLL:
NFRAC * 2^8
NINT + -------------
XTAL [MHz] 2^(18 - 1)
- PLL [MHz] = ------------ * ----------------------
REFDIV 2^OUTDIV
- Unfortunatelly, there is no way to reliably compute the variables.
- The vendor U-Boot port contains macros for various combinations of
- CPU PLL / DDR PLL / AHB bus speed and there is no obvious pattern
- in those numbers.
- */
+struct ar934x_pll_config {
- u8 range;
- u8 refdiv;
- u8 outdiv;
- /* Index 0 is for XTAL=25MHz , Index 1 is for XTAL=40MHz */
- u8 nint[2];
+};
+struct ar934x_clock_config {
- u16 cpu_freq;
- u16 ddr_freq;
- u16 ahb_freq;
- struct ar934x_pll_config cpu_pll;
- struct ar934x_pll_config ddr_pll;
+};
+static const struct ar934x_clock_config ar934x_clock_config[] = {
- { 300, 300, 150, { 1, 1, 1, { 24, 15 } }, { 1, 1, 1, { 24, 15 } } },
- { 400, 200, 200, { 1, 1, 1, { 32, 20 } }, { 1, 1, 2, { 32, 20 } } },
- { 400, 400, 200, { 0, 1, 1, { 32, 20 } }, { 0, 1, 1, { 32, 20 } } },
- { 500, 400, 200, { 1, 1, 0, { 20, 12 } }, { 0, 1, 1, { 32, 20 } } },
- { 533, 400, 200, { 1, 1, 0, { 21, 13 } }, { 0, 1, 1, { 32, 20 } } },
- { 533, 500, 250, { 1, 1, 0, { 21, 13 } }, { 0, 1, 0, { 20, 12 } } },
- { 560, 480, 240, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 12 } } },
- { 566, 400, 200, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 16, 10 } } },
- { 566, 450, 225, { 1, 1, 0, { 22, 14 } }, { 0, 1, 1, { 36, 22 } } },
- { 566, 475, 237, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 19, 11 } } },
- { 566, 500, 250, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 20, 12 } } },
- { 566, 525, 262, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 21, 13 } } },
- { 566, 550, 275, { 1, 1, 0, { 22, 14 } }, { 1, 1, 0, { 22, 13 } } },
- { 600, 266, 133, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
- { 600, 266, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 21, 16 } } },
- { 600, 300, 150, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 24, 15 } } },
- { 600, 332, 166, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
- { 600, 332, 200, { 0, 1, 0, { 24, 15 } }, { 1, 1, 1, { 26, 16 } } },
- { 600, 400, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 1, { 32, 20 } } },
- { 600, 450, 200, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 18, 20 } } },
- { 600, 500, 250, { 0, 1, 0, { 24, 15 } }, { 1, 1, 0, { 20, 12 } } },
- { 600, 525, 262, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 21, 20 } } },
- { 600, 550, 275, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 22, 20 } } },
- { 600, 575, 287, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 23, 14 } } },
- { 600, 600, 300, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 24, 20 } } },
- { 600, 650, 325, { 0, 1, 0, { 24, 15 } }, { 0, 1, 0, { 26, 20 } } },
- { 650, 600, 300, { 0, 1, 0, { 26, 15 } }, { 0, 1, 0, { 24, 20 } } },
- { 700, 400, 200, { 3, 1, 0, { 28, 17 } }, { 0, 1, 1, { 32, 20 } } },
+};
+static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) +{
- u32 reg;
- do {
writel(0x10810f00, pll_reg_base + 0x4);writel(srif_val, pll_reg_base + 0x0);writel(0xd0810f00, pll_reg_base + 0x4);writel(0x03000000, pll_reg_base + 0x8);writel(0xd0800f00, pll_reg_base + 0x4);clrbits_be32(pll_reg_base + 0x8, BIT(30));udelay(5);setbits_be32(pll_reg_base + 0x8, BIT(30));udelay(5);wait_for_bit("clk", pll_reg_base + 0xc, BIT(3), 1, 10, 0);clrbits_be32(pll_reg_base + 0x8, BIT(30));udelay(5);/* Check if CPU SRIF PLL locked. */reg = readl(pll_reg_base + 0x8);reg = (reg & 0x7ffff8) >> 3;- } while (reg >= 0x40000);
+}
+void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +{
- void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE,
AR934X_SRIF_SIZE, MAP_NOCACHE);- void __iomem *reset_regs = map_physmem(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE, MAP_NOCACHE);- void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE,
AR71XX_PLL_SIZE, MAP_NOCACHE);- const struct ar934x_pll_config *pll_cfg;
- int i, xtal_40 = 0;
- u32 reg, cpu_pll, cpu_srif, ddr_pll, ddr_srif;
- /* Register remap failed, hang. */
- if (!srif_regs || !reset_regs || !pll_regs)
hang();map_physmem() is never NULL unless you implement plat_ioremap(). Thus those checks aren't necessary.
Removed
[...]
Thanks! Best regards, Marek Vasut
Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well.
Signed-off-by: Marek Vasut marex@denx.de Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Wills Wang wills.wang@live.com --- arch/mips/dts/Makefile | 1 + arch/mips/dts/tplink_wdr4300.dts | 53 +++++++++++++++++++++++ arch/mips/mach-ath79/Kconfig | 5 +++ board/tplink/wdr4300/Kconfig | 15 +++++++ board/tplink/wdr4300/MAINTAINERS | 6 +++ board/tplink/wdr4300/Makefile | 5 +++ board/tplink/wdr4300/wdr4300.c | 74 ++++++++++++++++++++++++++++++++ configs/tplink_wdr4300_defconfig | 43 +++++++++++++++++++ include/configs/tplink_wdr4300.h | 93 ++++++++++++++++++++++++++++++++++++++++ 9 files changed, 295 insertions(+) create mode 100644 arch/mips/dts/tplink_wdr4300.dts create mode 100644 board/tplink/wdr4300/Kconfig create mode 100644 board/tplink/wdr4300/MAINTAINERS create mode 100644 board/tplink/wdr4300/Makefile create mode 100644 board/tplink/wdr4300/wdr4300.c create mode 100644 configs/tplink_wdr4300_defconfig create mode 100644 include/configs/tplink_wdr4300.h
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index bd87ead..a94b745 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb +dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
targets += $(dtb-y)
diff --git a/arch/mips/dts/tplink_wdr4300.dts b/arch/mips/dts/tplink_wdr4300.dts new file mode 100644 index 0000000..cfda4df --- /dev/null +++ b/arch/mips/dts/tplink_wdr4300.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ar934x.dtsi" + +/ { + model = "TP-Link WDR4300 Board"; + compatible = "tplink,wdr4300", "qca,ar934x"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + status = "okay"; +}; + +&spi0 { + spi-max-frequency = <25000000>; + status = "okay"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + memory-map = <0x1e000000 0x00800000>; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +&uart0 { + clock-frequency = <40000000>; + status = "okay"; +}; + +&xtal { + clock-frequency = <40000000>; +}; diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index 527960f..7d483aa 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -42,9 +42,14 @@ config TARGET_AP143 bool "AP143 Reference Board" select SOC_QCA953X
+config BOARD_TPLINK_WDR4300 + bool "TP-Link WDR4300 Board" + select SOC_AR934X + endchoice
source "board/qca/ap121/Kconfig" source "board/qca/ap143/Kconfig" +source "board/tplink/wdr4300/Kconfig"
endmenu diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig new file mode 100644 index 0000000..902abf5 --- /dev/null +++ b/board/tplink/wdr4300/Kconfig @@ -0,0 +1,15 @@ +if BOARD_TPLINK_WDR4300 + +config SYS_VENDOR + default "tplink" + +config SYS_SOC + default "ath79" + +config SYS_BOARD + default "wdr4300" + +config SYS_CONFIG_NAME + default "tplink_wdr4300" + +endif diff --git a/board/tplink/wdr4300/MAINTAINERS b/board/tplink/wdr4300/MAINTAINERS new file mode 100644 index 0000000..db239c2 --- /dev/null +++ b/board/tplink/wdr4300/MAINTAINERS @@ -0,0 +1,6 @@ +TPLINK_WDR4300 BOARD +M: Marek Vasut marex@denx.de +S: Maintained +F: board/tplink/wdr4300/ +F: include/configs/tplink_wdr4300.h +F: configs/tplink_wdr4300_defconfig diff --git a/board/tplink/wdr4300/Makefile b/board/tplink/wdr4300/Makefile new file mode 100644 index 0000000..4f0c296 --- /dev/null +++ b/board/tplink/wdr4300/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = wdr4300.o diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c new file mode 100644 index 0000000..6e070fd --- /dev/null +++ b/board/tplink/wdr4300/wdr4300.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/addrspace.h> +#include <asm/types.h> +#include <mach/ath79.h> +#include <mach/ar71xx_regs.h> +#include <mach/ddr.h> +#include <debug_uart.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB +static void wdr4300_usb_start(void) +{ + void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE, + AR71XX_GPIO_SIZE, MAP_NOCACHE); + if (!gpio_regs) + return; + + /* Power up the USB HUB. */ + clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22)); + writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET); + mdelay(1); + + ath79_usb_reset(); +} +#else +static inline void wdr4300_usb_start(void) {} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + void __iomem *regs; + + regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, + MAP_NOCACHE); + + /* Assure JTAG is not disconnected. */ + writel(0x40, regs + AR934X_GPIO_REG_FUNC); + + /* Configure default GPIO input/output regs. */ + writel(0x3031b, regs + AR71XX_GPIO_REG_OE); + writel(0x0f804, regs + AR71XX_GPIO_REG_OUT); + + /* Configure pin multiplexing. */ + writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0); + writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1); + writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2); + writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3); + writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4); + writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5); + +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + ar934x_pll_init(560, 480, 240); + ar934x_ddr_init(560, 480, 240); +#endif + + wdr4300_usb_start(); + ath79_eth_reset(); + + return 0; +} +#endif diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig new file mode 100644 index 0000000..b1af2f6 --- /dev/null +++ b/configs/tplink_wdr4300_defconfig @@ -0,0 +1,43 @@ +CONFIG_MIPS=y +CONFIG_ARCH_ATH79=y +CONFIG_BOARD_TPLINK_WDR4300=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_NS16550=y +CONFIG_DM_SERIAL=y +CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300" +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_NET=y +CONFIG_CMD_NFS=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_ETH=y +CONFIG_AG7XXX=y +CONFIG_CLK=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_ATH79_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h new file mode 100644 index 0000000..2b9e92e --- /dev/null +++ b/include/configs/tplink_wdr4300.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2016 Marek Vasut marex@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SYS_TEXT_BASE 0xa1000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MHZ 280 +#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 0x8000 +#define CONFIG_SYS_ICACHE_SIZE 0x10000 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_MALLOC_LEN 0x40000 +#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 + +#define CONFIG_SYS_SDRAM_BASE 0xa0000000 +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_CLK 40000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE \ + {9600, 19200, 38400, 57600, 115200} + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs" +#define CONFIG_BOOTCOMMAND \ + "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" +#define CONFIG_LZMA + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x10000 + +/* + * Command + */ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ +#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + /* Boot argument buffer size */ +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE /* Command auto complete */ +#define CONFIG_CMDLINE_EDITING /* Command history etc */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* USB, USB storage, USB ethernet */ +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_IS_TDI + +#define CONFIG_DOS_PARTITION + +/* + * Diagnostics + */ +#define CONFIG_SYS_MEMTEST_START 0x80100000 +#define CONFIG_SYS_MEMTEST_END 0x83f00000 +#define CONFIG_CMD_MEMTEST + +#define CONFIG_USE_PRIVATE_LIBGCC + +#define CONFIG_CMD_MII +#define CONFIG_PHY_GIGE + +#endif /* __CONFIG_H */
participants (2)
-
Daniel Schwierzeck -
Marek Vasut