From: David Brownell dbrownell@users.sourceforge.net

Minor cleanup for DaVinci NAND code:

- Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't be defined when there are multiple chipselect lines in use (as with common 2 GByte chips).

- Cleanup handling of EMIF control registers * Only need one pointer pointing to them * Remove incorrect and unused struct supersetting them

- Use the standard waitfunc; we don't need a custom version

- Partial legacy cleanup: * Don't initialize every board like it's a DM6446 EVM * #ifdef a bit more code for BROKEN_ECC

Sanity checked with small page NAND on dm355 and dm6446 EVMs; and large page on dm355 EVM (packaged as two devices, not one).

Signed-off-by: David Brownell dbrownell@users.sourceforge.net --- There are two remaining chipselect issues of note. First, this doesn't present the common "two chipselects per package" chips as one device, like Linux does. Second, the hardware ECC code assumes a specific DaVinci chipselect (with secondary chipselects driven by address lines) ... but e.g. the DM357 EVM uses two distinct hardware chipselects.

drivers/mtd/nand/davinci_nand.c | 55 +++++++++++------------------ include/asm-arm/arch-davinci/nand_defs.h | 54 ---------------------------- 2 files changed, 22 insertions(+), 87 deletions(-)

--- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -49,6 +49,8 @@

extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];

+static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE; + static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; @@ -115,34 +117,31 @@ static struct nand_ecclayout davinci_nan

static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) { - emifregs emif_addr; int dummy;

- emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - dummy = emif_addr->NANDF1ECC; - dummy = emif_addr->NANDF2ECC; - dummy = emif_addr->NANDF3ECC; - dummy = emif_addr->NANDF4ECC; + dummy = emif_regs->NANDF1ECC; +#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC + dummy = emif_regs->NANDF2ECC; + dummy = emif_regs->NANDF3ECC; + dummy = emif_regs->NANDF4ECC; +#endif

- emif_addr->NANDFCR |= (1 << 8); + /* FIXME: only chipselect 0 is supported for now */ + emif_regs->NANDFCR |= 1 << 8; }

static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) { u_int32_t ecc = 0; - emifregs emif_base_addr; - - emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;

if (region == 1) - ecc = emif_base_addr->NANDF1ECC; + ecc = emif_regs->NANDF1ECC; else if (region == 2) - ecc = emif_base_addr->NANDF2ECC; + ecc = emif_regs->NANDF2ECC; else if (region == 3) - ecc = emif_base_addr->NANDF3ECC; + ecc = emif_regs->NANDF3ECC; else if (region == 4) - ecc = emif_base_addr->NANDF4ECC; + ecc = emif_regs->NANDF4ECC;

return(ecc); } @@ -369,27 +368,21 @@ static int nand_davinci_correct_data(str

static int nand_davinci_dev_ready(struct mtd_info *mtd) { - emifregs emif_addr; - - emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - - return(emif_addr->NANDFSR & 0x1); -} - -static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this) -{ - while(!nand_davinci_dev_ready(mtd)) {;} - *NAND_CE0CLE = NAND_STATUS; - return(*NAND_CE0DATA); + return emif_regs->NANDFSR & 0x1; }

static void nand_flash_init(void) { + /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! + * Instead, have your board_init() set EMIF timings, based on its + * knowledge of the clocks and what devices are hooked up ... and + * don't even do that unless no UBL handled it. + */ +#ifdef CONFIG_SOC_DM6446 u_int32_t acfg1 = 0x3ffffffc; u_int32_t acfg2 = 0x3ffffffc; u_int32_t acfg3 = 0x3ffffffc; u_int32_t acfg4 = 0x3ffffffc; - emifregs emif_regs;

/*------------------------------------------------------------------* * NAND FLASH CHIP TIMEOUT @ 459 MHz * @@ -411,20 +404,17 @@ static void nand_flash_init(void) | (0 << 0 ) /* asyncSize 8-bit bus */ ;

- emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; - emif_regs->AWCCR |= 0x10000000; emif_regs->AB1CR = acfg1; /* 0x08244128 */; emif_regs->AB2CR = acfg2; emif_regs->AB3CR = acfg3; emif_regs->AB4CR = acfg4; emif_regs->NANDFCR = 0x00000101; +#endif }

int board_nand_init(struct nand_chip *nand) { - nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA; - nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA; nand->chip_delay = 0; nand->select_chip = nand_davinci_select_chip; #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT @@ -458,7 +448,6 @@ int board_nand_init(struct nand_chip *na nand->cmd_ctrl = nand_davinci_hwcontrol;

nand->dev_ready = nand_davinci_dev_ready; - nand->waitfunc = nand_davinci_waitfunc;

nand_flash_init();

--- a/include/asm-arm/arch-davinci/nand_defs.h +++ b/include/asm-arm/arch-davinci/nand_defs.h @@ -31,60 +31,6 @@ #define MASK_CLE 0x10 #define MASK_ALE 0x0a

-#define NAND_CE0CLE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x10)) -#define NAND_CE0ALE ((volatile u_int8_t *)(CONFIG_SYS_NAND_BASE + 0x0a)) -#define NAND_CE0DATA ((volatile u_int8_t *)CONFIG_SYS_NAND_BASE) - -typedef struct { - u_int32_t NRCSR; - u_int32_t AWCCR; - u_int8_t RSVD0[8]; - u_int32_t AB1CR; - u_int32_t AB2CR; - u_int32_t AB3CR; - u_int32_t AB4CR; - u_int8_t RSVD1[32]; - u_int32_t NIRR; - u_int32_t NIMR; - u_int32_t NIMSR; - u_int32_t NIMCR; - u_int8_t RSVD2[16]; - u_int32_t NANDFCR; - u_int32_t NANDFSR; - u_int8_t RSVD3[8]; - u_int32_t NANDF1ECC; - u_int32_t NANDF2ECC; - u_int32_t NANDF3ECC; - u_int32_t NANDF4ECC; - u_int8_t RSVD4[4]; - u_int32_t IODFTECR; - u_int32_t IODFTGCR; - u_int8_t RSVD5[4]; - u_int32_t IODFTMRLR; - u_int32_t IODFTMRMR; - u_int32_t IODFTMRMSBR; - u_int8_t RSVD6[20]; - u_int32_t MODRNR; - u_int8_t RSVD7[76]; - u_int32_t CE0DATA; - u_int32_t CE0ALE; - u_int32_t CE0CLE; - u_int8_t RSVD8[4]; - u_int32_t CE1DATA; - u_int32_t CE1ALE; - u_int32_t CE1CLE; - u_int8_t RSVD9[4]; - u_int32_t CE2DATA; - u_int32_t CE2ALE; - u_int32_t CE2CLE; - u_int8_t RSVD10[4]; - u_int32_t CE3DATA; - u_int32_t CE3ALE; - u_int32_t CE3CLE; -} nand_registers; - -typedef volatile nand_registers *nandregs; - #define NAND_READ_START 0x00 #define NAND_READ_END 0x30 #define NAND_STATUS 0x70