sending couple of DT patches to be in sync with Linux repository. There are still some changes but we are working on it to get them fully in sync for SystemReady IR certification.
Thanks, Michal
Harini Katakam (3): arm64: zynqmp: Assign TSU clock frequency for KR260 arm64: zynqmp: Increase reset assert time for TI SGMII PHY arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
Manikanta Guntupalli (1): xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Michal Simek (8): arm64: zynqmp: Fix gpio comment about No of gpios arm64: zynqmp: Record compatible string for kv260 rev2 arm64: zynqmp: Cover K24 revB/1 SOM arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 arm64: zynqmp: Sync node name address with reg (mailbox) arm64: zynqmp: Remove interrupt/reg-names for AMS arm64: zynqmp: Rename ams_ps/pl node names arm64: zynqmp: Remove clock-names from pcap node
Parth Gajjar (1): arm64: zynqmp: Update MALI 400 interrupt and clock names
Piyush Mehta (1): arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb
Radhey Shyam Pandey (2): arm64: zynqmp: Add L2 cache nodes arm64: zynqmp: add pmu interrupt-affinity
Varalaxmi Bingi (1): arm: xilinx: Setting default i2c clock frequency to 400kHz
arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynq-zc702.dts | 5 ++-- arch/arm/dts/zynqmp-clk-ccf.dtsi | 10 +++---- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 6 ++--- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 8 +++--- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 8 +++--- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 8 +++--- arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 +++--- arch/arm/dts/zynqmp-zcu100-revC.dts | 6 +++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 +-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 +-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +++---- arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +++---- arch/arm/dts/zynqmp.dtsi | 33 ++++++++++++++++-------- 28 files changed, 103 insertions(+), 79 deletions(-)
From: Varalaxmi Bingi varalaxmi.bingi@amd.com
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of 400kHz. Current default value is 100kHz.
Signed-off-by: Varalaxmi Bingi varalaxmi.bingi@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynqmp.dtsi | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 97a9e49a19c3..8c6eafec1d4e 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -153,6 +153,7 @@ clocks = <&clkc 38>; interrupt-parent = <&intc>; interrupts = <0 25 4>; + clock-frequency = <400000>; reg = <0xe0004000 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -164,6 +165,7 @@ clocks = <&clkc 39>; interrupt-parent = <&intc>; interrupts = <0 48 4>; + clock-frequency = <400000>; reg = <0xe0005000 0x1000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index c9640c44451f..5f1e163e87f2 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -611,6 +611,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 17 4>; + clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -622,6 +623,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 18 4>; + clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>;
From: Manikanta Guntupalli manikanta.guntupalli@amd.com
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by Linux. "enforced open drain please flag it properly in DT/ACPI DSDT/board file."
Signed-off-by: Manikanta Guntupalli manikanta.guntupalli@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynq-zc702.dts | 5 +++-- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 4 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 4 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 ++-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu100-revC.dts | 4 ++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 ++-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 ++-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu208-revA.dts | 8 ++++---- arch/arm/dts/zynqmp-zcu216-revA.dts | 8 ++++---- 18 files changed, 49 insertions(+), 48 deletions(-)
diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 27fb194fc9e2..8d47f24b757b 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" +#include <dt-bindings/gpio/gpio.h>
/ { model = "Xilinx ZC702 board"; @@ -102,8 +103,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio0 50 0>; - sda-gpios = <&gpio0 51 0>; + scl-gpios = <&gpio0 50 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio0 51 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index b185669b9c5e..11142401151f 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -131,8 +131,8 @@ &i2c0 { /* MIO 34-35 - can't stay here */ status = "okay"; clock-frequency = <400000>; - scl-gpios = <&gpio 34 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 34 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 35 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u94 */ compatible = "nxp,pca9548"; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 95347604a27b..5ac66bc1ec5f 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -68,8 +68,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 26ac540e7b0e..401de9efb913 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -68,8 +68,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 2b6c3946e858..8229244d241a 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -34,8 +34,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 308d7876b882..96a51219f425 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -28,8 +28,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e9ec4b79fc1f..4b88b57e0c2c 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -267,8 +267,8 @@ status = "okay"; bootph-all; clock-frequency = <400000>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index b663651583c3..cffad447406b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -118,8 +118,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index 9d0cf11665c6..bb0477825a93 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -109,8 +109,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u26: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 7f973fcf4da4..74a5b020e863 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -91,8 +91,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; };
&i2c1 { @@ -100,8 +100,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 116037dbe73f..78c325076006 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -188,8 +188,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 8823eb2462e4..79d67c495dee 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -232,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -496,8 +496,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 92e01ac921e3..90fbfca87f2b 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -139,8 +139,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index c61d8b15ee23..69470f8dede3 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -144,8 +144,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 67775eceaa84..7a8094a16b79 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -232,8 +232,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -495,8 +495,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
/* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 7fc1aa238a60..c9ff99f8a830 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -204,8 +204,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u22: gpio@20 { compatible = "ti,tca6416"; @@ -384,8 +384,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 1fac632d6317..5ad07d30b8bc 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -231,8 +231,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; @@ -397,8 +397,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */ diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index ea96f5c80141..574e4845be8f 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -241,8 +241,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
tca6416_u15: gpio@20 { /* u15 */ compatible = "ti,tca6416"; @@ -407,8 +407,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-mux@74 { compatible = "nxp,pca9548"; /* u20 */
From: Parth Gajjar parth.gajjar@amd.com
Motivation for the commit is to utilize the upstream community device tree so that the either modified ARM Mali 400 driver or upstream lima driver can be used.
Signed-off-by: Parth Gajjar parth.gajjar@amd.com Signed-off-by: Vishal Sagar vishal.sagar@amd.com Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.... Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 2 +- arch/arm/dts/zynqmp.dtsi | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 173e4bc5f1d8..4d44924f6633 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -126,7 +126,7 @@ };
&gpu { - clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>; + clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>; };
&lpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 5f1e163e87f2..38114d55386b 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -396,12 +396,12 @@
gpu: gpu@fd4b0000 { status = "disabled"; - compatible = "arm,mali-400", "arm,mali-utgard"; + compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; - interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; - clock-names = "gpu", "gpu_pp0", "gpu_pp1"; + interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; + clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; };
From: Harini Katakam harini.katakam@amd.com
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KR260 CC to allow PTP functionality.
Signed-off-by: Harini Katakam harini.katakam@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ++++ arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 ++ arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 ++ 3 files changed, 8 insertions(+)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 4d44924f6633..a21dca87d248 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -169,24 +169,28 @@ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; };
&gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; };
&gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; };
&gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; };
&gpio { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index 5ac66bc1ec5f..caaf71d729e4 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; };
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>;
mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index 401de9efb913..f9d87559a719 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -188,6 +188,7 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma; + assigned-clock-rates = <250000000>; };
&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ @@ -196,6 +197,7 @@ pinctrl-0 = <&pinctrl_gem1_default>; phy-handle = <&phy1>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>;
mdio: mdio { #address-cells = <1>;
There are total 174 gpios but from 0 - 173 that's why fix comment to reflect it.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index e287a9b6591c..1b247bfa8944 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -131,7 +131,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO34/35 */ diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index e24d070adb69..bf6ffb778b6a 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -201,7 +201,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 11142401151f..d5cfc61faf71 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -125,7 +125,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index aa4f7c23ede5..97500b132876 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -154,7 +154,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index 7aa8c2b4d1f6..3bdcf052a555 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -149,7 +149,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 459736abe6bc..9a693a57a932 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -149,7 +149,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index d5f4a16f20eb..16691a85e158 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -134,7 +134,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { /* MIO 34-35 - can't stay here */ diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 4b88b57e0c2c..d718fec76065 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -363,7 +363,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&xilinx_ams { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 5ad07d30b8bc..9b3ae67bff12 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -222,7 +222,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&i2c0 { diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 574e4845be8f..43eeaec5b15b 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -228,7 +228,7 @@ "", "", "", "", "", /* 155 - 159 */ "", "", "", "", "", /* 160 - 164 */ "", "", "", "", "", /* 165 - 169 */ - "", "", "", ""; /* 170 - 174 */ + "", "", "", ""; /* 170 - 173 */ };
&gpu {
From: Harini Katakam harini.katakam@amd.com
Increase reset assert time for TI SGMII PHY on KR260 CC starting 6.1 kernel. This PHY does not come out of reset with the existing 100us pulse width as per testing on multiple carrier cards. The reset is driven via a PCA9570 I2C expander. The expander driver was updated to an upstream version in 6.1 where gpio_chip _set was optimized. Delays in earlier kernels may have masked this issue. This is a safe workaround value for assert pulse width before the discussions are resolved with TI.
Signed-off-by: Harini Katakam harini.katakam@amd.com Reviewed-by: Radhey Shyam Pandey radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts index caaf71d729e4..d318773bd9d6 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -210,7 +210,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts index f9d87559a719..69dba0761b37 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -210,7 +210,7 @@ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,dp83867-rxctrl-strap-quirk; - reset-assert-us = <100>; + reset-assert-us = <300>; reset-deassert-us = <280>; reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; };
From: Harini Katakam harini.katakam@amd.com
Set TSU clock frequency as 250MHz (minimum when running at 1G) on KV and KD carrier cards to allow PTP functionality.
Signed-off-by: Harini Katakam harini.katakam@amd.com Reviewed-by: Radhey Shyam Pandey radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 1 + arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 8229244d241a..a81b3f6f51ad 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -165,6 +165,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>;
mdio: mdio { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 96a51219f425..0ac20869b37d 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -152,6 +152,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>;
mdio: mdio { #address-cells = <1>;
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335 autofocus feature). PS side is completely unchanged.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts index 0ac20869b37d..f935f25c887f 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts @@ -16,7 +16,8 @@ /plugin/;
&{/} { - compatible = "xlnx,zynqmp-sk-kv260-rev1", + compatible = "xlnx,zynqmp-sk-kv260-rev2", + "xlnx,zynqmp-sk-kv260-rev1", "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp"; model = "ZynqMP KV260 revB";
Extend compatible versions for K24 SOM. Changes are not affecting SW behavior that's why all versions are compatible to each other. Describing all revisions is done by purpose because user space SW is reading compatible string for logic around DT overlays and bitstreams.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts index 24514409cb9e..653bd9362264 100644 --- a/arch/arm/dts/zynqmp-sm-k24-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -11,8 +11,9 @@ #include "zynqmp-sm-k26-revA.dts"
/ { - model = "ZynqMP SM-K24 RevA"; - compatible = "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", + model = "ZynqMP SM-K24 RevA/B/1"; + compatible = "xlnx,zynqmp-sm-k24-rev1", "xlnx,zynqmp-sm-k24-revB", + "xlnx,zynqmp-sm-k24-revA", "xlnx,zynqmp-sm-k24", "xlnx,zynqmp";
memory@0 {
The commit a4180c369607 ("arm64: zynqmp: Add mode-pin GPIO controller DT node") added usb phy reset over bootmode pins by default on usb0 only. zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744 hub which is used only in host mode. Especially this chip requires reset to operate properly that's why better assign gpio reset to usb1 instead of usb0. Without this change usb start crashed when runs.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-zcu100-revC.dts | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 78c325076006..a84cd86694e2 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -569,6 +569,7 @@ pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 0>; + /delete-property/ reset-gpios; };
&dwc3_0 { @@ -584,6 +585,7 @@ pinctrl-0 = <&pinctrl_usb1_default>; phy-names = "usb3-phy"; phys = <&psgtr 3 PHY_TYPE_USB3 1 0>; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; };
&dwc3_1 {
From: Radhey Shyam Pandey radhey.shyam.pandey@amd.com
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache node and let each CPU point to it.
Reported-by: John Toomey john.toomey@amd.com Signed-off-by: Radhey Shyam Pandey radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 38114d55386b..59b52919f130 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -33,6 +33,7 @@ operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; };
cpu1: cpu@1 { @@ -42,6 +43,7 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; };
cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; };
cpu3: cpu@3 { @@ -60,6 +63,13 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; };
idle-states {
Address in node name should match with the first reg property in DT.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 59b52919f130..b9cfd562c913 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -121,7 +121,7 @@ #size-cells = <2>; ranges;
- ipi_mailbox_pmu1: mailbox@ff990400 { + ipi_mailbox_pmu1: mailbox@ff9905c0 { bootph-all; reg = <0x0 0xff9905c0 0x0 0x20>, <0x0 0xff9905e0 0x0 0x20>,
From: Radhey Shyam Pandey radhey.shyam.pandey@amd.com
Explicitly specify interrupt affinity to avoid HW perfevents need to guess. This avoids the following error upon linux boot: armv8-pmu pmu: hw perfevents: no interrupt-affinity property, guessing.
Reported-by: John Toomey john.toomey@amd.com Signed-off-by: Radhey Shyam Pandey radhey.shyam.pandey@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b9cfd562c913..11eaf4b6a193 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -149,6 +149,10 @@ <0 144 4>, <0 145 4>, <0 146 4>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; };
psci {
From: Piyush Mehta piyush.mehta@amd.com
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk' quirk for usb. This quirk is no more available in linux after the xilinx release 2022.2.
This functionality is taken care of by the 'snps,resume-hs-terminations' quirk.
Signed-off-by: Piyush Mehta piyush.mehta@amd.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 11eaf4b6a193..223cdab5f93d 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -892,7 +892,6 @@ iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations; @@ -924,7 +923,6 @@ iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_resume_quirk; snps,enable_guctl1_ipd_quirk; snps,xhci-stream-quirk; snps,resume-hs-terminations;
These two properties are not described in DT binding and also not used by driver that's why remove them.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 223cdab5f93d..299ad1e7c039 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -954,9 +954,7 @@ status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 56 4>; - interrupt-names = "ams-irq"; reg = <0x0 0xffa50000 0x0 0x800>; - reg-names = "ams-base"; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>;
Fix child node names to be aligned with dt-binding available in the Linux kernel which requires names as ams-ps@ and ams-pl@.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 299ad1e7c039..6228149b886e 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -960,13 +960,13 @@ #io-channel-cells = <1>; ranges = <0 0 0xffa50800 0x800>;
- ams_ps: ams_ps@0 { + ams_ps: ams-ps@0 { compatible = "xlnx,zynqmp-ams-ps"; status = "disabled"; reg = <0x0 0x400>; };
- ams_pl: ams_pl@400 { + ams_pl: ams-pl@400 { compatible = "xlnx,zynqmp-ams-pl"; status = "disabled"; reg = <0x400 0x400>;
Clock is not used in driver and also not described in binding.
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4 ---- arch/arm/dts/zynqmp.dtsi | 1 - 2 files changed, 5 deletions(-)
diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index a21dca87d248..1ae8ea2e43f7 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -289,10 +289,6 @@ clocks = <&zynqmp_clk AMS_REF>; };
-&zynqmp_pcap { - clocks = <&zynqmp_clk PCAP>; -}; - &zynqmp_dpdma { clocks = <&zynqmp_clk DPDMA_REF>; assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */ diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6228149b886e..1632be843b15 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -193,7 +193,6 @@
zynqmp_pcap: pcap { compatible = "xlnx,zynqmp-pcap-fpga"; - clock-names = "ref_clk"; };
xlnx_aes: zynqmp-aes {
On 7/10/23 14:37, Michal Simek wrote:
sending couple of DT patches to be in sync with Linux repository. There are still some changes but we are working on it to get them fully in sync for SystemReady IR certification.
Thanks, Michal
Harini Katakam (3): arm64: zynqmp: Assign TSU clock frequency for KR260 arm64: zynqmp: Increase reset assert time for TI SGMII PHY arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
Manikanta Guntupalli (1): xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Michal Simek (8): arm64: zynqmp: Fix gpio comment about No of gpios arm64: zynqmp: Record compatible string for kv260 rev2 arm64: zynqmp: Cover K24 revB/1 SOM arm64: zynqmp: Fix usb reset over bootmode pins on zcu100 arm64: zynqmp: Sync node name address with reg (mailbox) arm64: zynqmp: Remove interrupt/reg-names for AMS arm64: zynqmp: Rename ams_ps/pl node names arm64: zynqmp: Remove clock-names from pcap node
Parth Gajjar (1): arm64: zynqmp: Update MALI 400 interrupt and clock names
Piyush Mehta (1): arm64: zynqmp: remove snps,enable_guctl1_resume_quirk quirk for usb
Radhey Shyam Pandey (2): arm64: zynqmp: Add L2 cache nodes arm64: zynqmp: add pmu interrupt-affinity
Varalaxmi Bingi (1): arm: xilinx: Setting default i2c clock frequency to 400kHz
arch/arm/dts/zynq-7000.dtsi | 2 ++ arch/arm/dts/zynq-zc702.dts | 5 ++-- arch/arm/dts/zynqmp-clk-ccf.dtsi | 10 +++---- arch/arm/dts/zynqmp-dlc21-revA.dts | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 6 ++--- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 2 +- arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 8 +++--- arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 8 +++--- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sck-kv-g-revB.dts | 8 +++--- arch/arm/dts/zynqmp-sm-k24-revA.dts | 5 ++-- arch/arm/dts/zynqmp-sm-k26-revA.dts | 6 ++--- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts | 4 +-- arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts | 8 +++--- arch/arm/dts/zynqmp-zcu100-revC.dts | 6 +++-- arch/arm/dts/zynqmp-zcu102-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu104-revA.dts | 4 +-- arch/arm/dts/zynqmp-zcu104-revC.dts | 4 +-- arch/arm/dts/zynqmp-zcu106-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu111-revA.dts | 8 +++--- arch/arm/dts/zynqmp-zcu208-revA.dts | 10 +++---- arch/arm/dts/zynqmp-zcu216-revA.dts | 10 +++---- arch/arm/dts/zynqmp.dtsi | 33 ++++++++++++++++-------- 28 files changed, 103 insertions(+), 79 deletions(-)
Applied and also fix subject for this cover letter just in reply.
M
participants (1)
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Michal Simek